Abstract: Methods of manufacturing semiconductor devices having low resistance reduced channel length transistors. Spacers are formed on each side of trenches that define the location of transistor channels. The spacers are formed with a dimension between the spacers that is less than a dimension available from photolithography systems currently available. A layer of gate oxide and a polysilicon gate are formed within the dimension resulting in transistors having channels length less than that available from standard photolithographic methods of forming gates and channels.

Abstract: The semiconductor device has a trench isolation between a P-well and N-well. This trench isolation region is formed of oxide which during the course of the formation of the P and N well is doped with P-type and N-type dopants. Thus the trench has a P-type doped region and an N-type doped region which are typically phosphorous and boron. After the P and N well are formed, a rapid thermal anneal is applied to the device structure. This has the effect of causing the phosphorous doped and boron doped portions of the trench oxide to be etched at substantially the same rate. After this RTA step, gate oxide is formed over the P and N well. The following formation of polysilicon gates results in a relatively flat gate over transistor structure. This avoids corner leakage which is a problem with trench isolation.

Abstract: A semiconductor memory device has a silicon substrate 10. A first embedded layer 11 is formed in the silicon substrate 10 under a p-well 18 in an area below a region where a drain 36 of a driver transistor 30 is located. The first embedded layer 11 makes a junction with the p-well 18. Also, the first embedded layer 11 is formed below an n-well 16 and contacts the n-well 16. When the drain 36 of the driver transistor 30 is at a voltage of 3V, &agr;-ray may pass through the p-well 18, the first embedded layer 11 and the silicon substrate 10. As a result, electron-hole pairs are cut. Due to the presence of the p-n junction that is formed by the p-well 18 and the first embedded layer 11, only electrons in the p-well 18 are drawn to the drain 36. As a result, a fall in the drain voltage of 3V is reduced. As a consequence, the device structure makes it difficult to destroy retained data.

Abstract: A method for forming a CMOS transistor gate with a self-aligned. channel implant. A semiconductor structure having a first active area is provided. A first insulating layer is formed on the semiconductor structure, and a second insulating layer is formed on the first insulating layer. The second insulating layer is patterned using a poly reverse mask and an etch selective to the first insulating layer to form a first channel implant opening, and the poly reverse mask is removed. A first channel implant mask is formed exposing the first channel implant opening. Impurity ions are implanted through the first channel implant opening to form a first threshhold adjust region and a first anti-punchthrough region. A gate layer is formed over the semiconductor structure, and the first gate layer is planarized to form a gate electrode. The second insulating layer is removed, and lightly doped source and drain regions, sidewall spacers and source and drain regions can be formed adjacent the gate electrode.

Abstract: MOSFETS are formed by implanting at least a portion of a semiconductor substrate with a depart of a first type to form a first well region, annealing the first well region, implanting the annealed first well region with nitrogen; forming a gate insulator above at least a portion of the first well region; and providing a gate electrode above the gate oxide and providing source/drain regions in the substrate below the gate oxide about the gate electrode.

Abstract: A semiconductor device has, in one embodiment, two wells of different conductivity types formed in a semiconductor substrate. The two wells are arranged to be adjacent to each other to form a junction therebetween. A field oxide film is formed to cover the junction at a main surface of the semiconductor substrate. Other field oxide films or field-shield isolation structures may be formed to isolate circuit elements from one another in the wells.

Abstract: Embodiments in accordance with the present invention provide methods of forming a dual gated semiconductor-on-insulator (SOI) device. Such methods encompass forming a first transistor structure operatively adjacent a first side of the semiconductor layer of an SOI substrate. Insulator layer material is removed from the second side of the semiconductor layer, between the source/drain contact structures of the first transistor structure and a second transistor structure there formed operatively adjacent the second side of the semiconductor layer and aligned to the first transistor structure.

Abstract: A method of reducing the capacitance of a conductive layer and a semiconductor obtained thereby. In the method, a well region is formed below the isolation, adjacent to it, an in a floating form. The well region has a dopant type different than the dopant type of the substrate. A depletion region can be formed at the interface between the floating well and the substrate. By connecting the capacitance of the depletion region and the parasitic capacitance generated between the conductive layer and the floating well in series, the total parasitic capacitance of the conductive layer can be reduced so as to increase the operational speed of the device.

Abstract: A method of forming a semiconductor device with improved leakage control, includes: providing a semiconductor substrate; forming a trench in the substrate; forming a leakage stop implant in the substrate under the bottom of the trench and under and aligned to a sidewall of the trench; filling the trench with an insulator; and forming an N-well (or a P-well) in the substrate adjacent to and in contact with an opposite sidewall of the trench, the N-well (or the N-well) extending under the trench and forming an upper portion of an isolation junction with the leakage stop implant, the upper portion of the isolation junction located entirely under the trench. The leakage control implant is self-aligned to the trench sidewalls.

Abstract: A method for fabricating an SRAM device having a standard well tub, where an additional well tub is deposited within the standard well tub. In this manner, the dopant concentration is increased in the well area of the SRAM device, which increases both the isolation punchthrough tolerance and the SER immunity of the device. The additional well tub is deposited to a depth that is shallower than the standard well tub. The additional well tub is deposited using an ion implantation process using the same mask set as that used for the threshold voltage adjustment deposition. Thus, no additional mask layer is required to deposit the additional well tub, and the all of the expenses normally associated with an additional mask layer are avoided.

Abstract: An improved method of making CMOS surface channel transistors using fewer masking steps. In-situ doped poly silicon deposition can be used to reduce problems with poly depletion effects in transistor gates. In addition, using this method, the number of layers in each gate dielectric, the dielectric type, and dielectric thickness between n-channel and p-channel devices can be separately controlled. This method also allows the use of a lithography mask normally used to fabricate buried channel devices for use in fabricating surface channel devices, thus saving the manufacture of an additional mask.

Abstract: A method of forming an integrated circuit dual gate structure using only one mask is disclosed. In one embodiment, a substrate is prepared for the fabrication of a dual gate structure, a first gate structure having an NWELL is formed without using a mask, and a second gate structure having a PWELL is formed using only one mask. In an alternate embodiment, a substrate is prepared for the fabrication of a dual gate structure, a first gate structure having a PWELL is formed without using a mask, and a second gate structure having an NWELL is formed using only one mask.

Abstract: A CMOS device which includes first and second wells formed in first and second regions of a semiconductor substrate, respectively, first and second transistors formed in the respective wells, a third transistor formed in a third region of the semiconductor substrate outside of the wells, a first impurity layer formed in the vicinity of the depletion region of at least one but not more than two of the first, second, and third regions, and a second impurity layer deeper than the first impurity layer and formed in the region(s) of the substrate in which the first impurity layer is not formed. A method for manufacturing such a CMOS device enables the punch-through voltage characteristics of the first, second, and third transistors to be optimally different, without necessitating any additional, separate mask processing steps.

Abstract: The present invention relates to a transistor in a semiconductor device and method of manufacturing the same, more particularly to a new dual gate P+ salicide forming technology having an elevated channel and a source/drain using the selective SiGe epi-silicon growth technology.

Abstract: For use with sub-micron CMOS technologies, a gate etch process improves control of the etch profile. Gate stacks utilize N-type or P-type doped amorphous or poly silicon to enhance device performance. However, the different etching characteristics of the N-type versus the P-type amorphous or poly silicon material can result in a localized breakthrough of the underlying thin gate oxide adjacent to the edge of the gate stack, especially in the N doped active regions. According to one example embodiment, this localized breakthrough (“microtrenching”) is avoided by building the gate stacks with undoped amorphous or poly silicon to the desired configuration, masking the gate stacks with a dielectric layer, planarizing the dielectric layer and then implanting the N-type or P-type species into the selected gate stack.

Abstract: A halo implant (42, 44) for an MOS transistor (10) is formed in a semiconductor substrate (12) at a shallow implant angle, relative to normal to the substrate surface (29). A polysilicon gate structure (32, 33) is formed over a gate oxide (28) and then a hard mask (70), such as a TEOS-generated layer of silicon oxide, is deposited on an upper surface (68) of the gate. The mask is etched with a blanket anisotropic etch to form a cap-shaped mask (72). The shape of the cap causes the dopant for the halo implant to penetrate to a depth which follows the contour of the cap. Thus, halo implants may be formed which extend under the gate structure without the need for large angle implants and resultant shadowing problems caused by adjacent devices.

Abstract: First and second circuit blocks are provided in a semiconductor device. The first circuit block is provided with a first complementary MOS transistor including a first P-channel MOS transistor and a first N-channel MOS transistor. The second circuit block is provided with a second complementary MOS transistor including a second P-channel MOS transistor and a second N-channel MOS transistor. The threshold voltages of the first P-channel MOS transistor and the first N-channel MOS transistor are set to be higher than those of the second P-channel MOS transistor and the second N-channel MOS transistor. A gate leakage current of the first N-channel MOS transistor in a stand-by state is set to be substantially equal to that of the first P-channel MOS transistor.

Abstract: A high-voltage device. A substrate has a first conductive type. A first well region with the first conductive type is located in the substrate. A second well region with the second conductive type is located in the substrate but is isolated from the first well region. Several field oxide layers are located on a surface of the second well region. A shallow trench isolation is located between the field oxide layers in the second well region. A first doped region with the second conductive type is located beneath the field oxide layers. A second doped region with the first conductive type is located beneath the shallow trench isolation in the second well region. A third well region with the first conductive type is located in the first well region and expands from a surface of the first well region into the first well region. A gate structure is positioned on the substrate between the first and the second well regions and covers a portion of the first, the third well regions and the field oxide layers.

Abstract: A solid imaging device including: a semiconductor substrate of a first conductivity type; a layer of a second conductivity type formed on a surf ace of the semiconductor substrate, the layer at least including a photosensitive portion of the second conductivity type; and a MOS transistor of the second conductivity type coupled to the photosensitive portion, wherein the solid imaging device further includes a layer of the first conductivity type in at least a channel region of the MOS transistor of the second conductivity type, the layer of the first conductivity type having an impurity concentration which is higher than an impurity concentration of the semiconductor substrate, and wherein at least a portion of a boundary of the layer of the second conductivity type is in direct contact with the semiconductor substrate.

Abstract: A method of selective formation of SiN layer in a semiconductor device comprising the following steps. A semiconductor structure having at least one PMOS transistor and one NMOS transistor formed therein is provided. The PMOS and NMOS transistors each have source/drain regions, a gate, and salicide contact regions. An undoped silicate glass (USG) layer is deposited over the semiconductor structure and the PMOS and NMOS transistors. An H2-rich PECVD silicon nitride layer is deposited over the undoped silicate glass layer and over the PMOS and NMOS transistors. The H2-rich PECVD silicon nitride layer is patterned, etched, and removed from over the PMOS transistor. An inter-level dielectric (ILD) layer is formed over the structure. The ILD layer is densified whereby hydrogen diffuses from the H2-rich PECVD silicon nitride layer overlying the NMOS transistor into the source/drain of the NMOS transistor.

Abstract: In a semiconductor memory device, first and second impurity regions of a second conductivity are provided as wells in a semiconductor substrate of a first conductivity. Outside of the first and second impurity regions, third impurity regions of the first conductivity are provided as wells in the substrate. Fourth impurity regions of the first conductivity are provided as wells in the first impurity regions. The first impurity regions each have an impurity concentration which gradually decreases with increasing depth below the top surface of the semiconductor substrate, and the fourth impurity regions have at least two impurity concentration peaks below the top surface of the semiconductor substrate. A memory cell can be reliably erased by forming a retrograde pocket well for a memory cell array, and a diffusion well surrounding the pocket well, thus maintaining a high breakdown voltage between the pocket well and the substrate.

Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS.FETs.

Abstract: An electro-static discharge (ESD) circuit of a semiconductor device, a structure thereof and a method for fabricating the ESD structure are provided. In the ESD circuit, a gate electrode and a drain region of a MOS transistor are connected to an electrical signal pad, and a Zener diode is connected to a source region of the MOS transistor. A threshold voltage of the MOS transistor is higher than an operating voltage of an internal circuit and lower than a drain junction breakdown voltage of a MOS transistor constituting the internal circuit. Also, instead of using a Zener diode for each signal pad, a common diode having a maximized junction area can be shared by a plurality of signal pads.

Abstract: A method for incorporating an ion implanted channel stop layer under field isolation for a twin-well CMOS process is described in which the layer is placed directly under the completed field isolation by a blanket boron ion implant over the whole wafer. The channel stop implant follows planarization of the field oxide and is thereby essentially at the same depth in both field and active regions. Subsequently implanted p- and n-wells are formed deeper than the channel stop layer, the n-well implant being of a sufficiently higher dose to over compensate the channel stop layer, thereby removing it's effect from the n-well. A portion of the channel stop implant under the field oxide adjacent the p-well provides effective anti-punchthrough protection with only a small increase in junction capacitance. The method is shown for, and is particularly effective in, processes utilizing shallow trench isolation.

Abstract: An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a first polysilicon gate, wherein the first polysilicon gate has sidewalls with sloped profiles and the sloped profiles are used as masks during the ion implantation of the LDD structures to space the resultant LDD structures away from the edges of second polysilicon gates to be formed subsequently with substantially vertical profiles.

Abstract: To reduce p-n junction leakage at the boundary between lightly doped wells formed in lightly doped bulk materials, a high concentration region is implanted at the junction. The high concentration region contains a relatively high dopant level, and thus reduces the width of the depletion region at the junction. The reduced width of the depletion region in turn reduces junction leakage.

Abstract: A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N+ and P+ diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N+ diffusion to said P+ diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P+ diffusion is formed in the N well in the pillar adjacent the distal end and a N+ diffusion is formed in the P well in the pillar adjacent the distal end.

Abstract: A process for manufacturing deep well junction structures that includes in succession, the steps of: on a first substrate having a first conductivity type and a first doping level, growing an epitaxial layer having the first conductivity type and a second doping level lower than the first doping level; anisotropically etching the epitaxial layer using a mask to form trenches; forming deep conductive regions surrounding the trenches and having a second conductivity type, opposite to the first conductivity type and the second doping level; and filling the trenches. The deep conductive regions are formed by angular ionic implantation and subsequent diffusion of a doping ion species within the epitaxial layer.

Abstract: Wells of n- and p-type are formed in a p-type substrate. Wells of p-type are also formed in the n-type well. Both the p-type wells are formed by the same process at the same time to make MOS transistors have different threshold voltages. MOS transistors having a long gate length and a low threshold voltage are formed in the p-well in the n-well, and MOS transistors having a short gate length and a high threshold voltage are formed in the p-well at the outside of the n-well. Fuses are formed over the p-type wells in the n-type well at a high density.

Abstract: An objective of the present invention is to realize a comparator which uses MOS transistors and has a reduced offset voltage and occupies a small surface area. This is characterized in that an impurity is introduced into a channel region of a MOS transistor, the mobility of a load side MOS transistor is made smaller than the mobility of a differential side MOS transistor, and the mutual conductance of the load side MOS transistor is made smaller than the mutual conductance of the differential side MOS transistor.

Abstract: A method for fabricating a semiconductor device. A shallow trench isolation is formed by forming a well region, a gate oxide layer and a wiring layer prior to forming a trench in the substrate. The trench is then filled with silicon oxide layer doped with germanium, nitrogen, titanium or other refractory metal. In addition, a MOS device is also fabricated with a gate buried in the substrate with a shallow trench isolation filled with the doped silicon oxide layer formed therein.

Abstract: A method for manufacturing a CMOS sensor comprises the steps of providing a substrate having a first conductive type, wherein the substrate comprises an isolation region, an active region, a gate structure on the active region and a source/drain region having a second conductive type in the substrate. A patterned photoresist is formed over the substrate. A first doped region having the second conductive type is formed across a portion of the source/drain region and extends from the surface of the substrate into the substrate. A second doped region having the first conductive type is formed to wrap the first doped region in the substrate. A third doped region having the second conductive type is formed under the second doped region. A fourth doped region having the first conductive type is formed under the third doped region. The patterned photoresist is removed.

Abstract: A method and structure for improving the latch-up characteristic of semiconductor devices is provided. A dual depth STI is used to isolate the wells from each other. The trench has a first substantially horizontal surface at a first depth and a second substantially horizontal surface at a second depth which is deeper than the first depth. The n- and p-wells are formed on either side of the trench. A highly doped region is formed in the substrate underneath the second substantially horizontal surface of the trench. The highly doped region abuts both the first and the second wells and extends the isolation of the trench.

Abstract: A semiconductor integrated circuit comprises a substrate (1) of a first conduction type semiconductor material, an epitaxial layer (10) which is carried by the substrate (1) and which is of a second conduction type semiconductor material different to the first conduction type material, a well (3) of semiconductor material in the epitaxial layer and a semiconductor material, the epitaxial layer (10) being substantially depleted of charges is a region substantially beneath the well (3).

Abstract: The present invention relates to a well-drive process in which the process of well driving is carried out simultaneously with a densification cycle. The inventive method is particularly applicable to isolation trenches having widths at or below about 0.2 microns. The inventive method may be applied to other semiconductive structures of varying geometries.

Abstract: Provided with a semiconductor device which is adopted to reduce the resistance of a well without the need to increase the concentration of dopants in forming the well by depositing conductive layer patterns and then growing an epitaxial layer on the conductive layer patterns, the semiconductor device including: conductive layer patterns formed on a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate and the conductive layer patterns; well regions formed in the semiconductor layer and the semiconductor substrate such that the conductive layer patterns are positioned at the bottoms of the well regions; and gate and source/drain electrodes formed on the well regions, and a method for fabricating the semiconductor device including the steps of: forming conductive layer patterns on a semiconductor substrate; forming a semiconductor layer on the semiconductor substrate including the conductive layer patterns; forming well regions in the semiconductor layer and the semiconductor subs

Abstract: A twin-well CMOS integrated circuit device includes an n-well region and a p-well region. Each of the n-well and p-well region includes spaced-apart regions which serve as drain and source regions, a channel region between the spaced-apart regions, a shallow trench isolation structure contiguous with one of the spaced-apart regions, and a doped diffused region extending from the surface of the well region, around and underneath the trench isolation structure, to a region beneath the contiguous spaced-apart region.

Abstract: A semiconductor substrate having an n-well region, a p-well region and shallow trench isolation (STI) regions is provided. Poly-gates are formed over the n-well region and p-well region respectively. First, nitrogen oxide (such as NO, N2O) layer are formed on surface of the aforesaid structure by furnace or rapid thermal oxidation (RTO). A photoresist layer is formed over the p-well region, and then BF2 or boron ion implantation is carried out to form a nitrogen oxide (such as NO, N2O) layer having boron ion in the n-well region. Another photoresist layer is formed over the n-well region after removing the photoresist layer. Arsenic ion implantation is then carried out to form a nitrogen oxide (such as NO, N2O) layer having arsenic ion in the p-well region. Next, spacer is formed on the sidewall of gates after removing the photoresist layer. Finally, deep source/drain implantation are carried out once again.

Abstract: A method of fabricating a transistor, comprising the following steps. A silicon semiconductor structure having spaced, raised, wedge-shaped dielectric isolation regions defining an active region there between is provided. Epitaxial silicon is grown over the active area to form an SEG region. A dummy gate is formed over the SEG region. Raised epitaxial silicon layers are grown over the SEG region adjacent the dummy gate. The dummy gate is removed, exposing the interior side walls of the raised epitaxial silicon layers. Sidewall spacers are formed on the exposed sidewalls of the raised epitaxial silicon layers. A gate oxide layer is grown over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. A layer of polysilicon is deposited over the structure and is planarized to form a gate conductor over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. The sidewall spacers are removed.

Abstract: Methods are described to prevent the inherent latchup problem of CMOS transistors in the sub-quarter micron range. Latchup is avoided by eliminating the low resistance between the Vdd and Vss power rails caused by the latchup of parasitic and complementary bipolar transistor structure that are present in CMOS devices. These goals have been achieved without the use of guard rings by using a deep n-well to disconnect the pnp collector to npn base connection of two parasitic bipolar transistors, and by using a buried p-well to disconnect the npn collector to pnp base connection of those same two parasitic transistors. Further, the deep n-well is shorted to a supply voltage Vdd, and the buried p-well is shorted to a reference voltage Vss via both the P substrate and a P+ ground tab. The proposed methods do not require additional mask or processes.

Abstract: A method of fabricating a CMOS transistor using Si—B layer to form a source/drain extension junction is disclosed. The fabrication includes the steps as follows; First, a p-type semiconductor substrate and an n-well region are provided. Afterwards, a shallow trench isolation (STI) is formed into the p-type semiconductor substrate and the n-well region, thereby forming a plurality of active regions therebetween. A channel is formed into the p-type semiconductor substrate and the n-well region. Then, a PMOSFET gate pattern and an NMOSFET gate pattern are formed over the p-type semiconductor substrate and the n-well region. A first defined photoresist layer is formed over the n-well region. Afterwards, the n−-type dopant is implanted into the p-type semiconductor substrate to form an n−-type lightly doped source/drain. Then the first defined photoresist layer is removed. A first dielectric layer is deposited over the p-type semiconductor substrate and the n-well region.

Abstract: The present invention is about a single side high voltage lateral diffused metal-oxide-semiconductor (LDMOS) transistor. The drain side is low-voltage N-well with lower concentration to increase driving voltage while the source side is low-voltage P-well with higher concentration to increase the interior electric field such that the conductivity is improved and the threshold voltage is adjusted by high-voltage P-well with lower concentration.

Abstract: A twin-well CMOS integrated circuit device includes an n-well region and a p-well region. Each of the n-well and p-well region includes spaced-apart regions which serve as drain and source regions, a channel region between the spaced-apart regions, a shallow trench isolation structure contiguous with one of the spaced-apart regions, and a doped diffused region extending from the surface of the well region, around and underneath the trench isolation structure, to a region beneath the contiguous spaced-apart region.

Abstract: A method for fabricating a mask comprises a first pattern in respective of active areas, and a second pattern in respective of dummy active areas. After removing the first pattern, the profiles of the dummy active areas are enlarged. The N-well boundary and the P-well boundary of the second pattern is respectively shielded to form a first composed pattern and a second composed pattern comprising the larger dummy active areas and a shielding pattern. The dummy active areas on the substrate are shielded by the patterns of the embodiment during the process of ion implantation. Thus the resistivity of the dummy active areas is increased, whereby the parasitic capacitance can be prevented from being too large and affecting the performance of the devices.

Abstract: This invention proposes a process to form planarized twin-wells for CMOS devices. After depositing pad oxide and a silicon nitride layers, a high-energy phosphorus ion implantation is performed to form the N-well by using a photoresist as a mask. A thick oxide layer deposited by liquid phase deposition process is then grown on the N-well region part of the silicon nitride layer, but not on the photoresist. After stripping the photoresist, a high-energy boron ion implantation is carried out to form the P-well by using the LPD-oxide layer as a mask. The thick LPD-oxide layer is removed by BOE or HF solution. Trenched isolation regions are formed to isolate and define active regions. After removing the pad oxide and the silicon nitride layer, the CMOS device is fabricated by standard processes.

Abstract: A method of forming a semiconductor memory device formed on a semiconductor substrate with an N-well and a P-well comprises the following steps. Form over a substrate the combination of a gate oxide layer and a gate layer patterned into gate stacks with sidewalls for an NMOS FET device over a P-well in the substrate and a PMOS FET device over an N-well. Form P− lightly doped S/D regions in the N-well and N− lightly doped S/D regions in the P-well. Form spacers on the sidewalls of the gate stacks. Thereafter form deep N− lightly doped S/D regions in the P-well, and form deep P− lightly doped S/D regions in the N-well. Form heavily doped P++ regions self-aligned with the gate below future P+ S/D sites to be formed self-aligned with the spacers in the N-well, and form heavily doped N++ regions self-aligned with the gate below future N+ S/D sites to be formed self-aligned with the spacers in the P-well.

Abstract: A dual gate MOSFET fabrication method includes the steps of forming a first insulation layer on a semiconductor substrate, forming a first polysilicon layer on the first insulation layer, forming a first photoresist pattern on the first polysilicon layer, forming a first gate by sequentially etching the first polysilicon layer and the first insulation layer by using the first photoresist pattern as a mask, removing the first photoresist pattern, forming a second insulation layer on the semiconductor substrate and the first gate, forming a second polysilicon layer on the second insulation layer, forming a second photoresist pattern on the second polysilicon layer, and forming a second gate by etching the second polysilicon layer and the second insulation layer by using the second photoresist pattern as a mask.

Abstract: A method of forming a twin well includes the steps of: forming a field oxide layer on a semiconductor substrate to define active regions of a device, and forming a first mask which exposes a predetermined active region of the semiconductor substrate; ion-implanting a first conductivity type impurity into the exposed region of the semiconductor substrate using the first mask as an ion implantation mask, to form a first well; ion-implanting a second conductivity type impurity to penetrate the first mask, to form a buried region which is self-aligned with the first well and comes into contact with the bottom of the field oxide layer; removing the first mask, and forming a second mask which is to expose the first well of the semiconductor substrate; and ion-implanting a second conductivity impurity into the exposed region of the semiconductor substrate to levels deeper and shallower than the buried region using the second mask as an ion implantation mask, to form a second well including the buried region.

Abstract: A method of fabricating a CMOS semiconductor device is provided, which decreases the number of necessary photolithography processes for forming the LDD and pocket structures. A first pair of doped regions of a first conductivity type are formed in a first section of a semiconductor substrate and a second pair of doped regions of the first conductivity type are formed in a second section thereof. Then, a third pair of doped regions of a second conductivity type are formed in the first pair of doped regions and a fourth pair of doped regions of the second conductivity type are formed in the second pair of doped regions. Thereafter, an impurity of the second conductivity type is selectively ion-implanted into the first section while covering the second section with a mask, thereby forming a fifth pair of doped regions of the second conductivity type from the first pair of remaining doped regions.

Abstract: A method of making semiconductor devices which enables control of the impurity concentration and fine patterning by making removal of residual stress due LOCOS oxidation compatible with the formation of deep wells. A selective oxide layer is formed for separating element regions on a principal plane of a semiconductor substrate, for example, a p.sup.- -type silicon substrate 1. A mask is formed (for example photoresist 47) on the surface including the selective oxide layer and impurities (for example phosphorous) of a conductivity type opposite that of the semiconductor substrate are introduced via an opening in the mask. Then the selective oxide film is annealed by a high-temperature treatment while a deep well (for example n-type deep well 50) is formed by introducing the impurities.