Abstract: An IC comprises a tub of a first conductivity type, at least one transistor embedded in the tub, and a first pair of isolating regions defining therebetween a tub-tie region coupled to the tub. The tub-tie region comprises a cap portion of the first conductivity type and an underlying buried pedestal portion of a second conductivity type. At least a top section of the pedestal portion is surrounded by the cap portion so that a conducting path is formed between the cap portion and the tub. In a CMOS IC tub-ties of this design are provided for both NMOS and PMOS transistors. In a preferred embodiment, the cap portion of each tub-tie comprises a relatively heavily doped central section and more lightly doped peripheral sections, both of the same conductivity type.

Abstract: A semiconductor device is formed on a semiconductor substrate with an N-well and a P-well with source/drain sites in the N-well and in the P-well by the following steps. Form a gate oxide layer and a gate electrode layer patterned into a gate electrode stack with sidewalls over a substrate with N-well and P-well. Form N- LDS/LDD regions in the P-well. Form N- LDS/LDD regions in the P-well and P- lightly doped halo regions in the P-well below the source site and the drain site in the P-well. Form a counter doped halo region doped with N type dopant below the source region site in the P-well. Form spacers on the gate electrode sidewalls. Then, form lightly doped regions self-aligned with the gate electrode in the source/drain sites. Form N+ type doped source/drain regions deeper than the N- LDS/LDD regions in the P-well in the source/drain sites. Form P+ type doped source/drain regions deeper than the P- LDS/LDD regions in the N-well in the source/drain sites.

Abstract: A MOSFET integrated circuit device comprises a lightly doping a semiconductor substrate, with wells formed within the substrate doped with an opposite value dopant, forming a plurality of doped regions within the surface of the substrate and within the surface of the wells, the improvement comprising opening a trench about the periphery of the wells, and filling the trench with a relatively highly conductive material as a guard structure.

Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS.FETs.

Abstract: A twin tub integrated circuit and method for its formation are disclosed. A portion of the substrate is covered by photoresist while an n region is formed, illustratively, by ion implantation. Then the n region is covered with a protective material, illustratively a spin on glass or another photoresist. The previously-formed photoresist is removed and a p-type implant is performed to create an p region. When all the protective layers are removed, both regions have upper surfaces which are co-planar. The co-planar surfaces, a departure from previous practice, make submicron lithography easier. The regions are annealed to form twin tubs.

Abstract: A method of improving latch-up immunity and interwell isolation in a semiconductor device is provided. In one embodiment, an implant mask which has a variable permeability to implanted impurities is formed on the surface of a substrate having a first dopant region. A first portion of the implant mask overlies a first portion of the first dopant region. The structure is subjected to high energy implantation which forms a heavily doped region. A first portion of the heavily doped region is located along the lower boundary of the first dopant region. A second portion of the heavily doped region which extends along a side boundary of the first dopant region is formed by impurity ions which pass through the first portion of the implant mask. The heavily doped region improves latch-up immunity and interwell isolation without degrading threshold voltage tolerance.

Abstract: A method of manufacturing a high-voltage metal-oxide-semiconductor device that uses trenches instead of a field oxide layer as an isolating structure, and employs a vertical layout rather than a horizontal layout so that more area is available for forming devices and drift region is lengthened as well. Therefore, this invention is capable of fabricating a CMOS transistor even at the sub-micron level, and hence is able to increase the level of circuit integration for a given a wafer. Furthermore, localized atomic oxygen implant and epitaxial growth techniques are used in this invention. Consequently, an etching stop layer can be precisely established in the silicon substrate within an active area. Due to the presence of an oxide layer underneath the epitaxial layer, the oxide layer can serve as an etching stop layer when the active area of a silicon substrate is patterned.

Abstract: The present invention provide a method for forming a triple well. The triple well includes an n-well, a first p-well surrounded with the n-well and a second p-well apart from the first p-well and adjacent to the n-well. According to the present invention, only one conductivity type of impurities are implanted in each well. Therefore, it is possible to prevent the decrease of the carrier mobility and increase of the leakage current.

Abstract: The present invention discloses a method of forming CMOS transistors with planar shallow trench isolations. Before a twin well being formed, a pad oxide film and a nitride film are sequentially deposited on a silicon substrate. When a photoresist film is patterned to define active regions, the silicon substrate is recessed by using the patterned photoresist film as a mask. A liquid-phase-deposition oxide (LPD) film is then grown on the recess structure for shallow trench isolations. Next, a high temperature annealing procedure is performed to densify the LPD oxide film. Finally, when the pad oxide and the nitride films are removed, processes for fabricating CMOS transistors can be continued on the silicon substrate.

Abstract: A method of manufacturing a CMOS. A substrate is provided, wherein the substrate has a first conductive-type well, a second conductive-type well, an isolation structure formed therein, a first gate electrode on the second conductive-type well and a second gate electrode on the first conductive-type well. The first conductive-type well and the second conductive-type well are partly isolated from each other by the isolation structure. A first offset spacer is formed on a sidewall of the first and the second gate electrodes and a second offset spacer on a sidewall of the first offset spacer, wherein a portion of the first offset spacer extends on a surface of the substrate and the second offset spacer is on the portion of the first offset spacer. A first LDD region having the first conductive type is formed in a portion of the second conductive-type well exposed by the first gate electrode, the first offset spacer and the second offset spacer.

Abstract: A method of forming a self-aligned halo-isolated well with a single mask is disclosed. First, a layer of resist is disposed over at least a portion of a substrate's surface. Then, an impurity of a first polarity type is implanted at an angle into the substrate through a gap in the layer of resist, thus forming a well having the impurity of the first polarity, which extends beneath the layer of resist. An impurity of a second polarity type is also implanted, using the same mask as previously used. The second implantation forms a well of the impurity of the second polarity disposed within the well of to impurity of the first polarity.

Abstract: The invention provides an isolation technique using fewer process steps and a double charged implantation step (141) for defining a well region (139) of a CMOS integrated circuit device. The invention provides steps of providing a semiconductor substrate comprising an multiple layer of films (105, 107, 109). These films include an oxide layer (105) overlying the substrate, a polysilicon layer (107) overlying the oxide layer, and a nitride layer (109) overlying the polysilicon layer. The invention also uses a step of removing a first portion of the nitride layer and a first portion of the polysilicon layer defined underlying the first portion of the nitride layer and removing a second portion of the nitride layer and a second portion of the polysilicon layer defined underlying the second portion of the nitride layer. This sequence of steps provides a partially completed semiconductor structure that defines isolation regions before forming well regions for active devices.

Abstract: A method to form, in a NMOS area, a shallow trench isolation (STI) having B doped sidewalls regions 44 to reduce the NMOS reverse narrow width effect in narrow active areas 12N (e.g., narrow channel regions <0.1 .mu.m wide). A substrate is provided having a NMOS area 13 and a PMOS area 15. A pad oxide layer 20 and a barrier layer 22 are formed on the substrate. Trenches 24 are etched in the substrate 10 in the NMOS and PMOS areas. The etching forms narrow active areas 12N and wide active areas 12W. The narrow active areas 12N have a width between 0.4 and 1.0 .mu.m. A liner layer 30 is grown on the sidewalls and bottom of the trench on the substrate. A first photoresist layer is formed covering the PMOS areas and having first opening over the NMOS areas. In a critical step, a large angle Boron implantation is performed into the sidewalls and the bottom of the trenches forming Boron doped regions 44 in the substrate. The first photoresist layer is removed.

Abstract: To form a device isolating deep trench adjacent to a well, the deep trench is formed by using, as a mask, a photoresist mask used for forming the well and a silicon oxide film or a polysilicon film formed on a semiconductor substrate and patterned by an etching using another photoresist mask which was used for forming an adjacent well, or two patterned insulating layers formed on the semiconductor substrate. Thus, the deep trench for the device isolation can be formed without adding a photoresist step for forming a trench formation pattern. In addition, since a lift-off process is not used for forming the deep trench, an isolation trench having a narrow width can be formed, and also, there does not occur the re-deposition of the peeled-off plasma CVD insulating film onto the semiconductor substrate, with the result that the stability in manufacturing the semiconductor device is remarkably elevated.

Abstract: The present invention relates to the formation of trench isolation structures that isolate active areas and a preferred doping in the fabrication of a CMOS device with a minimized number of masks. Ions of a P-type dopant are implanted into a semiconductor substrate having therein a P-well and an N-well. Each of the N-well and P-well has therein a trench. The ions of the P-type dopant are implanted beneath each of the trenches in the P-well and the N-well to create a first P-type dopant concentration profile in the semiconductor substrate, wherein the P-well and the N-well are substantially unimplanted by the ions of the P-type dopant in active areas adjacent to the respective trenches therein. A second implanting ions of a P-type dopant is made into the semiconductor substrate. The second implanting is beneath each of the trenches in the P-well and the N-well to form a second P-type dopant concentration profile.

Abstract: The invention is an improved process for forming isolations of uniform thickness in narrow and wide trenches. The process begins by forming a pad layer on a semiconductor substrate. A first barrier layer is formed on the pad layer. The first barrier layer and pad layer are patterned forming openings, thereby exposing the substrate surface. The substrate is then etched through the openings to form shallow trenches in the substrate. The trenches generally falling into two ranges of width: narrow trenches having widths in the range between 0.3 .mu.m and 1.0 .mu.m; and wide trenches having widths greater than 1.0 .mu.m. A thin oxide film is grown on the sidewalls and bottoms of the trenches. A gap-fill dielectric layer is formed on the thin oxide film. A polysilicon layer is grown on the gap-fill dielectric layer. The polysilicon layer acts as a stop during CMP, providing additional protection of the gap-fill dielectric layer in the wide trenches. A planarizing material layer is formed on the polysilicon layer.

Abstract: A method to fabricate simultaneously a MOS transistor and an ESD protective transistor in a silicon substrate is disclosed. The ESD protective devices are fabricated by using double diffused drain (DDD) ion implantation technology. In the functional region, MOSFETs structure are ion implanted by utilizing a large angle pocket antipunchthrough, succeeded using a lightly doped drain implantation technology with a liquid phase deposition (LPD) oxide layer in the ESD protective region as a mask. Next, a first thermal process is applied to form self-aligned silicide contacts. A low energy, high dose ion implantation implanted into silicide is then carried out, which is used as a diffusion source for forming an ultra-shallow junction. After that, a second rapid thermal process (RTP) is employed, an ultra-shallow junction, and low-resistivity stable phase of self-aligned silicide contacts in the functional region and a double diffusion junction in the ESD protective region are formed simultaneously.

Abstract: A method of manufacturing a semiconductor device is provided. A first interlayer insulating layer is formed on a silicon substrate, and a lower metal layer is formed on the first interlayer insulating layer. A first insulating layer is formed on the first interlayer insulating layer including the lower metal layer, moisture contained in the first insulating layer is removed by N.sub.2 or N.sub.2 O plasma. Thereafter, a SOG layer and a second insulating layer are sequentially formed on the first insulating layer.

Abstract: A method for fabricating a high bias metal oxide semiconductor device includes using a trench structure instead of the conventional field oxide layer, constructing a structure with a vertical voltage gradient and performing punch implantation and threshold voltage implantation under a doped N.sup.- region and a doped P.sup.- region to increase the channel length.

Abstract: A novel MOS transistor structure for improving device scaling by improving short channel control includes a buried back gate beneath a channel region of the MOS transistor. A separate contact to a well that is electrically communicated to the buried back gate improves short channel controls without performance degradations. In a preferred embodiment, the back gate is grounded when turning the n-channel MOS transistor off. In alternate embodiments, the buried layer produces retrograde p wells. In some applications, multiple buried layers may be used, with one or more being planar. CMOS devices may have independent, multiple buried back gates.

Abstract: CMOS transistors are formed by a damascene process resulting in field oxide regions exhibiting essentially no bird's beak portions. A trench isolation is also formed in a source/drain region each transistor between adjacent junctions.

Abstract: A method for forming a shallow junction of a semiconductor device, characterized by a rapid thermal process executed to considerably decrease the density of the point defects which may be caused by ion implantation. With it, a junction which is much shallower, with lower sheet resistance and less junction leakage current can be obtained even under conventional ion implantation and tube treatment conditions. This contributes to an improvement in the production yield of a semiconductor device. By virtue of the elimination of the point defects, the limits in selecting the tube thermal treatment temperature and time for planarizing the subsequent interlayer insulating film can be relieved, so that process allowance can be secured, thereby improving the reliability of the semiconductor device and allowing the high integration of the semiconductor device.

Abstract: Methods of manufacturing trench-bounded buried-channel p-type metal oxide semiconductor field effect transistors (p-MOSFETs), as used in dynamic random access memory (DRAM) technologies, for significantly reducing the anomalous buried-channel p-MOSFET sensitivity to device width. In one embodiment, the method comprises the initiation of a low temperature annealing step using an inert gas after the deep phosphorous n-well implant step, and prior to the boron buried-channel implant and 850.degree. C. gate oxidation steps. Alternatively, the annealing step may be performed after the boron buried-channel implant and prior to the 850.degree. C. gate oxidation step. In another embodiment, a rapid thermal oxidation (RTO) step is substituted for the 850.degree. C. gate oxidation step, following the deep phosphorous n-well and boron buried-channel implant steps. Alternatively, an 850.degree. C. gate oxidation step may follow the RTO gate oxidation step.

Abstract: A new method for forming shallow trench isolation is disclosed herein. A pad oxide layer and a silicon nitride layer are formed on a wafer, respectively. A plurality of trenches are created in the wafer. Then, a SAC layer is formed on an N-well. A BSG layer is formed on a P-well and the N-well. A thermal process is used to form a channel stop in the P-well. Then, the BSG layer and the SAC layer are removed. Subsequently, a LPD oxide layer is deposited in the trenches. Then, a CMP process is used to polish the LPD oxide layer for planarization. The pad oxide layer and the silicon nitride layer are removed. Next, a gate oxide layer is formed on the wafer.

Abstract: A method of forming a multiple transistor channel doping in a semiconductor substrate utilizes a unique photoresist sequence. A pattern of a first resist in first and second locations on first and second different areas of the semiconductor substrate is formed, respectively. A pattern of a second resist is then formed on the second area, wherein the second resist covers the first resist pattern in the second location. The first resist is selected for being immune from the second resist. Ions are then implanted in the first area to form a first conductivity type well having a first multiple transistor channel doping profile. The second resist pattern is then removed and a pattern of a third resist is formed on the first area, wherein the third resist covers the first resist pattern in the first location. In addition, the first resist is selected for being immune from the third resist.

Abstract: A CMOS integrated circuit with field isolation including an NFET(s) having an isolated P-well, wherein the isolated P-well is adjusted so that it does not extend below the field isolation (e.g., STI) and the width and doping of the P-well and an underlying buried N-well is adjusted so that the depletion regions of the source/drain (S-D) diode and also the well-diode just meet (merge) without overlap in the P-well. The semiconductor device obtains bipolar effect and reduced junction capacitance in a bulk single-crystal technology. A method for fabricating the semiconductor device is also provided.

Abstract: A structure includes an element isolating region for isolating a transistor formation region having an MOS transistor from other element formation region. Two or more trenches is formed at a semiconductor substrate in the element isolation region. An isolating and insulating layer filling the trench and protruded above the main surface of the semiconductor substrate has a side surface continuous with a side surface of the trench. Insulating layers and layered on the surface of the semiconductor substrate is located between the trenches. The insulating layer has the upper surface at the substantially same level as the upper surface of an isolating and insulating layer. This structure suppresses increase in a parasitic capacitance of a gate electrode, and allows a fast operation without difficulty.

Abstract: A method for fabricating a CMOSFET includes the steps of forming a first well of a first conduction type and a second well of a second conduction type on a substrate of the first conduction type; forming gate electrodes having sides on the first well and the second well; forming semiconductor sidewall spacers of the first conduction type at the sides of the gate electrodes; forming a semiconductor layer of the second conduction type over the first well; implanting impurity ions of the first conduction type into the second well; and annealing the semiconductor substrate to form lightly doped shallow impurity regions of the first conduction type in the first and second wells under the semiconductor sidewall spacers, and heavily doped deep impurity regions of the second conduction type in the first well, and simultaneously activating the impurity ions in the second well to formed heavily doped deep impurity regions of the first conduction type in the second well.

Abstract: A CMOS device having reduced parasitic junction capacitance and a process for fabrication of the device. The device includes an a portion (20') of an undoped epitaxial layer (20) vertically separating source and drain regions (52 and 53, 54 and 55) from buried layers (16, 18) formed in a semiconductor substrate (12). The undoped epitaxial layer (20) reduces the junction capacitance of the source and drain regions by providing an intrinsic silicon region physically separating regions of high dopant concentration from the source and drain regions. Additionally, MOS transistors fabricated in accordance with the invention have fully self-aligned channel regions extending from the upper surface (22) of the undoped epitaxial layer (20) to the buried layers (16, 18) residing in the semiconductor substrate (12).

Abstract: The present invention provides a CMOS integrated circuit in which core transistors are provided with punch-through pockets, while the input/output transistors are not provided with punch-through pockets. Punch-through protection for the input/output transistors by virtue of their larger dimensions. The pockets, like lightly doped drains, are formed after the gates are formed but before the formation of gate sidewalls. However, the input/output are masked during the punch-through implants, but are unmasked for at least one of the lightly doped drain implants. The absence of pockets on the input/output transistors enhances their ESD resistance, and thus the ESD resistance of the incorporating integrated circuit.