Abstract: In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has a second compressive stress smaller than the first compressive stress. The dual stress liner may be formed by forming a stress liner on a semiconductor substrate on which the PMOSFET and the NMOSFET are formed and selectively exposing a portion of the stress liner on the NMOSFET.

Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

Abstract: The present invention is generally directed to a method of forming a p-well in an integrated circuit device. In one illustrative embodiment, the method comprises forming a first layer of epitaxial material above an active layer of a substrate, forming a first doped region in the first layer of epitaxial material, forming a second layer of epitaxial material above the first layer of epitaxial material, forming a second doped region in the second layer of epitaxial material, and performing at least one heat treating process.

Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.

Abstract: A method is described to fabricate a MOSFET device with increased threshold voltage stability. After the pad oxide and pad nitride are deposited on the silicon substrate and shallow trenches are patterned and the pad nitride removed. As+ or P+ species are then implanted using low energy ions of approximately 5 keV into the pad oxide. Conventional As+ or P+ implant follows the shallow implant to form the n-wells. With this procedure of forming a sacrificial shallow implantation oxide layer, surface dopant concentration variation at pad oxide:silicon substrate interface is minimized; and threshold voltage stability variation of the device is significantly decreased.

Abstract: Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the active areas having a width of less than one micron, and with some of the active areas having different widths. A gate line is formed over the active areas to provide transistors having different threshold voltages. In one embodiment, the transistors are provided with different threshold voltages without using a separate channel implant for the transistors.

Abstract: A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.

Abstract: Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A gate dielectric layer is formed over the device. A gate electrode layer is formed that serves as the gate electrode and a bottom capacitor plate. The gate electrode and the gate dielectric layer are patterned to form gate structures. Source and drain regions are formed within the well regions and the drain extension regions. A silicide blocking layer is formed that also serves as a capacitor dielectric. Field plates and a top capacitor plate are formed on the blocking layer.

Abstract: A silicon-on-insulator (SOI) device structure 100 formed using a self-aligned body tie (SABT) process. The SABT process connects the silicon body of a partially depleted (PD) structure to a bias terminal. In addition, the SABT process creates a self-aligned area of silicon around the edge of the active areas, as defined by the standard transistor active area mask, providing an area efficient device layout. By reducing the overall gate area, the speed and yield of the device may be increased. In addition, the process flow minimizes the sensitivity of critical device parameters due to misalignment and critical dimension control. The SABT process also suppresses the parasitic gate capacitance created with standard body tie techniques.

Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.

Abstract: The present invention provides a non-volatile memory device and fabricating method thereof, by which a cell size can be lowered despite high degree of cell integration and by which the device fabrication is facilitated. The present invention includes at least two trench isolation layers arranged in a device isolation area of a semiconductor substrate, each having a first depth, a first conductive type well arranged between the at least two trench isolation layers to have a second depth smaller than the first depth, a second conductive type source region and a second conductive type drain region arranged in a prescribed upper part of the first conductive type well to be separated from each other by a channel region in-between, an ONO layer on the channel region of the semiconductor substrate, the ONO layer comprising a lower oxide layer, a nitride layer, and an upper oxide layer, and a wordline conductor layer on the ONO layer.

Abstract: A method of fabricating an LDMOS transistor and a conventional CMOS transistor together on a substrate. A P-body is implanted into a source region of the LDMOS transistor. A gate oxide for the conventional CMOS transistor is formed after implanting the P-body into the source region of the LDMOS transistor. A fixed thermal cycle associated with forming the gate oxide of the conventional CMOS transistor is not substantially affected by the implanting of the P-body into the source region of the LDMOS transistor.

Abstract: A method of removing the cap from a gate of an embedded SiGe semiconductor device includes the formation of the embedded SiGe semiconductor device with the cap consisting of a cap material on top of the gate, first sidewall spacers on side surfaces of the gate, and embedded SiGe in source and drain regions. Second sidewall spacers are formed on the first sidewall spacers, these second sidewall spacers consisting of a material different from the cap material. The cap is stripped from the top of the gate with an etchant that selectively etches the cap material and not the second sidewall spacer material.

Abstract: A semiconductor element such as a DMOS-transistor is fabricated in a semiconductor substrate. Wells of opposite conductivity are formed by implanting and then thermally diffusing respective well dopants into preferably spaced-apart areas in the substrate. At least one trench and active regions are formed in the substrate. The trench may be a shallow drift zone trench of a DMOS-transistor, and/or a deep isolation trench. The thermal diffusion of the well dopants includes at least one first diffusion step during a first high temperature drive before forming the trench, and at least one second diffusion step during a second high temperature drive after forming the trench. Dividing the thermal diffusion steps before and after the trench formation achieves an advantageous balance between reducing or avoiding lateral overlapping diffusion of neighboring wells and reducing or avoiding thermally induced defects along the trench boundaries.

Abstract: In a multiple input ESD protection structure, the inputs are isolated from the substrate by highly doped regions of opposite polarity to the input regions. Dual polarity is achieved by providing a symmetrical structure with n+ and p+ regions forming each dual polarity input. The inputs are formed in a p-well which, in turn, is formed in a n-well. Each dual polarity input is isolated by a PBL under the p-well, and a NISO underneath the n-well. An isolation ring separates and surrounds the inputs. The isolation ring comprises a p+ ring or a p+ region, n+ region, and p+ region formed into adjacent rings.

Abstract: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

Abstract: A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.

Abstract: In a method for fabricating a semiconductor device different types of a metal-semiconductor compound are formed on or in at least two different conductive semiconductor regions so that for each semiconductor region the metal-semiconductor compound region may be formed to obtain an optimum overall performance of the semiconductor device. On one of the two semiconductor regions, the metal-semiconductor compound is formed of at least two different metal layers, whereas the metal-semiconductor compound in or on the other semiconductor region is formed from a single metal layer.

Abstract: A CMOS integrated circuit (15A-B-C) includes both relatively low-power (124, 126) and high-power (132, 134) CMOS transistors on the same chip. A 20V, relatively high-power PMOS device (134) includes a heavily doped N-well drain region (70). A 20V, relatively high-power NMOS device (132) includes heavily doped P-type buried layers (76, 78) underneath the source (94) and drain regions (96) and spanning the gap between the P-well gate (90F) and adjacent P-well isolation regions (46, 50).

Abstract: The present invention provides a SiGe-based bulk integration scheme for generating FinFET devices on a bulk Si substrate in which a simple etch, mask, ion implant set of sequences have been added to accomplish good junction isolation while maintaining the low capacitance benefits of FinFETs. The method of the present invention includes providing a structure including a bottom Si layer and a patterned stack comprising a SiGe layer and a top Si layer on the bottom Si layer; forming a well region and isolation regions via implantation within the bottom Si layer; forming an undercut region beneath the top Si layer by etching back the SiGe layer; and filling the undercut with a dielectric to provide device isolation, wherein the dielectric has an outer vertical edge that is aligned to an outer vertical edge of the top Si layer.

Abstract: A dual-metal CMOS arrangement and method of making the same provides a substrate and a plurality of NMOS devices and PMOS devices formed on the substrate. Each of the plurality of NMOS devices and PMOS devices have gate electrodes. Each NMOS gate electrode includes a first silicide region on the substrate and a first metal region on the first silicide region. The first silicide region of the NMOS gate electrode consists of a first silicide having a work function that is close to the conduction band of silicon. Each of the PMOS gate electrodes includes a second silicide region on the substrate and a second metal region on the second silicide region. The second silicide region of the PMOS gate electrode consists of a second silicide having a work function that is close to the valence band of silicon.

Abstract: A method of creating two or more semiconductor elements of different characteristics in one and the same semiconductor substrate. Two antimony-diffused regions are formed in a p-type semiconductor region (of a semiconductor substrate for providing embedded layers for two field-effect transistors of unlike characteristics. Then the substrate is overlaid with a mask bearing two different patterns of windows. Then phosphor is introduced into the substrate through the mask windows to create phosphor-diffused regions in overlying relationship to the antimony-diffused regions. The two window patterns of the mask are such that the two phosphor-diffused regions differ in mean phosphor concentration. The embedded layers for the two FETs are obtained as an n-type epitaxial layer is subsequently formed on the p-type semiconductor region in which have been created the antimony-diffused regions and phosphor-diffused regions.

Abstract: Low RC structures for routing body-bias voltage are provided and described. These low RC structures are comprised of a deep well structure coupled to a metal structure.

Abstract: Disclosed is a method of manufacturing semiconductor devices. Before the threshold voltage ion is implanted, an inert ion having no electrical properties is implanted into the bottom of a channel region to form an anti-diffusion layer. Therefore, it is possible to prevent diffusion of an ion for adjusting the threshold voltage into the bottom of the channel region, occurring in a subsequent annealing process, and prohibit behavior of the ion at the channel region when a high voltage is applied to a P well. Further, the anti-diffusion layer serves as a layer to gather defects, etc. existing in the semiconductor substrate. Also, as the amount of channel ion could be adjusted by controlling the implantation depth of the inert ion, it is possible to control the threshold voltage of the device depending on higher integration.

Abstract: A method to provide a triple well in an epitaxially based CMOS or B:CMOS process comprises the step of implanting the triple well prior to the epitaxial deposition.

Abstract: A method is provided for manufacturing a semiconductor device that can reduce the number of steps in manufacturing a triple-well that includes multiple ion implantation steps and heat treatment steps.

Abstract: For characterizing bulk leakage current of a junction, a center junction surrounded by an isolation structure is formed with a first depth. In addition, at least one periphery junction having a second depth greater than the first depth is formed in a portion of the center junction adjacent the isolation structure. A junction silicide is formed with the center and periphery junctions. The magnitude of a reverse-bias voltage across the junction silicide and the P-well is incremented for determining a critical magnitude of the reverse-bias when current through the junction silicide and the P-well reaches a threshold current density.

Abstract: A method is provided for forming NMOS and PMOS transistors with ultra shallow source/drain regions having high dopant concentrations. First sidewall spacers and nitride spacers are sequentially formed on the sides of a gate electrode followed by forming a self-aligned oxide etch stop layer. The nitride spacer is removed and an amorphous silicon layer is deposited. The etch stop layer enables a controlled etch of the amorphous silicon layer to form silicon sidewalls on the first sidewall spacers. Implant steps are followed by an RTA to activate shallow and deep S/D regions. The etch stop layer maintains a high dopant concentration in deep S/D regions. After the etch stop is removed and a titanium layer is deposited on the substrate, an RTA forms a titanium silicide layer on the gate electrode and an extended silicide layer over the silicon sidewalls and substrate which results in a low resistivity.

Abstract: A method is provided for manufacturing a semiconductor device having a high breakdown voltage transistor and a low breakdown voltage transistor with different driving voltages in a common substrate.

Abstract: In a method for creating a stepped structure on a substrate, which at least includes a first portion with a first thickness and a second portion with a second thickness, at first a layer sequence of a first oxide layer, a first nitride layer, and a second oxide layer is applied onto the substrate. Then a portion of the second oxide layer and a portion of the first nitride layer are removed to expose a portion of the first oxide layer. Then a part of the first nitride layer is removed to establish the first region of the stepped structure. Then the thickness of the first oxide layer is changed at least in the established first region to establish the first thickness of this region. Subsequently, a further part of the first nitride layer is removed to establish a second region of the stepped structure.

Abstract: A method is provided for manufacturing a semiconductor device having a high breakdown voltage transistor and a low breakdown voltage transistor with different driving voltages in a common substrate. The method includes: (a) introducing an impurity of a second conductivity type in a specified region of a semiconductor substrate of a first conductivity type to form a first impurity layer and a second impurity layer; (b) further introducing an impurity of the second conductivity type in a region of the second impurity layer to form a third impurity layer; and (c) conducting a heat treatment to diffuse impurities of the first impurity layer and the third impurity layer to form a first well of the second conductivity type and a second well of the second conductivity type having an impurity concentration higher than the first well.

Abstract: A method of manufacturing a semiconductor component includes forming a first electrically insulating layer (120) and a second electrically insulating layer (130) over a semiconductor substrate (110). The method further includes etching a first trench (140) and a second trench (150) through the first and second electrically insulating layers and into the semiconductor substrate, and etching a third trench (610) through a bottom surface of the second trench and into the semiconductor substrate. The third trench has a first portion (920) and a second portion (930) interior to the first portion. The method still further includes forming a third electrically insulating layer (910) filling the first trench and the first portion of the third trench without filling the second portion of the third trench, and also includes forming a plug layer (1010) in the second portion of the third trench.

Abstract: A method for fabricating a high voltage dual gate device is disclosed which limits damage to a device isolation layer by forming a high voltage oxide film after formation of a buffer nitride film.

Abstract: High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.

Abstract: An LDMOS transistor and a bipolar transistor with LDMOS structures are disclosed for suitable use in high withstand voltage device applications, among others. The LDMOS transistor includes a drain well region 21 formed in P-type substrate 1, and also formed therein spatially separated one another are a channel well region 23 and a medium concentration drain region 24 having an impurity concentration larger than that of drain well region 21, which are simultaneously formed having a large diffusion depth through thermal processing. A source 11s is formed in channel well region 23, while a drain 11d is formed in drain region 24 having an impurity concentration larger than that of drain region 24. In addition, a gate electrode 11g is formed over the well region, overlying the partially overlapped portions with well region 23 and drain region 24 and being separated from drain 11d.

Abstract: A transistor is formed in a semiconductor substrate. A deep n-well region is used in conjunction with a shallow n-well region. A lightly doped drain extension region is disposed between a drain region and a gate conductor. The use of the regions and against the backdrop of region provides for a very high breakdown voltage as compared to a relatively low channel resistance for the device.

Abstract: A semiconductor device having a plurality of silicidation steps is provided. In the preferred embodiment in which the semiconductor device is a MOSFET, the source/drain regions are silicided. A dielectric layer is formed and the etch stop layer is removed from the gate electrode of the MOSFET. A second silicidation process is performed to silicide the gate electrode. The process may be performed individually for each transistor, allowing the electrical characteristics of each transistor to be determined individually.

Abstract: One aspect of the present invention provides a process for forming IC devices with ESD protection transistors. According to one aspect of the invention, an ESD protection transistor is provided with a light doping and then, after forming spacers, a heavy doping. The heavy doping with spacers in place can lower the sheet resistance, enhance the bipolar effect for the transistor, reduce the transistor's capacitance, and reduce the junction breakdown voltage, all without causing short channel effects. The invention thereby provides ESD protection transistors that are compact, highly sensitive, and fast-switching. The spacers can be formed at the same time as spacers for other transistors, such as other transistors in a peripheral region of the device.

Abstract: A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically active portion of a transistor gate is disclosed. The well region is laterally displaced from a charge collection region of a second conductivity type of a pinned photodiode.

Abstract: On the surface of a semiconductor material of a first conductivity type 101a, a lateral MOS transistor 100 is described surrounded by a well 171 of the opposite conductivity type and, nested within the well, an electrical isolation region 102. The semiconductor region 101a embedding this transistor has a resistivity higher than the remainder of the semiconductor material 101 and further contains a buried layer 160 of the opposite conductivity type. This layer 160 extends laterally to the wells 171, thereby electrically isolating the near-surface portion of the semiconductor region from the remainder of the semiconductor material, and enabling the MOS transistor to operate as an electrically isolated high-voltage I/O transistor for circuit noise reduction, while having low drain junction capacitance. In the first embodiment of the invention (FIG.

Abstract: A Deep Trench (DT) capacitor in a semiconductor substrate has an isolation collar formed on trench sidewalls above the DT bottom. An outer plate is formed below the collar. Capacitor dielectric is formed on DT walls below the collar. An node electrode is formed in the DT, recessed below the DT top. The collar is recessed in the DT. A combined poly/counter-recrystallizing species cap is formed over the node electrode with a peripheral strap. The cap may be formed after formed a peripheral divot of a recessed collar, followed by forming an intrinsic poly strap in the divot and doping with a counter-recrystallization species, e.g. Ge, into the node electrode and the strap. Alternatively, the node electrode is recessed followed by codeposition of poly and Ge or another counter-recrystallization species to form the cap and strap.

Abstract: A flash memory device includes a substrate having first and second wells. The first well is defined within the second well. A plurality of trenches defines the substrate into a plurality of sub-columnar active regions. The trenches is formed within the first well and extends into the second well. A plurality of flash memory cells are formed on each of the sub-columnar active regions.

Abstract: A heterogeneous device comprises a substrate and a plurality of heterogeneous circuit devices defined in the substrate. In embodiments, a plurality of heterogeneous circuit devices are integrated by successively masking and ion implanting the substrate. The heterogeneous device may further comprise at least one microelectromechanical system-based element and/or at least one photodiode. In embodiments, the heterogeneous circuit devices comprise at least one CMOS transistor and at least one DMOS transistor. In embodiments, the substrate comprises a layer of silicon or a layer of p-type silicon. In other embodiments, the substrate comprises a silicon-on-insulator wafer comprising a single-crystal-silicon layer or a single-crystal-P-silicon layer, a substrate and an insulator layer therebetween.

Abstract: A semiconductor device includes a relatively lower threshold level MOSFET and relatively higher threshold level MOSFETs of n- and p-types. The higher threshold level MOSFETs have gate oxide films which is thicker than that of the lower threshold level MOSFET and, in addition, the gate oxide film of the higher threshold level MOSFET of n-type is thicker than that of the higher threshold level MOSFET of p-type. To fabricate the semiconductor device, implantation treatments of fluorine ions are carried out before the gate oxide treatment. Specifically, as for the higher threshold level MOSFETs of n- and p-types, implantation treatments of fluorine ions are independently carried out with unique implantation conditions.

Abstract: Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.

Abstract: A semiconductor device with p-channel and n-channel field effect devices formed on a common substrate, where the drain and source regions of the n-channel field effect device are formed within a silicon epitaxial layer formed on a silicon layer germanium relax which is formed on a silicon germanium buffer layer with a graduated germanium concentration. Additionally, drain and source regions of the p-channel field effect device are formed within a silicon-germanium compound layer formed on the substrate and the silicon epitaxial cap layer formed on the silicon-germanium compound layer.

Abstract: A plurality of p-wells and n-wells are formed in a front side of a bulk material, and a plurality of n layers and p layers are alternately formed within the bulk material between a back side of the bulk material and the plurality of n-wells and p-wells. The plurality of n layers are electrically isolated from one another and respectively route different potentials to selected ones of the plurality of n-wells, and likewise, the plurality of p layers are electrically isolated from one another and respectively route different potentials to selected ones of the plurality of p-wells.

Abstract: A field oxide film for element isolation is formed on an SOI substrate having a silicon layer formed on an insulating layer, an active nitride film is wet-etched to reduce its film thickness to a value small enough to allow the edge of the silicon layer to become exposed and ions of a channel stopping impurity are implanted only into the edge of the silicon layer through self-alignment either vertically or at an angle by using the active nitride film as a mask. Through this manufacturing method, a field effect transistor which achieves a small gate length, is free from the adverse effect of a parasitic transistor and thus does not readily manifest a hump, and allows a reduction in the distance between an nMOS and a pMOS provided next to each other is realized.

Abstract: A method for forming a semiconductor device, includes forming a first locally doped semiconductor region of a first conductivity type and a second locally doped semiconductor region of a second conductivity type over an undoped, lower semiconductor region. A first etch is implemented to simultaneously create a desired pattern in the first and second locally doped semiconductor regions in a manner that also provides a first passivation of exposed sidewalls thereof, wherein the first etch removes material from the first and second locally doped regions at a substantially constant rate with respect to one another, and in a substantially anisotropic manner. A second etch is implemented to complete the desired pattern in the undoped, lower semiconductor region in a manner that protects the first and second locally doped regions from additional material removal therefrom.