Abstract: For use with sub-micron CMOS technologies, a gate etch process improves control of the etch profile. Gate stacks utilize N-type or P-type doped amorphous or poly silicon to enhance device performance. However, the different etching characteristics of the N-type versus the P-type amorphous or poly silicon material can result in a localized breakthrough of the underlying thin gate oxide adjacent to the edge of the gate stack, especially in the N doped active regions. According to one example embodiment, this localized breakthrough (“microtrenching”) is avoided by building the gate stacks with undoped amorphous or poly silicon to the desired configuration, masking the gate stacks with a dielectric layer, planarizing the dielectric layer and then implanting the N-type or P-type species into the selected gate stack.

Abstract: A process for forming a vertical double-diffused metal oxide semiconductor (VDMOS) structure comprising a semiconductor substrate, an epitaxial layer on the substrate, and a dielectric gate layer on the epitaxial layer includes implanting a first concentration dopant of a first conductivity type through an aperture defined by edges of a patterned gate conductor layer on the dielectric gate layer so that the first concentration dopant diffuses to form a body region of the VDMOS structure. A mask is formed on the patterned gate conductor layer and on a first portion of the body region for defining apertures exposing second portions of the body region.

Abstract: A pad oxide layer is formed on a substrate, wherein the thickness of the pad oxide layer is about greater than 250 Å. The alignment photo-resist layer is selectively patterned by a conventional lithography method to define the N-well region. The pad oxide layer is partially etched by using etch method with the alignment photo-resist pattern as a mask until the thickness of the pad oxide layer is about 100 Å to form an alignment mark. The N-type ion-implant is performed by the alignment photo-resist pattern as a mask to form an N-doped region in the substrate. Then, the alignment photo-resist pattern is removed. The P-well photo-resist is defined and formed on the pad oxide layer, then performing a P-type ion-implant through the pad oxide layer into the substrate by means of the P-well photo-resist as a mask to form a P-doped region. Then remove the P-well photo-resist and proceed with the drive-in process to form the N-well region and P-well region.

Abstract: A photoresist pattern through which a first well forming region and a second well forming region are exposed is formed over a semiconductor substrate, used as the mask to dope the semiconductor substrate with an impurity thereby to form buried n-wells, and further used as the mask to dope the same with an impurity thereby to form shallow p-wells in a self-alignment manner over the buried n-wells. Subsequently, the photoresist pattern is removed. After this, a photoresist pattern through which the outer peripheral region of the first well forming region and a third well forming region are exposed is formed over the major surface of the semiconductor substrate, and used as the mask to dope the semiconductor substrate with an impurity thereby to form shallow p-wells.

Abstract: There is provided a method of fabricating a semiconductor device, including the steps of (a) forming both a p-well region and an n-well region at a surface of a semiconductor substrate, and (b) forming an n-type epitaxial layer on both the p- and n-well regions so that the n-type epitaxial layer contains impurities therein at a concentration lower than a concentration of impurities contained in the n-well region. For instance, the n-type epitaxial layer is formed by chemical vapor deposition in which a process gas including phosphorus or arsenic compounds therein is used. In accordance with the method, it is possible to optimize threshold voltages of both n-type and p-type transistors in a low-impurity channel transistor at a smaller number of steps. This ensures reduction in fabrication cost and enhancement in a fabrication yield.

Abstract: A high-voltage device. A substrate has a first conductive type. A first well region with the first conductive type is located in the substrate. A second well region with the second conductive type is located in the substrate but is isolated from the first well region. Several field oxide layers are located on a surface of the second well region. A shallow trench isolation is located between the field oxide layers in the second well region. A first doped region with the second conductive type is located beneath the field oxide layers. A second doped region with the first conductive type is located beneath the shallow trench isolation in the second well region. A third well region with the first conductive type is located in the first well region and expands from a surface of the first well region into the first well region. A gate structure is positioned on the substrate between the first and the second well regions and covers a portion of the first, the third well regions and the field oxide layers.

Abstract: A solid imaging device including: a semiconductor substrate of a first conductivity type; a layer of a second conductivity type formed on a surf ace of the semiconductor substrate, the layer at least including a photosensitive portion of the second conductivity type; and a MOS transistor of the second conductivity type coupled to the photosensitive portion, wherein the solid imaging device further includes a layer of the first conductivity type in at least a channel region of the MOS transistor of the second conductivity type, the layer of the first conductivity type having an impurity concentration which is higher than an impurity concentration of the semiconductor substrate, and wherein at least a portion of a boundary of the layer of the second conductivity type is in direct contact with the semiconductor substrate.

Abstract: A method for fabricating a semiconductor device comprises implantating and diffusing a first well in a semiconductor substrate. A second well is implantated and diffused in the first well. A third well is implantated in the second well and a MOS transistor is formed in the third well.

Abstract: An electro-static discharge (ESD) circuit of a semiconductor device, a structure thereof and a method for fabricating the ESD structure are provided. In the ESD circuit, a gate electrode and a drain region of a MOS transistor are connected to an electrical signal pad, and a Zener diode is connected to a source region of the MOS transistor. A threshold voltage of the MOS transistor is higher than an operating voltage of an internal circuit and lower than a drain junction breakdown voltage of a MOS transistor constituting the internal circuit. Also, instead of using a Zener diode for each signal pad, a common diode having a maximized junction area can be shared by a plurality of signal pads.

Abstract: A method for incorporating an ion implanted channel stop layer under field isolation for a twin-well CMOS process is described in which the layer is placed directly under the completed field isolation by a blanket boron ion implant over the whole wafer. The channel stop implant follows planarization of the field oxide and is thereby essentially at the same depth in both field and active regions. Subsequently implanted p- and n-wells are formed deeper than the channel stop layer, the n-well implant being of a sufficiently higher dose to over compensate the channel stop layer, thereby removing it's effect from the n-well. A portion of the channel stop implant under the field oxide adjacent the p-well provides effective anti-punchthrough protection with only a small increase in junction capacitance. The method is shown for, and is particularly effective in, processes utilizing shallow trench isolation.

Abstract: There is disclosed a method for manufacturing a semiconductor integrated circuit of triple well structure, comprising the steps of forming an N-well, a P-well and a device isolation region in an N-type silicon substrate, thereafter forming a silicon oxide film on the whole surface of the silicon substrate by a thermal oxidation, forming a resist mask covering a region in which the silicon oxide film is required, ion-implanting a P-type impurity using the resist mask as a mask and with an implantation energy enough to allow the ion-implanted impurity to reach a bottom of the N-well and the P-well, so as to form a buried impurity layer, thereafter removing the silicon oxide film not covered with the resist mask by an etching, then removing the resist mask, and conducting a thermal oxidation on the whole surface of the silicon substrate so that a relatively thick gate oxide film is formed on a region which was covered with the resist mask, and a relatively thin gate oxide film is formed on a region which was not

Abstract: To reduce p-n junction leakage at the boundary between lightly doped wells formed in lightly doped bulk materials, a high concentration region is implanted at the junction. The high concentration region contains a relatively high dopant level, and thus reduces the width of the depletion region at the junction. The reduced width of the depletion region in turn reduces junction leakage.

Abstract: Isolation regions are formed with greater accuracy and consistency by forming an oxide-silicon nitride stack and then depositing an amorphous silicon antireflective layer, on the silicon nitride layer before patterning. Embodiments also include depositing the silicon nitride layer and the amorphous silicon layer in the same tool.

Abstract: A method for fabricating a CMOS image sensor is disclosed. The CMOS sensor includes the portions of sensor photo-diode array NMOS and PMOS. In the method, partial steps involving implantation for image sensor fabrication are implemented at different times with the fabrication of NMOS. The method is compatible with the present process only to add a mask for patterning sensor implantation and to modify some traditional patterns of masks. The doses of the field region within the region of sensor photo-diode array can be implemented separately and are not subject to higher dopants for NMOS in the present fabrication. Thus, the doses for the sensor photo-diode array can be adjusted to meet the requirements of isolation and low dark current for the image sensor.

Abstract: A semiconductor structure comprises first gate conductors which wrap around N-wells of buried-channel P-type metal oxide semiconductor field effect transistors and second gate conductors which do not wrap around P-wells of surface-channel N-type metal oxide semiconductor field effect transistors and a method of manufacturing the same comprises forming insulators adjacent each of the N-wells and the P-wells, protecting the N-wells with a patterned mask, forming first divots in areas of the insulators adjacent the N-wells and forming second divots in areas of the insulators P-wells, wherein the first divots have a greater depth than the second divots.

Abstract: A method is provided for fabricating a first and second MOSFET transistors in different electrically isolated active areas of a semiconductor body, each one of the transistors having a plurality of layers. A first gate oxide layer and a first poly-crystalline silicon layer are deposited over the semiconductor body over the active areas. Trenches are etched in said first gate oxide and poly-crystalline silicon layers and said semiconductor body to delineate the first and second active areas, thereby forming first delineated gate oxide layer and poly-crystalline silicon layers coextensive with the first active area. Material is deposited in said trenches to form the active area isolations, the active area isolations having a top surface above said semiconductor body. A masking layer is then formed over said first and second active areas and selective portions of it are removed to expose said second active area.

Abstract: The present invention provides a CMOS process, wherein a halo structure can be fabricated without employing an additional lithographic mask for protecting the transistors of the opposite conductivity during a halo implant. The halo implant has a projected range or depth that lies in the range of an LIP implant or a counter-doping implant in the well containing the transistors of the opposite conductivity. The LIP or counter-doping implant effectively cancels the halo impurities.

Abstract: A method for selectively heating a substrate without damaging surrounding regions of the substrate. In particular, the invention provides for a method of selectively activating doped regions of a semiconductor device without damaging surrounding doped and activated regions. Specifically, the invention provides a laser anneal which activates locally doped regions, while surrounding doped and activated regions are protected using a reflective mask.

Abstract: A method for fabricating a semiconductor device. A shallow trench isolation is formed by forming a well region, a gate oxide layer and a wiring layer prior to forming a trench in the substrate. The trench is then filled with silicon oxide layer doped with germanium, nitrogen, titanium or other refractory metal. In addition, a MOS device is also fabricated with a gate buried in the substrate with a shallow trench isolation filled with the doped silicon oxide layer formed therein.

Abstract: Provided with a semiconductor device including: a semiconductor substrate having a first conductivity type; a first well having a second conductivity type formed in a first region in a major surface of the semiconductor substrate; a second well having the first conductivity type formed in a second region in the major surface of the semiconductor substrate; a first MOS transistor having the first conductivity type and a first contact region having the second conductivity type formed in the first well; a second MOS transistor having the second conductivity type and a second contact region having the second conductivity type formed in the second well; a heavily doped region of buried layer having the second conductivity type formed at a portion corresponding to the first contact region in the first well; and a heavily doped region of buried layer having the first conductivity type formed at a portion corresponding to the second contact region in the second well.

Abstract: A method of manufacturing wells comprises the step of providing a p-type substrate and then sequentially forming a p-well and n-well with low dosage in the p-type substrate. Thereafter, energy is used to dope n-type ions into the p-well. The triple well formed in the present invention has low dosage ions, hence the DRAM formed on the triple well in subsequent process can have a faster refresh time.

Abstract: A fabrication method for a metal oxide semiconductor (MOS) transistor involves forming gate oxide layers of different thicknesses on a core region and a input/output (I/O) region. After forming wells in the substrate, two implantation regions for providing a threshold voltage (VT) adjustment and an anti-punch through layer are formed respectively in a P-well and a N-well of the core region as well as a P-well and a N-well of the I/O region. The method involves forming a pattern mask on the gate oxide layer, wherein the pattern mask has an opening, which may be a channel that corresponds to the P-well of the core region. With the pattern mask serving as an ion implantation mask, two implantation regions for providing the VT adjustment and the anti-punch through layer are formed in the P-well of the core region. After the pattern mask is removed, the steps described above are repeated in order to form implantation regions in other regions, but the sequence of the steps can be swapped around at will.

Abstract: A photoresist pattern through which a first well forming region and a second well forming region are exposed is formed over a semiconductor substrate, used as the mask to dope the semiconductor substrate with an impurity thereby to form buried n-wells, and further used as the mask to dope the same with an impurity thereby to form shallow p-wells in a self-alignment manner over the buried n-wells. Subsequently, the photoresist pattern is removed. After this, a photoresist pattern through which the outer peripheral region of the first well forming region and a third well forming region are exposed is formed over the major surface of the semiconductor substrate, and used as the mask to dope the semiconductor substrate with an impurity thereby to form shallow p-wells.

Abstract: A circuit device that includes a gate overlying an area of a semiconductor substrate, a well formed in the substrate proximate a first edge of the gate and doped with a first concentration of a first dopant, a channel region doped with a first concentration of a second dopant underlying a portion of the gate adjacent the well, a non-conducting region formed in the first portion of the well, and a contact to the second portion of the well distal from the first edge of the gate.

Abstract: Methods of manufacturing trench-bounded buried-channel p-type metal oxide semiconductor field effect transistors (p-MOSFETs), as used in dynamic random access memory (DRAM) technologies, for significantly reducing the anomalous buried-channel p-MOSFET sensitivity to device width. In one embodiment, the method comprises the initiation of a low temperature annealing step using an inert gas after the deep phosphorous n-well implant step, and prior to the boron buried-channel implant and 850° C. gate oxidation steps. Alternatively, the annealing step may be performed after the boron buried-channel implant and prior to the 850° C. gate oxidation step. In another embodiment, a rapid thermal oxidation (RTO) step is substituted for the 850° C. gate oxidation step, following the deep phosphorous n-well and boron buried-channel implant steps. Alternatively, an 850° C. gate oxidation step may follow the RTO gate oxidation step.

Abstract: A twin-well CMOS integrated circuit device includes an n-well region and a p-well region. Each of the n-well and p-well region includes spaced-apart regions which serve as drain and source regions, a channel region between the spaced-apart regions, a shallow trench isolation structure contiguous with one of the spaced-apart regions, and a doped diffused region extending from the surface of the well region, around and underneath the trench isolation structure, to a region beneath the contiguous spaced-apart region.

Abstract: A first dielectric layer (22) is formed over a semiconductor device substrate. A resist layer (32) is then patterned to expose portions of the first dielectric layer (22). Portions of the first dielectric layer (22) are removed to expose portions of the semiconductor device substrate (42). The resist layer (32) is then removed. The semiconductor device substrate is cleaned without using a fluorine-containing solution and a second dielectric layer (62) is formed overlying the semiconductor device substrate.

Abstract: The present invention provides a CMOS process, wherein a halo structure can be fabricated without employing an additional lithographic mask for protecting the transistors of the opposite conductivity during a halo implant. The halo implant has a projected range or depth that lies in the range of an LIP implant or a counter-doping implant in the well containing the transistors of the opposite conductivity. The LIP or counter-doping implant effectively cancels the halo impurities.

Abstract: Methods are described to prevent the inherent latchup problem of CMOS transistors in the sub-quarter micron range. Latchup is avoided by eliminating the low resistance between the Vdd and Vss power rails caused by the latchup of parasitic and complementary bipolar transistor structure that are present in CMOS devices. These goals have been achieved without the use of guard rings by using a deep n-well to disconnect the pnp collector to npn base connection of two parasitic bipolar transistors, and by using a buried p-well to disconnect the npn collector to pnp base connection of those same two parasitic transistors. Further, the deep n-well is shorted to a supply voltage Vdd, and the buried p-well is shorted to a reference voltage Vss via both the P substrate and a P+ ground tab. The proposed methods do not require additional mask or processes.

Abstract: A method of fabricating a CMOS transistor using Si—B layer to form a source/drain extension junction is disclosed. The fabrication includes the steps as follows; First, a p-type semiconductor substrate and an n-well region are provided. Afterwards, a shallow trench isolation (STI) is formed into the p-type semiconductor substrate and the n-well region, thereby forming a plurality of active regions therebetween. A channel is formed into the p-type semiconductor substrate and the n-well region. Then, a PMOSFET gate pattern and an NMOSFET gate pattern are formed over the p-type semiconductor substrate and the n-well region. A first defined photoresist layer is formed over the n-well region. Afterwards, the n−-type dopant is implanted into the p-type semiconductor substrate to form an n−-type lightly doped source/drain. Then the first defined photoresist layer is removed. A first dielectric layer is deposited over the p-type semiconductor substrate and the n-well region.

Abstract: A layer of well oxide is grown over the n-well or p-well region of the semiconductor substrate. A deep n-well implant is performed in high voltage device region, followed by a deep n-well drive-in of the deep n-well implant. The well oxide is removed; the field oxide (FOX) region is created in the high voltage device region. A layer of sacrificial oxide is deposited on the surface of the semiconductor substrate. A low voltage cluster n-well implant is performed in the high voltage PMOS region of the semiconductor substrate followed, for the high voltage NMOS region, by a low voltage cluster p-well implant which is followed by a buried p-well cluster implant.

Abstract: A twin-well CMOS integrated circuit device includes an n-well region and a p-well region. Each of the n-well and p-well region includes spaced-apart regions which serve as drain and source regions, a channel region between the spaced-apart regions, a shallow trench isolation structure contiguous with one of the spaced-apart regions, and a doped diffused region extending from the surface of the well region, around and underneath the trench isolation structure, to a region beneath the contiguous spaced-apart region.

Abstract: To provide a process for manufacturing a semiconductor integrated circuit device in which ion implantation of an embedded diffused layer for forming triple-well and oxide film etching for forming two types of gate oxide films having different thicknesses is performed by only one photoetching step, the process being capable of reducing the manufacturing cost, and speeding up the circuit operation by making the gate oxide film of the peripheral unit thinner than that of the I/O circuit unit. A resist mask having a given width ranging in a given range which will be formed on the silicon oxide film is formed in a gate forming area in a region where an embedded N-type layer will be formed in a P-type silicon substrate and it is desired to make the thickness of the gate oxide film thicker. The embedded N-type layer is also formed even immediately below the resist mask by conducting an ion implantation at a given energy via the resist mask.

Abstract: A photoresist pattern through which a first well forming region and a second well forming region are exposed is formed over a semiconductor substrate, used as the mask to dope the semiconductor substrate with an impurity thereby to form buried n-wells, and further used as the mask to dope the same with an impurity thereby to form shallow p-wells in a self-alignment manner over the buried n-wells. Subsequently, the photoresist pattern is removed. After this, a photoresist pattern through which the outer peripheral region of the first well forming region and a third well forming region are exposed is formed over the major surface of the semiconductor substrate, and used as the mask to dope the semiconductor substrate with an impurity thereby to form shallow p-wells.

Abstract: This invention proposes a process to form planarized twin-wells for CMOS devices. After depositing pad oxide and a silicon nitride layers, a high-energy phosphorus ion implantation is performed to form the N-well by using a photoresist as a mask. A thick oxide layer deposited by liquid phase deposition process is then grown on the N-well region part of the silicon nitride layer, but not on the photoresist. After stripping the photoresist, a high-energy boron ion implantation is carried out to form the P-well by using the LPD-oxide layer as a mask. The thick LPD-oxide layer is removed by BOE or HF solution. Trenched isolation regions are formed to isolate and define active regions. After removing the pad oxide and the silicon nitride layer, the CMOS device is fabricated by standard processes.

Abstract: The present invention provides a method of forming first and second transistor devices. A first region of silicide is formed over a first portion of a gate dielectric that overlies a first well region in a semiconductor substrate. A second region of silicide is formed over a second portion of the gate dielectric. The second portion of the gate dielectric overlies a second well region in the semiconductor substrate. First and second doped junction regions are formed in the first and second well regions respectively.

Abstract: A method to fabricate simultaneously a MOS transistor and an ESD protective transistor in a silicon substrate is disclosed. The ESD protective devices are fabricated with a double diffused drain (DDD) junction. In the functional region, a MOSFET structure is characterized as having an anti-punchthrough region beneath the poly-gate, LDD regions beneath sidewall spacers and a silicide layer on the source/drain and the poly-gate. In addition, the n+p junction are ultra shallow. Furthermore, the invention utilizes a liquid phase deposition (LPD) oxide layer to serve as a hard mask for the spacer forming process, salicide process and the S/D implant so as to simplify the fabricating process.

Abstract: A method of forming a semiconductor memory device formed on a semiconductor substrate with an N-well and a P-well comprises the following steps. Form over a substrate the combination of a gate oxide layer and a gate layer patterned into gate stacks with sidewalls for an NMOS FET device over a P-well in the substrate and a PMOS FET device over an N-well. Form P− lightly doped S/D regions in the N-well and N− lightly doped S/D regions in the P-well. Form spacers on the sidewalls of the gate stacks. Thereafter form deep N− lightly doped S/D regions in the P-well, and form deep P− lightly doped S/D regions in the N-well. Form heavily doped P++ regions self-aligned with the gate below future P+ S/D sites to be formed self-aligned with the spacers in the N-well, and form heavily doped N++ regions self-aligned with the gate below future N+ S/D sites to be formed self-aligned with the spacers in the P-well.

Abstract: A method and structure for improving the latch-up characteristic of semiconductor devices is provided. A dual depth STI is used to isolate the wells from each other. The trench has a first substantially horizontal surface at a first depth and a second substantially horizontal surface at a second depth which is deeper than the first depth. The n- and p-wells are formed on either side of the trench. A highly doped region is formed in the substrate underneath the second substantially horizontal surface of the trench. The highly doped region abuts both the first and the second wells and extends the isolation of the trench.

Abstract: A high voltage transistor, formed in a bulk semiconductor material, has a gate region defined by a relatively thick field oxide and a source and drain on opposite sides of the field oxide.

Abstract: A method of forming a twin well includes the steps of: forming a field oxide layer on a semiconductor substrate to define active regions of a device, and forming a first mask which exposes a predetermined active region of the semiconductor substrate; ion-implanting a first conductivity type impurity into the exposed region of the semiconductor substrate using the first mask as an ion implantation mask, to form a first well; ion-implanting a second conductivity type impurity to penetrate the first mask, to form a buried region which is self-aligned with the first well and comes into contact with the bottom of the field oxide layer; removing the first mask, and forming a second mask which is to expose the first well of the semiconductor substrate; and ion-implanting a second conductivity impurity into the exposed region of the semiconductor substrate to levels deeper and shallower than the buried region using the second mask as an ion implantation mask, to form a second well including the buried region.

Abstract: A semiconductor structure comprises first gate conductors which wrap around N-wells of buried-channel P-type metal oxide semiconductor field effect transistors and second gate conductors which do not wrap around P-wells of surface-channel N-type metal oxide semiconductor field effect transistors and a method of manufacturing the same comprises forming insulators adjacent each of the N-wells and the P-wells, protecting the N-wells with a patterned mask, forming first divots in areas of the insulators adjacent the N-wells and forming second divots in areas of the insulators adjacent P-wells, wherein the first divots have a greater depth than the second divots.

Abstract: A semiconductor device (2) includes contact gate structures (28, 30) associated with contacts (82, 84) to source/drain regions (42, 44). Each contact (82, 84) includes a polysilicon layer (50) overlying the associated contact gate structure (28, 30) and source/drain region (42, 44). The polysilicon layer (50) may include different doped regions (52, 58) in accordance with the design and function of the device (2).

Abstract: A silicon layer provided in a silicon substrate through a buried oxide film includes a silicon island partitioned by a trench. A surface of the silicon island in the trench is covered with a side wall oxide film, and LDMOS transistors are formed in the trench. A first impurity-doped polysilicon layer for applying a substrate potential is disposed between the buried oxide film and the substrate, and a second impurity-doped polysilicon layer is buried in the trench to communicate with the first impurity-doped polysilicon layer. Further, electrodes for applying the substrate potential are disposed on the second impurity-doped polysilicon layer. Accordingly, the substrate potential can be readily applied from the surface of the silicon layer.

Abstract: An ESD protection device including a transistor structure with resistive regions located within active areas thereof. The transistor structure is formed of one or more MOS transistors, preferably N-type MOS transistors. The drain regions of the transistors are modified to reduce the conductivity of those resistive regions by preventing high carrier concentration implants in one or more sections of the drain regions. This is achieved by modifying an N LDD mask and the steps related thereto, as well as a silicide exclusion mask and the steps related thereto. The modifications result in the omission of N LDD dopant from the area immediately adjacent to the underlying channel. In addition, portions of a spacer oxide remain over the drain region to be formed. Subsequent implant and siliciding steps are effectively blocked by the spacer oxide that remains, leaving a low-density drain (LDD) charge carrier concentration in those regions, except where omitted.

Abstract: The method of manufacturing a CMOS transistor according to the present invention comprises the steps of forming a field oxide at a selected region on a semiconductor substrate to isolate a first region for a NMOS transistor from a second region for a PMOS transistors; forming a P-well region and a N-well region in the first and second regions, respectively; forming a gate oxide film and a gate electrode on selected regions of the first and second regions; implanting low concentration N-type impurities ions to form low concentration impurity implantation regions within the first and second regions; forming spacers at said side walls of the gate electrode and the gate oxide film; forming a high concentration implantation region in the first and second regions; and implanting N-type impurity ions into the second region to form a punch stop doping layer below said low concentration impurity implantation region of the second region.

Abstract: An MOSFET includes a substrate, an active region on the substrate, a first insulating element and a second insulating element located a distance apart from each other on the active region, the first and second insulating elements dividing the active region into a source region, a drain region, and a channel region, the channel region being disposed between the source region and the drain region, a third insulating film over the active region between the first and second insulating films, and a gate electrode over the third insulating film.

Abstract: A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes a first pair of source/drain regions on either side of a first channel region and a second pair of source/drain regions on either side of a second channel region. One of the first pair of source/drain regions is proximal to one of the second pair of source/drain regions. First and second laterally displaced MOS transistors are formed partially within the semiconductor substrate. An isolation trench is formed through the proximal source/drain regions and the trench is filled with a trench dielectric material such that the proximal source/drain regions are electrically isolated whereby the first transistor is electrically isolated from the second transistor.

Abstract: A new method for forming polysilicon lines using a SiON anti-reflective coating during photolithography wherein a thin oxide protection layer is formed over the polysilicon sidewalls and active area surfaces after etching to prevent damage caused by removal of the SiON in the fabrication of integrated circuits is achieved. A gate oxide layer is provided on the surface of a silicon substrate. A polysilicon layer is deposited overlying the gate oxide layer. A SiON anti-reflective coating layer is deposited overlying the polysilicon layer. A photoresist mask is formed over the SiON anti-reflective coating layer. The SiON anti-reflective coating layer, polysilicon layer, and gate oxide layer are etched away where they are not covered by the photoresist mask to form polysilicon lines. The polysilicon lines and the silicon substrate are oxidized to form a protective oxide layer on the sidewalls of the polysilicon lines and on the surface of the silicon substrate.

Abstract: A memory device comprising a semiconductor material substrate with a dopant of a first type; a first semiconductor material well with a dopant of a second type formed in the substrate; a second semiconductor material well with a dopant of the first type formed in said first well; an array of memory cells formed within said second well. Each memory cell comprises a first electrode and a second electrode respectively formed by a first and a second doped regions with dopant of the second type formed in said second well, and a control gate electrode.