Abstract: A semiconductor device capable of a high-speed operation is provided. The semiconductor device is provided with low concentration impurity regions, a gate electrode formed with gate oxide film interposed between the gate electrode and a silicon substrate, an etching stopper, an interlayer insulating film having a contact hole and having an etching rate greater than that of the etching stopper, a high concentration impurity region formed by implanting an impurity into the silicon substrate through the contact hole, a plug layer filling the contact hole, and an interconnection layer.

Abstract: A method for making an integrated circuit device includes forming at least one interconnect structure adjacent a substrate by forming at least one barrier layer, forming a doped copper seed layer on the at least one barrier layer, and forming a copper layer on the doped copper seed layer. The method may further include annealing the integrated circuit device after forming the copper layer to diffuse the dopant from the doped copper seed layer into grain boundaries of the copper layer. The doped copper seed layer may include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant to provide the enhanced electromigration resistance. Forming the copper layer may comprise plating the copper layer. In addition, forming the copper layer may comprise forming the copper layer to include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant.

Abstract: Vacuum processing equipment capable of preventing particles from sticking to objects to be processed in vacuum vessels. The vacuum equipment comprises a series of vacuum vessels separated by doors, and the pressure in the vessels are reducible respectively. The vessels are so configured that objects to be processed are movable among them, and there is provided light projection means for projecting ultra rays on gases introduced to at least of the vessels.

Abstract: When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.

Abstract: Steep concentration gradients are achieved in semiconductor device of small sizes by using implanted polycrystalline material such as polysilicon as a solid diffusion source. Rapid diffusion of impurities along grain boundaries relative to diffusion rates in monocrystalline materials provides a substantially constant impurity concentration at the interface between polycrystalline material and monocrystalline material. Steepness of the impurity concentration gradient is thus effectively scaled as transistor size is decreased to counter increased short channel and other deleterious effects.

Abstract: A method of selectively oxidizing a composite film. According to the present invention a substrate of having a composite film comprising of lower silicon film, a barrier layer, and upper metal film on the barrier layer is placed into a reaction chamber. An inert gas is then fed into reaction chamber to create an inert ambient in the reaction chamber. The temperature of the substrate is then raised or ramped from first temperature to a second temperature in the inert ambient. After the temperature of the substrate is raised to the second temperature the substrate is exposed to an ambient which oxidizes the silicon but which does not oxidize the metal.

Abstract: Embodiments include a semiconductor device including a well structure such that well areas can be formed with a higher density of integration and a plurality of high-voltage endurable transistors can be driven independently of one another with different voltages, and a method of manufacturing the semiconductor device. The semiconductor device may include a triple well comprising a first well formed in a silicon substrate and having a first conductivity type (P-type), a second well formed in adjacent relation to the first well and having a second conductivity type (N-type), and a third well formed in the second well and having the first conductivity type (P-type). A high-voltage endurable MOSFET is provided in each of the wells. Each MOSFET has an offset area in the corresponding well around a gate insulating layer. The offset area is formed of a low-density impurity layer which is provided under an offset LOCOS layer on the silicon substrate.

Abstract: A CMOS imager having an epitaxial layer formed below pixel sensor cells is disclosed. An epitaxial layer is formed between a semiconductor substrate and a photosensitive region to improve the cross-talk between pixel cells. The thickness of the epitaxial layer is optimized so that the collection of signal carriers by the photosensitive region is maximized.

Abstract: A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the gate electrode. In one configuration, the thickness of the silicon oxide layer under the sidewall structure is thicker than the thickness of the silicon oxide layer under the gate electrode.

Abstract: A field oxide film is provided in the surface of a semiconductor substrate. An interlayer insulating film is provided on the semiconductor substrate so as to cover an active layer. A contact hole exposing the surface of the active layer is provided in the interlayer insulating film. A conductor fills the contact hole so as to be electrically connected to the surface of the active layer. The end portion of the field oxide film has a surface perpendicular with respect to the surface of the semiconductor substrate. As a result, a dynamic random access memory can be obtained which is improved so that leakage current is reduced, which in turn increases a hold time of information.

Abstract: A method for making a dual-gate oxide field effect transistors is achieved. The method utilizes a patterned thin silicon nitride layer and a single rapid thermal oxidation step to form a thicker gate oxide for memory and peripheral circuits while forming a thin nitrogen rich gate oxide for high-performance logic circuits. After forming STI around the logic and memory call areas and removing any native oxide, a thin CVD silicon nitride layer is deposited. The Si3N4 is patterned to leave portions over the logic device areas. A single rapid thermal oxidation process is performed to grow a thicker gate oxide on the exposed memory areas while concurrently the Si3N4 is slowly converted to a nitrogen-rich oxide and forms a thinner gate oxide on the logic device areas. The thinner nitrogen-rich gate oxide also retards boron diffusion to make more stable devices.

Abstract: In a method for integrating a high-voltage device and a low-voltage device, a substrate includes a first isolation region separating a high-voltage device region and a low-voltage device region, a second isolation region formed in a scribe region, and a patterned insulating layer that exposes the first and second isolation regions. A patterned photoresist, formed over the substrate, exposes a portion of the patterned insulating layer in the high-voltage device region and a portion of the second isolation region in the scribe region. A doped region and a trench are respectively formed in the substrate under the exposed portion of the patterned insulating layer and in the exposed portion of the second isolation region. The patterned photoresist and the patterned insulating layer are subsequently removed. First and second gate structures are respectively formed in the high-voltage and low-voltage device regions by using the trench as an alignment mark.

Abstract: The invention includes a laterally diffused metal oxide semiconductor transistor comprising a gate electrode and comprising tapered oxide self aligned to the gate electrode and a method of making the transistor.

Abstract: A first amorphous semiconductor film is formed on an insulating surface. A catalyst element for promoting crystallization is added thereto. Thereafter, by a first heat treatment in an inert gas, a first crystalline semiconductor film is formed. A barrier layer and a second semiconductor layer are formed on the first crystalline semiconductor film. The second semiconductor layer contains a rare gas element at a concentration of 1×1019 to 2×1022/cm3, preferably 1×1020 to 1×1021/cm3 and oxygen at a concentration of 5×1017 to 1×1021/cm3. Subsequently, by a second treatment in an inert gas, the catalyst element remaining in the first crystalline semiconductor film is moved to the second semiconductor film.

Abstract: A method of forming an oxidation diffusion barrier stack for use in fabrication of integrated circuits includes forming an inorganic antireflective material layer on a semiconductor substrate assembly with an oxidation diffusion barrier layer then formed on the inorganic antireflective material layer. Another method of forming such a stack includes forming a pad oxide layer on the semiconductor substrate assembly with an inorganic antireflective material layer then formed on the pad oxide layer and an oxidation diffusion barrier layer formed on the antireflective material layer. The antireflective material layer may include a layer of material selected from the group of silicon nitride, silicon oxide, and silicon oxynitride and further may be a silicon-rich layer. The oxidation diffusion barrier stacks may be used for oxidation of field regions for isolation in an integration circuit. Further, the various oxidation diffusion barrier stacks are also described.

Abstract: The present invention provides a semiconductor integrated circuit having excellent junction characteristics when applying the silicide technology to an extremely narrowed diffusion layer between adjacent gate electrodes as well as a method for manufacturing the same. To attain this object, a configuration of the invention has electrode layers formed on a semiconductor substrate, sidewall layers formed on the side walls of electrode layers, and high-melting point metal silicide layers formed on the electrode layers, wherein the sidewall layers are connected together. This makes it possible to eliminate abnormal growth during silicide formation because of the fact that the region defined between the electrode layers on the substrate is covered by the sidewall layers.

Abstract: A method of fabricating a semiconductor device applies a LOCOS profile characteristic to an edge portion of an STI in a HV region to thereby lower compressive stress that is concentrated on the side of the STI. A field oxide film is formed so that only edge portions of HV region (active region II) may be in contact with a comparatively stiff STI, and then, a thick gate oxide film is formed on the HV region by utilizing a nitride film as a mask. After the nitride film as a mask is removed, a thin gate oxide film is formed on a LV region (an active region I in which a thin gate oxide film is formed). As a result, a thinning phenomenon of a gate oxide film at an edge portion of STI is prevented that otherwise would occur when the gate oxide film for HV grows in a normal STI structure by utilizing a nitride film as a mask.

Abstract: A semiconductor integrated circuit having an input protection device which is suitable for receiving inputs of signals having voltages higher than the internal power supply voltage is provided. The input protection device consists of an offset NMOS transistor in which one of heavily doped N-type diffusion layers is electrically connected to a signal input terminal of the semiconductor integrated circuit. In the NMOS transistor, the field isolation structure is a trench structure, and the heavily doped N-type diffusion layers are offset from the gate electrode. Since a parasitic bipolar action easily occurs according to this construction, the protective function against overcurrent caused by static electricity or the like is not impaired. Since signal voltages are by no means applied directly to the gate oxide of the protection device during normal operation, signals with voltages higher than the internal power supply voltage can be input.

Abstract: A fabrication method for a memory device with a floating gate is provided. A substrate is provided. A channel doping step is performed on the substrate, wherein the actual threshold voltage of the subsequently formed memory device becomes greater than the preset threshold voltage. A stack gate and source/drain regions are then sequentially formed on the substrate to complete the formation of the memory device. The drain-turn-on leakage is prevented by an increase of the actual threshold voltage.

Abstract: The current density profile in the conduction channel of a field effect transistor is controlled and thermal gradients are limited under extreme operating conditions by providing lateral resistive ballasting at the source/drain regions adjacent the conduction channel. A distributed resistance is formed by inhibiting conversion of a region of deposited salicide from a high resistance phase state to a low resistance phase state through formation of the deposit with a width or area less than a critical dimension.

Abstract: There is provided a method for manufacturing semiconductor memory devices includes the steps of; forming, for example, an N-type MOS transistor as a memory-cell selecting transistor on a P-type silicon substrate beforehand; forming, as a capacitive-element manufacturing step, an HSG on a first amorphous silicon film which provides a lower electrode; and diffusing an impurity into this HSG and then removing a surface layer of the HSG.

Abstract: A method of forming an oxidation diffusion barrier stack for use in fabrication of integrated circuits includes forming an inorganic antireflective material layer on a semiconductor substrate assembly with an oxidation diffusion barrier layer then formed on the inorganic antireflective material layer. Another method of forming such a stack includes forming a pad oxide layer on the semiconductor substrate assembly with an inorganic antireflective material layer then formed on the pad oxide layer and an oxidation diffusion barrier layer formed on the antireflective material layer. Another method of forming the stack includes forming a pad oxide layer on the semiconductor substrate assembly. A first oxidation diffusion barrier layer is then formed on the pad oxide layer, an inorganic antireflective material layer is formed on the first oxidation diffusion barrier layer, and a second oxidation diffusion barrier layer is formed on the inorganic antireflective material layer.

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs on an SOI substrate. The MOSFETs include recessed source and drain regions. The recessed source and drain regions are formed utilizing an amorphous semiconductor layer. The recessed source and drain regions allow sufficient material for silicidation and yet allow an ultra thin channel region to be utilized. The channel region is above an insulative island.

Abstract: A semiconductor photomask set for producing wafer alignment accuracy in a semiconductor fabrication process. The photomask set produces an alignment mark that is accurate for subsequent fabrication after undergoing a dual field oxide (FOX) fabrication process. Prior arts methods have traditionally covered the alignment marks with layers of oxide material.

Abstract: A method for fabricating oxide layers with different thicknesses on a substrate is described. A field oxide layer is formed on the substrate to define a first active region and a second active region therebetween. A first oxide layer is formed over the first active region. A thin oxynitride layer is formed on the first oxide layer.

Abstract: In a process of fabrication of a semiconductor device having its gate insulation films differ from each other in film thickness, each of a semiconductor substrate and a gate insulation film has its surface prevented from being contaminated. This enables a new gate insulation film to be normally formed on the surface of the semiconductor substrate.

Abstract: A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

Abstract: A semiconductor device having two or more types of separation oxide film are formed on the substrate of the semiconductor device by different methods so as to correspond with element types formed on the same semiconductor substrate. The method for producing the semiconductor device comprises a first separation oxide film formation process, and a second separation oxide film formation process. In the first separation oxide film formation process, a first mask layer is formed on the semiconductor substrate, the first mask layer of the element separation region of the logic element is selectively removed and the semiconductor substrate in the region area selectively oxidized. In second separation oxide film formation process, the remaining first mask layer is removed, a second mask layer is formed, the second mask layer of the element separation region of DRAM elements is then selectively removed, and the semiconductor substrate of the region is selectively oxidized.

Abstract: For fabricating a semiconductor device having gate oxide films of different film thicknesses and a device isolation oxide film having an elevated device isolation characteristics, an oxidation-resistant film such as a nitride film is formed to cover the whole surface of a semiconductor substrate having a plurality of active regions defined by a device isolation oxide film and covered with a thin oxide film. The oxidation-resistant film and the thin oxide film are removed using, as a mask, a first resist exposing a first device formation area, and after the first resist is removed, a first gate oxide film is formed by thermally oxidizing the whole surface.

Abstract: A high-voltage device. A substrate has a first conductive type. A first well region with the first conductive type is located in the substrate. A second well region with the second conductive type is located in the substrate but is isolated from the first well region. Several field oxide layers are located on a surface of the second well region. A shallow trench isolation is located between the field oxide layers in the second well region. A first doped region with the second conductive type is located beneath the field oxide layers. A second doped region with the first conductive type is located beneath the shallow trench isolation in the second well region. A third well region with the first conductive type is located in the first well region and expands from a surface of the first well region into the first well region. A gate structure is positioned on the substrate between the first and the second well regions and covers a portion of the first, the third well regions and the field oxide layers.

Abstract: An active pixel sensor cell, and the process for forming the active pixel sensor cell, featuring a pinned photodiode structure, and a readout region, located in a region of the pinned photodiode structure, has been developed. The process features the formation of a N+ readout region, performed simultaneously with the formation of the N+ source/drain region of the reset transistor, however with the N+ readout region placed in an area to be used for the pinned photodiode structure. The pinned photodiode structure is next formed via formation of a lightly doped N type well region, used as the lower segment of the pinned photodiode structure, followed by the formation of P+ region, used as the top segment of the pinned photodiode structure, with the N+ readout region, surrounded by the P+ region.

Abstract: CMOS devices and process for fabricating low voltage, high voltage, or both low voltage and high voltage CMOS devices are disclosed. According to the process, p-channel stops and source/drain regions of PMOS devices are implanted into a substrate in a single step. Further, gates for both NMOS and PMOS devices are doped with n-type dopant and NMOS gates are self-aligned.

Abstract: A process for forming self-aligned, twin well regions for a CMOS device, without the use of an oxidation retarding silicon nitride layer, has been developed. A first ion implantation procedure is used to place N type ions in a first portion of a semiconductor substrate, followed by a wet thermal oxidation procedure resulting in the growth of a thick silicon dioxide layer on the N type ions, in the first portion of the semiconductor substrate, while growing a thin silicon dioxide layer on a second portion of the lightly doped, P type semiconductor substrate. A second ion implantation procedure places P type ions through the thin silicon dioxide layer, into the second portion of the semiconductor substrate, while the thick silicon dioxide layer prevents the P type ions from reaching the first portion of the semiconductor substrate.

Abstract: Isolation regions are formed with greater accuracy and consistency by forming an oxide-silicon nitride stack and then depositing an amorphous silicon antireflective layer, on the silicon nitride layer before patterning. Embodiments also include depositing the silicon nitride layer and the amorphous silicon layer in the same tool.

Abstract: An MOS device is provided using indium as a threshold adjust implant in the channel regions of an NMOS device and/or in the conductive gate overlying the channel region in a PMOS device. Indium ions are relatively immobile and achieve location stability in the areas in which they are implanted. They do not readily segregate and diffuse in the lateral directions as well as in directions perpendicular to the silicon substrate. Placement immobility is necessary in order to minimize problems of threshold skew and gate oxide thickness enhancement. Additionally, it is believed that indium atoms within the channel region minimize hot carrier effects and the problems associated therewith.

Abstract: Process of manufacturing a semiconductor device comprising a step of forming recessed zones in a semiconductor layer of a first conductivity type, a step of oxidation for forming a gate oxide layer at the sidewalls of the recessed zones, a step of forming a polysilicon gate electrode inside the recessed zones, a step of forming body regions of a second conductivity type in the semiconductor layer between the recessed zones, and a step of forming source regions of the first conductivity type in the body regions. The step of forming recessed zones comprises a step of local oxidation of the surface of the semiconductor layer wherein the recessed zones will be formed, with an oxide growth at the semiconductor layer's cost in order to obtain thick oxide regions penetrating in the semiconductor layer, and a step of etching wherein the oxide of the thick oxide regions is removed.

Abstract: An integrated circuit is fabricated with a layer of polysilicon located on top of shallow trench regions. The polysilicon is patterned so that the trench features are not exposed during an etching operation performed on the polysilicon layer. The process of fabricating transistor gate electrodes, therefore, is improved by reducing etch byproducts contributed by the shallow trench regions features.

Abstract: A nonvolatile semiconductor memory cell array is shown which is composed of a plurality of unit cell-arrays arranged in a repeating pattern. Each of the unit cell-arrays includes a first plurality of cell transistors having control gates coupled in common to a first word line and a second plurality of cell transistors having control gates coupled in common to a second word line. The two word lines are arranged in parallel to one another and perpendicular to a bit line. The bit line is connected in common with drains of both the first and second plurality of cell transistors through a bit line contact. A pair of source lines is arranged along each side of the bit line and parallel to the bit line. Each source line is coupled to one transistor from each of the first and second pluralities of cell transistors through a source line contact.

Abstract: A method of fabricating a defect induced buried oxide (DIBOX) region in a semiconductor substrate utilizing an oxygen ion implantation step to create a stable defect region; a low energy implantation step to create an amorphous layer adjacent to the stable defect region, wherein the low energy implantation steps uses at least one ion other than oxygen; oxidation and, optionally, annealing, is provided. Silicon-on-insulator (SOI) materials comprising a semiconductor substrate having a DIBOX region in patterned or unpatterned forms is also provided herein.

Abstract: The present invention is drawn to a semiconductor integrated circuit device employing on the same silicon substrate a plurality of kinds of MOS transistors different in magnitude of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of two power supply units.

Abstract: Memory integrated circuitry includes an array of memory cells formed over a semiconductive substrate and occupying area thereover, at least some memory cells of the array being formed in lines of active area formed within the semiconductive substrate which are continuous between adjacent memory cells, said adjacent memory cells being isolated from one another relative to the continuous active area formed therebetween by a conductive line formed over said continuous active area between said adjacent memory cells. At least some adjacent lines of continuous active area within the array are isolated from one another by LOCOS field oxide formed therebetween. The respective area consumed by individual of said adjacent memory cells is ideally equal to less than 8F2, where “F” is no greater than 0.

Abstract: On the surface of a field oxide film (3 of FIG. 2e) formed-on a substrate region where the effective thickness in the vertical direction of a substrate is diminished due to the presence of a crystal defect (2 of FIG. 1a), the field oxide film is etched by a predetermined thickness until a recess (4 of FIG. 2f) ascribable to the presence of the defect is exposed (step of FIG. 2f). A new oxide film then is formed in an amount corresponding to the above-mentioned thickness on the field oxide film (step of FIG. 3g) to diminish the depth of the recess ascribable to the presence of the defect. To provide a semiconductor device in which leakage between elements can be eliminated with a thin LOCOS oxide film thickness remaining unchanged.

Abstract: The present invention relates to a method of manufacturing a semiconductor device for forming an insulated gate field effect transistor in a completely isolated SOI layer, and has for its object to prevent depletion or inversion surely by introducing impurities of sufficiently high concentration into an SOI layer adjacent to an isolating film filled up between element regions of the SOI layer and a backing insulating layer and to aim at flattening of the SOI substrate surface, and further, includes the steps of implanting impurity ions into a semiconductor layer from an oblique direction so as to reach the semiconductor layer under an oxidation-preventive mask using the oxidation-preventive mask as a mask for ion implantation, heating the semiconductor layer in an oxidizing atmosphere with the oxidation-preventive mask so as to form a local oxide film to isolate the semiconductor layer, and also forming a impurity region with impurities implanted into the semiconductor layer in a region adjacent to the local

Abstract: A SOI structure semiconductor device includes a silicon substrate (1), an insulating oxide layer (2) formed on the silicon substrate (1), a SOI layer (3) formed on the insulating oxide layer (2) a LOCOS oxide layer (4) formed on the insulating oxide layer (2) and contacting with the SOI layer (3) in order to insulate the SOI layer (3), a gate insulation layer (5) formed on the SOI layer (3) and a gate electrode (6) formed on the gate insulation layer (5). The SOI layer (3) has a sectional triangle portion (10) contacting with the LOCOS oxide layer (4). The sectional triangle has an oblique side (12) as a boundary between the SOI layer (4) and the LOCOS oxide layer (3), a height side (13) equal to the thickness of the SOI layer (3) and a base on the lower boundary of the SOI layer (3), in which the ratio of the height side (13) to the base is 4:1 or less.

Abstract: There is provided a trench type element isolation structure wherein no recess develops in the edge part of an imbedded oxide film of a trench type element isolation. Thermal oxidation films having higher etching resistance than a CVD film are formed not only on the surroundings of the imbedded oxide film inside the groove formed on the silicon substrate but also on the lateral sides of the imbedded oxide film projecting upward from the silicon substrate surface.

Abstract: A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P-type base layer. An N-type sink region is proximate the edge of the NMOS region, and twin wells are in the area surrounded with the sink region. N+ source and drain regions are formed in respective wells. As the sink region is interposed between the drain and isolation regions, a breakdown occurs between the sink and isolation regions when a high voltage is applied. Twin wells are also formed in the PMOS region P+ source and drain regions are formed in respective wells. As the N-type well surrounds the source and bulk regions, a breakdown occurs between a buried region and the isolation region when a high voltage is applied.

Abstract: The present invention provides a method for fabricating a field oxide on a semiconductor substrate. A first pad layer and a first mask layer is formed successively on the semiconductor substrate. An opening is formed in the first mask layer to define a region for forming the field oxide. A first field oxide is formed in the opening, which is then removed to form a concave portion. The first pad layer exposed by the concave portion is removed to form a cavity. A second pad layer having a smaller thickness than the first pad layer is formed on the semiconductor substrate. A mask portion is formed in the sidewall of the patterned first mask layer and the cavity. The mask portion in the sidewall of the patterned first mask layer has a thickness less than 300 Å. Finally, thermal oxidation is carried out to form a second field oxide in the concave portion.

Abstract: A NOR type mask ROM has embedded digit lines arranged in stripes sandwiching an active region on a semiconductor substrate, a gate insulating film formed on the surface of the semiconductor substrate, and word lines formed in stripes in a direction perpendicular to the embedded digit lines on the gate insulating film. The embedded digit line is composed of a first groove provided in the surface side region of the semiconductor substrate, a second groove provided at the substrate lower side of the first groove, an insulating film provided on an inner surface of the second groove, and a semiconductor layer doped with an impurity of other conductive type embedded in the first groove and second groove. An impurity diffusion layer of other conductive type functioning as the source and drain is formed by diffusing the impurity contained in the semiconductor layer through the side of the first groove in the active region.

Abstract: A method of forming a semiconductor device includes forming a moat stack outwardly from a substrate, the moat stack comprising a dielectric pad disposed outwardly from the substrate, a silicon buffer structure disposed outwardly from the dielectric pad, and a protective dielectric cap disposed outwardly from the silicon buffer structure. The method further comprises forming a protective sidewall structure outwardly from at least a sidewall of the silicon buffer structure, forming an isolation dielectric region adjacent to the moat stack, after formation of the isolation dielectric region, removing the protective dielectric cap, and forming a conductive gate comprising the silicon buffer structure.

Abstract: The adhesion of a barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by depositing the capping layer under high density plasma conditions at an elevated temperature, such as about 450° C. to about 650° C., e.g. about 450° C. to about 550° C. High density plasma deposition at such elevated temperatures increases the surface roughness of the exposed Cu metallization, thereby increasing adhesion of the deposited capping layer, such as silicon nitride and increasing the density of the silicon nitride capping layer thereby improving its etch stop characteristics. Embodiments of the present invention include treating the exposed surface of the Cu or Cu alloy interconnect member after CMP in a hydrogen-containing plasma, and depositing a silicon nitride capping layer under high density plasma conditions on the treated surface.