Having High Dielectric Constant Insulator (e.g., Ta2o5, Etc.) Patents (Class 438/240)
  • Patent number: 8481384
    Abstract: A method of producing a Metal-Insulator-Metal (MIM) capacitor stack through doping to achieve low current leakage and low equivalent oxide thickness is disclosed. A high K dielectric material is deposited on a non-noble electrode; the dielectric material is doped with oxides from group IIA. The dopant increases the barrier height of metal/insulator interface and neutralizes free electrons in dielectric material, therefore reduces the leakage current of MIM capacitor. The electrode may also be doped to increase work function while maintaining a rutile crystalline structure. The method thereby enhances the performance of DRAM MIM capacitor.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: July 9, 2013
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Hanhong Chen, Pragati Kumar
  • Patent number: 8470665
    Abstract: Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxide buffer layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxide buffer layer acts to improve capacitance and reduce capacitor leakage. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: June 25, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Sam Yang
  • Patent number: 8466021
    Abstract: Stable contact hole forming is attained even when an aluminum oxide film is present between layers provided with contact holes. The process comprises the steps of forming a first element layer on a semiconductor substrate; forming a first interlayer insulating film on the first element layer; forming a second element layer on the first interlayer insulating film; forming a second interlayer insulating film on the second element layer; forming a hole resist pattern on the second interlayer insulating film; conducting a first etching for forming of holes by etching the second interlayer insulating film; and conducting a second etching for extending of holes to the first element layer by etching the first interlayer insulating film.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: June 18, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yukimasa Miyazaki, Kouichi Nagai, Hideaki Kikuchi
  • Publication number: 20130146959
    Abstract: An ETSOI transistor and a capacitor are formed respectively in a transistor and capacitor region thereof by etching through an ETSOI and thin BOX layers in a replacement gate HK/MG flow. The capacitor formation is compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor or varactor. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch.
    Type: Application
    Filed: December 12, 2011
    Publication date: June 13, 2013
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce Doris, Ali Khakifirooz, Ghavam Shahidi
  • Patent number: 8461012
    Abstract: A method for forming a semiconductor structure includes forming an isolation region in a semiconductor substrate; forming a conductive layer over the isolation region; forming a first dielectric layer over the conductive layer; forming a plurality of conductive vias extending through the first dielectric layer to the conductive layer and electrically contacting the conductive layer; forming a second dielectric layer over the first dielectric layer; and forming a conductive ground plane in the second dielectric layer. Each of the plurality of conductive vias is in electrical contact with the conductive ground plane, and the conductive ground plane includes an opening, wherein the opening is located directly over the conductive layer. At least one interconnect layer may be formed over the second dielectric layer and may include a transmission line which transmits a signal having a frequency of at least 30 gigahertz.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: June 11, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Vishal P. Trivedi
  • Patent number: 8455360
    Abstract: A method for fabricating a storage node of a semiconductor device includes forming a sacrificial dielectric pattern with a storage node hole on a substrate, forming a support layer on the sacrificial dielectric pattern, forming a storage node, supported by the support layer, in the storage node hole, performing a full dip-out process to expose the outer wall of the storage node, and performing a cleaning process for removing or reducing a bridge-causing material formed on the surface of the support layer.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: June 4, 2013
    Assignee: SK Hynix Inc.
    Inventors: Hyo Geun Yoon, Ji Yong Park, Sun Jin Lee
  • Patent number: 8450173
    Abstract: Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: May 28, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Rishikesh Krishnan, Daniel Gealy, Vidya Srividya, Noel Rocklein
  • Patent number: 8441060
    Abstract: A nonvolatile memory element includes a first electrode (103) formed on a substrate (101), a resistance variable layer (108) and a second electrode (107), wherein the resistance variable layer has a multi-layer structure including at least three layers which are a first transition metal oxide layer (104), a second transition metal oxide layer (106) which is higher in oxygen concentration than the first transition metal oxide layer (104), and a transition metal oxynitride layer (105). The second transition metal oxide layer (106) is in contact with either one of the first electrode (103) and the second electrode (107). The transition metal oxynitride layer (105) is provided between the first transition metal oxide layer (104) and the second transition metal oxide layer (106).
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: May 14, 2013
    Assignee: Panasonic Corporation
    Inventors: Takeki Ninomiya, Koji Arita, Takumi Mikawa, Satoru Fujii
  • Patent number: 8435905
    Abstract: The present invention provides a manufacturing method of a semiconductor device that has a rapid film formation rate and high productivity, and to provide a substrate processing apparatus.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: May 7, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Sadayoshi Horii, Hideharu Itatani, Kazuhiro Harada
  • Patent number: 8435854
    Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: May 7, 2013
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Sandra Malhotra, Hanhong Chen, Wim Deweerd, Hiroyuki Ode
  • Patent number: 8424177
    Abstract: A method of forming a metal-insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: April 23, 2013
    Assignees: STMicroelectronics (Crolles 2) SAS, NXP B.V. (Dutch Corporation)
    Inventors: Alexis Farcy, Maryline Thomas, Joaquin Torres, Sonarith Chhun, Laurent-Georges Gosset
  • Patent number: 8421140
    Abstract: A capacitor structure and method of forming it are described. In particular, a high-K dielectric oxide is provided as the capacitor dielectric. The high-K dielectric is deposited in a series of thin layers and oxidized in a series of oxidation steps, as opposed to a depositing a single thick layer. Further, at least one of the oxidation steps is less aggressive than the oxidation environment or environments that would be used to deposit the single thick layer. This allows greater control over oxidizing the dielectric and other components beyond the dielectric.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: April 16, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Guy T. Blalock
  • Patent number: 8410535
    Abstract: A capacitor and a manufacturing method thereof are provided. The capacitor includes a first electrode, a first metal layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate. The first metal layer is disposed on the first electrode. The dielectric layer is disposed on the first metal layer, wherein the material of the first metal layer does not react with the material of the dielectric layer. The second electrode is disposed on the dielectric layer.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: April 2, 2013
    Assignee: Nanya Technology Corporation
    Inventors: Kuo-Hui Su, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8409880
    Abstract: Disclosed herein is a method of forming electronic device having thin-film components by using trenches. One or more of thin-film components is formed by depositing a thin-film in the trench followed by processing the deposited thin-film to have the desired thickness.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: April 2, 2013
    Assignee: Crocus Technologies
    Inventors: Jean Pierre Nozieres, Jason Reid
  • Patent number: 8405167
    Abstract: Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an integrated circuit. Embodiments of methods of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices. An embodiment may include forming hafnium tantalum titanium oxide film using a monolayer or partial monolayer sequencing process such as atomic layer deposition.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: March 26, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8399320
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a variety of electronic systems. The lanthanide yttrium aluminum oxide film may be structured as one or more monolayers. The lanthanide yttrium aluminum oxide film may be formed by a monolayer or partial monolayer sequencing process such as using atomic layer deposition.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: March 19, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8375539
    Abstract: A method of manufacturing a low capacitance density, high voltage MIM capacitor and the high density MIM capacitor. The method includes depositing a plurality of plates and a plurality of dielectric layers interleaved with one another. The method further includes etching a portion of an uppermost plate of the plurality of plates while protecting other portions of the uppermost plate. The protected other portions of the uppermost plate forms a top plate of a first metal-insulator-metal (MIM) capacitor and the etching exposes a top plate of a second MIM capacitor.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: February 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: James Stuart Dunn, Zhong-Xiang He, Anthony K. Stamper
  • Patent number: 8372732
    Abstract: A method for fabricating a non-volatile memory device includes repeatedly stacking interlayer dielectric layers and gate conductive layers on a substrate; etching the interlayer dielectric layers and the gate conductive layers to form cell channel holes that expose the substrate, forming a protective layer along a resultant structure, forming a capping layer on the protective layer to fill the cell channel holes, planarizing the protective layer and the capping layer until an uppermost one of the interlayer dielectric layers is exposed, forming a gate conductive layer for select transistors and an interlayer dielectric layer for select transistors on a resultant structure, etching the interlayer dielectric layer and the gate conductive layer, to form select transistor channel holes that expose the capping layer while removing the capping layer buried in the cell channel holes, and removing the protective layer.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: February 12, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: In-Hoe Kim
  • Patent number: 8372748
    Abstract: A method for manufacturing semiconductor device includes forming an interlayer dielectric layer including a contact plug defined therein to electrically couple a semiconductor substrate on which a cell region and a dummy region are defined. A sacrificial layer is formed over the interlayer dielectric layer. An etch stop pattern is formed over the sacrificial layer, the etch stop pattern being vertically aligned to the dummy region. A storage electrode region through the sacrificial layer is defined to expose a first storage electrode contact of the cell region, the second storage electrode contact of the dummy region remaining covered by the sacrificial layer. A conductive layer is deposited within the storage electrode region to form a storage electrode contacting the first storage electrode contact of the cell region.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: February 12, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Dae Jin Park, Jong Won Jang
  • Patent number: 8367561
    Abstract: The present invention relates to a method for enhancing uniformity of metal oxide coatings formed by Atomic Layer Deposition (ALD) or ALD-type processes. Layers are formed using alternating pulses of metal halide and oxygen-containing precursors, preferably water, and purging when necessary. An introduction of modificator pulses following the pulses of the oxygen-containing precursor affects positively on layer uniformity, which commonly exhibits gradients, particularly in applications with closely arranged substrates. In particular, improvement in layer thickness uniformity is obtained. According to the invention, alcohols having one to three carbon atoms can be used as the modificator.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: February 5, 2013
    Assignee: Beneq Oy
    Inventors: Jarmo Maula, Kari Harkonen
  • Patent number: 8349696
    Abstract: A bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a composition that is resistant to oxidation during subsequent anneal steps and have rutile templating capability. Examples include SnO2 and RuO2. The capacitor stack including the bottom layer is subjected to a PMA treatment to reduce the oxygen vacancies in the dielectric layer and reduce the interface states at the dielectric/second electrode interface. The other component of the bilayer (i.e. top layer) is a high work function, high conductivity metal or conductive metal compound.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: January 8, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Hanhong Chen, Hiroyuki Ode
  • Patent number: 8344439
    Abstract: Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: January 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-hyoung Choi, Jung-hee Chung, Cha-young Yoo, Young-sun Kim, Se-hoon Oh
  • Patent number: 8329534
    Abstract: The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material, the hard mask layer having an original thickness, performing at least two partial etching processes on the hard mask layer to thereby define a patterned hard mask layer above the layer of insulating material, wherein each of the partial etching processes is designed to etch through less than the original thickness of the hard mask layer, the hard mask layer having openings formed therein that correspond to a digitline contact and a plurality of storage node contacts for the dual bit memory cell, and performing at least one etching process to form openings in the layer of insulating material for the digitline contact and the plurality of storage node contacts using the patterned hard mask layer as an etch mask.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: December 11, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Jonathan Doebler
  • Patent number: 8324047
    Abstract: In a specific embodiment, the present invention provides an integrated circuit device. The device includes a base substrate having a surface region and an interlayer dielectric material overlying the surface region. The device also has a thickness of single crystal silicon material overlying the interlayer dielectric material. In one or more embodiments, the thickness of single crystal silicon material has a front region and a backside region. The front region faces the interlayer dielectric material. In a preferred embodiment, the device has a plurality of transistor devices spatially arranged in the thickness of silicon crystal silicon material. Each of the transistor devices has a gate structure within a region of the interlayer dielectric material. The device also has an enclosure housing configured to form a cavity between the backside region of the thickness of silicon material and an upper inside region of the enclosure housing.
    Type: Grant
    Filed: November 13, 2010
    Date of Patent: December 4, 2012
    Assignee: MCube Inc.
    Inventor: Xiao “Charles” Yang
  • Patent number: 8318572
    Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO2) for use as a dielectric, thereby leading to predictable and reproducible higher dielectric constant and lower effective oxide thickness and, thus, greater part density at lower cost.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: November 27, 2012
    Assignee: Intermolecular, Inc.
    Inventors: Sunil Shanker, Xiangxin Rui, Pragati Kumar, Hanhong Chen, Toshiyuki Hirota
  • Publication number: 20120292682
    Abstract: In an embodiment of the invention, a method of fabricating a floating-gate PMOSFET (p-type metal-oxide semiconductor field-effect transistor) is disclosed. A silicide blocking layer (e.g. oxide, nitride) is used not only to block areas from being silicided but to also form an insulator on top of a poly-silicon gate. The insulator along with a top electrode (control gate) forms a capacitor on top of the poly-silicon gate. The poly-silicon gate also serves at the bottom electrode of the capacitor. The capacitor can then be used to capacitively couple charge to the poly-silicon gate. Because the poly-silicon gate is surrounded by insulating material, the charge coupled to the poly-silicon gate may be stored for a long period of time after a programming operation.
    Type: Application
    Filed: May 19, 2011
    Publication date: November 22, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shanjen Pan, Allan T. Mitchell, Weidong Tian
  • Patent number: 8296943
    Abstract: The present invention relates to surveillance and/or identification devices having capacitors connected in parallel or in series, and methods of making and using such devices. Devices with capacitors connected in parallel, where one capacitor is fabricated with a relatively thick capacitor dielectric and another is fabricated with a relatively thin capacitor dielectric achieve both a high-precision capacitance and a low breakdown voltage for relatively easy surveillance tag deactivation. Devices with capacitors connected in series result in increased lateral dimensions of a small capacitor. This makes the capacitor easier to fabricate using techniques that may have relatively limited resolution capabilities.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: October 30, 2012
    Assignee: Kovio, Inc.
    Inventors: Patrick Smith, Criswell Choi, James Montague Cleeves, Vivek Subramanian, Arvind Kamath, Steven Molesa
  • Patent number: 8278168
    Abstract: A semiconductor device and associated methods, the semiconductor device including a semiconductor substrate with a first well region, a first gate electrode disposed on the first well region, and a first N-type capping pattern, a first P-type capping pattern, and a first gate dielectric pattern disposed between the first well region and the first gate electrode.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: October 2, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hongbae Park, Hagju Cho, Sunghun Hong, Sangjin Hyun, Hoonjoo Na, Hyung-seok Hong
  • Patent number: 8258041
    Abstract: A method of fabricating metal-bearing structures in an integrated circuit such as metal-polysilicon capacitors using conductive metal compounds. Defects due to organometallic polymers formed during the etch of a hard mask material are minimized by using a process that includes a plasma etch for the hard mask that achieves a predominantly chemical character using a fluorine-based etch chemistry. Using a low-temperature liquid-phase strip of the hard mask photoresist instead of an ash prevents further cross-linking of polymers formed during the plasma etch. Etching the metal-bearing material using a hot fully-concentrated mixture of ammonium hydroxide and hydrogen peroxide allows short etch times that are particularly shortened for tantalum nitride films deposited with a nitrogen concentration of about 30 percent or greater.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: September 4, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Srinivas Raghavan, Kalyan Cherukuri, Thomas E. Lillibridge, Richard A. Faust
  • Patent number: 8257984
    Abstract: A ferroelectric capacitor and a method of manufacturing the same are provided, wherein the ferroelectric capacitor of a semiconductor device, which sequentially includes a lower electrode, a ferroelectric layer, and an upper electrode on a conductive layer connected to a transistor formed on a semiconductor substrate, includes an oxidation preventing layer between the conductive layer and the lower electrode. The oxidation preventing layer prevents the conductive layer from being oxidized during high-temperature heat treatment of the ferroelectric layer. Accordingly, the oxidation resistivity of the interfaces of the conductive layer, used as a storage node, and the lower electrode, which faces the conductive layer, increases, so a temperature at which a ferroelectric thin layer is formed can be also increased. Consequently, a ferroelectric thin layer having excellent characteristics may be obtained.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: September 4, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: June-key Lee, Young-soo Park
  • Patent number: 8258053
    Abstract: In sophisticated semiconductor devices including transistors having a high-k metal gate electrode structure, disposable spacers may be provided on the encapsulating spacer element with a reduced width so as to not unduly increase a lateral offset of a strain-inducing material to be incorporated into the active region. For this purpose, a multi-layer deposition may be used in combination with a low pressure CVD process.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: September 4, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Matthias Kessler, Andreas Kurz
  • Patent number: 8247289
    Abstract: A capacitor having a high quality and a manufacturing method of the same are provided. A capacitor has a lower electrode formed on an oxide film, a dielectric layer formed on the lower electrode, an upper electrode formed so as to face the lower electrode with the dielectric layer between, and an upper electrode formed so as to cover the upper electrode, an opening portion of the upper electrode and an opening portion of the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to pattern the dielectric layer by using the upper electrode as a mask, and provide a capacitor having a high-quality dielectric layer by preventing impurity diffusion into the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to prevent the dielectric layer from being exposed to etching liquid, liquid developer, etc.
    Type: Grant
    Filed: August 23, 2006
    Date of Patent: August 21, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Yoshiki Yamanishi, Muneo Harada, Takahiro Kitano, Tatsuzo Kawaguchi, Yoshihiro Hirota, Kinji Yamada, Tomotaka Shinoda, Katsuya Okumura, Shuichi Kawano
  • Patent number: 8241980
    Abstract: Stable contact hole forming is attained even when an aluminum oxide film is present between layers provided with contact holes. The process comprises the steps of forming a first element layer on a semiconductor substrate; forming a first interlayer insulating film on the first element layer; forming a second element layer on the first interlayer insulating film; forming a second interlayer insulating film on the second element layer; forming a hole resist pattern on the second interlayer insulating film; conducting a first etching for forming of holes by etching the second interlayer insulating film; and conducting a second etching for extending of holes to the first element layer by etching the first interlayer insulating film.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: August 14, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yukimasa Miyazaki, Kouichi Nagai, Hideaki Kikuchi
  • Patent number: 8237244
    Abstract: A method of manufacturing a semiconductor device includes forming a lower electrode on a semiconductor substrate, applying a photoresist on the lower electrode, forming an opening in the photoresist spaced from the periphery of the lower electrode, forming a high-dielectric constant film of a high-k material having a dielectric constant of 10 or more, performing liftoff so that the high-dielectric-constant film remains on the lower electrode, and forming an upper electrode on the high-dielectric-constant film remaining after the liftoff.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: August 7, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventor: Masahiro Totsuka
  • Patent number: 8222683
    Abstract: To realize miniaturization/high integration and increase in the amount of accumulated charges, and to give a memory structure having a high reliability. A 1 transistor 1 capacitor (1T1C) structure having 1 ferroelectric capacitor structure and 1 selection transistor every memory cell is adopted, and respective capacitor structures are disposed respectively in either one layer of interlayer insulating films of 2 layers having different heights from the surface of a semiconductor substrate.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: July 17, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshimasa Horii
  • Patent number: 8202773
    Abstract: A PMOS transistor is disclosed which includes a nitrogen containing barrier to oxygen diffusion between a gate dielectric layer and a metal gate in the PMOS transistor, in combination with a low oxygen region of the metal gate in direct contact with the nitrogen containing barrier and an oxygen rich region of the metal gate above the low oxygen content metal region. The nitrogen containing barrier may be formed by depositing nitrogen containing barrier material on the gate dielectric layer or by nitridating a top region of the gate dielectric layer. The oxygen rich region of the metal gate may be formed by depositing oxidized metal on the low oxygen region of the metal gate or by oxidizing a top region of the low oxygen region of the metal gate.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: June 19, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, Huang-Chun Wen
  • Patent number: 8202760
    Abstract: In manufacturing a device using an organic TFT, it is essential to develop an element in which a channel length is short or a channel width is narrow to downsize a device. Based on the above, it is an object of the present invention to provide an organic TFT in which characteristic is improved. In view of the foregoing problem, one feature of the present invention is that an element is baked after an organic semiconductor film is deposited. More specifically, one feature of the present invention is that the organic semiconductor film is heated under atmospheric pressure or under reduced pressure. Moreover, a baking process may be carried out in an inert gas atmosphere.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: June 19, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiharu Hirakata, Tetsuji Ishitani, Shuji Fukai, Ryota Imahayashi
  • Patent number: 8191217
    Abstract: A high density capacitor and low density capacitor simultaneously formed on a single wafer and a method of manufacture is provided. The method includes depositing a bottom plate on a dielectric material; depositing a low-k dielectric on the bottom plate; depositing a high-k dielectric on the low-k dielectric and the bottom plate; depositing a top plate on the high-k dielectric; and etching a portion of the bottom plate and the high-k dielectric to form a first metal-insulator-metal (MIM) capacitor having a dielectric stack with a first thickness and a second MIM capacitor having a dielectric stack with a second thickness different than the first thickness.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventors: James S. Dunn, Zhong-Xiang He, Anthony K. Stamper
  • Patent number: 8187933
    Abstract: Some embodiments include dielectric structures. The structures include first and second portions that are directly against one another. The first portion may contain a homogeneous mixture of a first phase and a second phase. The first phase may have a dielectric constant of greater than or equal to 25, and the second phase may have a dielectric constant of less than or equal to 20. The second portion may be entirely a single composition having a dielectric constant of greater than or equal to 25. Some embodiments include electrical components, such as capacitors and transistors, containing dielectric structures of the type described above. Some embodiments include methods of forming dielectric structures, and some embodiments include methods of forming electrical components.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: May 29, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Noel Rocklein, Chris Carlson, Dave Peterson, Cunyu Yang, Praveen Vaidyanathan, Vishwanath Bhat
  • Patent number: 8183108
    Abstract: A method of making dense dielectrics layers via chemical solution deposition by adding inorganic glass fluxed material to high dielectric constant compositions, depositing the resultant mixture onto a substrate and annealing the substrate at temperatures between the softening point of the inorganic glass flux and the melting point of the substrate. A method of making a capacitor comprising a dense dielectric layer.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: May 22, 2012
    Assignee: CDA Processing Limited Liability Company
    Inventors: William J. Borland, Seigi Suh, Jon-Paul Maria, Jon Fredrick Ihlefeld, Ian Burn
  • Patent number: 8178413
    Abstract: A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from alloys such as cobalt-titanium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which inhibits unwanted species migration and unwanted reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: May 15, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8178404
    Abstract: A Metal-Insulator-Metal (MIM) capacitor structure and method of fabricating the same in an integrated circuit improve capacitance density in a MIM capacitor structure by utilizing a sidewall spacer extending along a channel defined between a pair of legs that define portions of the MIM capacitor structure. Each of the legs includes top and bottom electrodes and an insulator layer interposed therebetween, as well as a sidewall that faces the channel. The sidewall spacer incorporates a conductive layer and an insulator layer interposed between the conductive layer and the sidewall of one of the legs, and the conductive layer of the sidewall spacer is physically separated from the top electrode of the MIM capacitor structure. In addition, the bottom electrode of a MIM capacitor structure may be ammonia plasma treated prior to deposition of an insulator layer thereover to reduce oxidation of the electrode.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: May 15, 2012
    Assignee: NXP B.V.
    Inventors: Michael Olewine, Kevin Saiz
  • Patent number: 8168448
    Abstract: The present invention discloses a ferroelectric register and a method for manufacturing a capacitor of the same. The ferroelectric register is configured to reduce probability of data storage failure due to a weak state capacitor, by connecting a plurality of capacitors in parallel in a ferroelectric capacitor unit for storing data, instead of using a single capacitor, thereby improving storage reliability and stability. In addition, the ferroelectric register obtains a data sensing margin by pumping a cell plate signal into not a power voltage level but a pumping voltage level.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: May 1, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hee Bok Kang
  • Patent number: 8153527
    Abstract: A method for fabricating a semiconductor device is provided. The method comprising forming a first layer over a substrate and a second layer over the first layer. A patterned masking layer is subsequently provided over the second layer and a patterned second layer with outwardly tapered sidewalls is formed by isotropically etching exposed portions of the second layer. A patterned first layer is the formed by etching the first layer in accordance with the patterned second layer.
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: April 10, 2012
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Soon Yoong Loh, Carol Goh, Kin Wai Tang, Kim Foong Kong
  • Patent number: 8153514
    Abstract: The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: April 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: Wanda Andreoni, Alessandro C. Callegari, Eduard A. Cartier, Alessandro Curioni, Christopher P. D'Emic, Evgeni Gousev, Michael A. Gribelyuk, Paul C. Jamison, Rajarao Jammy, Dianne L. Lacey, Fenton R. McFeely, Vijay Narayanan, Carlo A. Pignedoli, Joseph F. Shepard, Jr., Sufi Zafar
  • Patent number: 8148249
    Abstract: Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: April 3, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yih-Ann Lin, Ryan Chia-Jen Chen, Chien-Hao Chen, Kuo-Tai Huang, Yi-Hsing Chen, Jr Jung Lin, Yu-Chao Lin
  • Patent number: 8120087
    Abstract: A semiconductor device includes an insulating film provided over a semiconductor substrate, a conductive plug buried in the insulating film, an underlying conductive film which is provided on the conductive plug and on the insulating film and which has a flat upper surface, and a ferroelectric capacitor provided on the underlying conductive film. At least in a region on the conductive plug, the concentration of nitrogen in the underlying conductive film gradually decreases from the upper surface to the inside.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: February 21, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoya Sashida
  • Patent number: 8114739
    Abstract: Methods are provided for fabricating a transistor. An exemplary method involves depositing an oxide layer overlying a layer of semiconductor material, forming an oxygen-diffusion barrier layer overlying the oxide layer, forming a layer of high-k dielectric material overlying the oxygen-diffusion barrier layer, forming a layer of conductive material overlying the layer of high-k dielectric material, selectively removing portions of the layer of conductive material, the layer of high-k dielectric material, the oxygen-diffusion barrier layer, and the oxide layer to form a gate stack, and forming source and drain regions about the gate stack. When the conductive material is an oxygen-gettering conductive material, the oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive material.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: February 14, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Murshed M. Chowdhury, James K. Schaeffer
  • Patent number: 8110491
    Abstract: A manufacturing method of a semiconductor device of the present invention includes the step of forming an insulating film on a substrate, and the step of forming a high dielectric constant insulating film on the insulating film, and the step of forming a titanium aluminum nitride film on the high dielectric constant insulating film, wherein in the step of forming the titanium aluminum nitride film, formation of an aluminum nitride film and formation of a titanium nitride film are alternately repeated, and at that time, the aluminum nitride film is formed firstly and/or lastly.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: February 7, 2012
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Kazuhiro Harada
  • Patent number: RE43673
    Abstract: A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT<10 nm is grown on the exposed device area. The high k dielectric layer is annealed during growth of the SiON dielectric layer. The high k dielectric layer is formed from a metal oxide or its silicate or aluminate and enables a low power device to be fabricated with an EOT<1.8 nm with a suppressed leakage current. The method is compatible with a dual or triple oxide thickness process when forming multiple gates.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: September 18, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tou-Hung Hou, Ming-Fang Wang, Chi-Chun Chen, Chih-Wei Yang, Liang-Gi Yao, Shih-Chang Chen