Having High Dielectric Constant Insulator (e.g., Ta2o5, Etc.) Patents (Class 438/240)
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Patent number: 8647943Abstract: A metal oxide first electrode material for a MIM DRAM capacitor is formed wherein the first and/or second electrode materials or structures contain layers having one or more dopants up to a total doping concentration that will not prevent the electrode materials from crystallizing during a subsequent anneal step. Advantageously, the electrode doped with one or more of the dopants has a work function greater than about 5.0 eV. Advantageously, the electrode doped with one or more of the dopants has a resistivity less than about 1000 ?? cm. Advantageously, the electrode materials are conductive molybdenum oxide.Type: GrantFiled: June 12, 2012Date of Patent: February 11, 2014Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Hanhong Chen, Wim Y. Deweerd, Edward L Haywood, Sandra G Malhotra, Hiroyuki Ode
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Patent number: 8633118Abstract: Methods for forming thin metal and semi-metal layers by thermal remote oxygen scavenging are described. In one embodiment, the method includes forming an oxide layer containing a metal or a semi-metal on a substrate, where the semi-metal excludes silicon, forming a diffusion layer on the oxide layer, forming an oxygen scavenging layer on the diffusion layer, and performing an anneal that reduces the oxide layer to a corresponding metal or semi-metal layer by oxygen diffusion from the oxide layer to the oxygen scavenging layer.Type: GrantFiled: February 1, 2012Date of Patent: January 21, 2014Assignee: Tokyo Electron LimitedInventor: Robert D Clark
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Patent number: 8623725Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield is etched through within the opening. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode.Type: GrantFiled: July 23, 2012Date of Patent: January 7, 2014Assignee: Micron Technology, Inc.Inventors: Mark Kiehlbauch, Kevin R. Shea
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Patent number: 8617949Abstract: A system-on-chip device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, and so forth.Type: GrantFiled: October 6, 2011Date of Patent: December 31, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chi Tu, Wen-Chuan Chiang, Chen-Jong Wang
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Patent number: 8603876Abstract: A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide. Also disclosed are a memory array using the cells, a computing apparatus using the memory array, a method of storing data, and a method of manufacturing.Type: GrantFiled: August 18, 2009Date of Patent: December 10, 2013Assignee: International Business Machines CorporationInventors: Win K. Luk, Jin Cai
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Patent number: 8603877Abstract: Some embodiments include dielectric structures. The structures include first and second portions that are directly against one another. The first portion may contain a homogeneous mixture of a first phase and a second phase. The first phase may have a dielectric constant of greater than or equal to 25, and the second phase may have a dielectric constant of less than or equal to 20. The second portion may be entirely a single composition having a dielectric constant of greater than or equal to 25. Some embodiments include electrical components, such as capacitors and transistors, containing dielectric structures of the type described above. Some embodiments include methods of forming dielectric structures, and some embodiments include methods of forming electrical components.Type: GrantFiled: May 1, 2012Date of Patent: December 10, 2013Assignee: Micron Technology, Inc.Inventors: Noel Rocklein, Chris Carlson, Dave Peterson, Cunyu Yang, Praveen Vaidyanathan, Vishwanath Bhat
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Patent number: 8604532Abstract: A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide. Also disclosed are a memory array using the cells, a computing apparatus using the memory array, a method of storing data, and a method of manufacturing.Type: GrantFiled: August 18, 2009Date of Patent: December 10, 2013Assignee: International Business Machines CorporationInventors: Win K. Luk, Jin Cai
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Patent number: 8592979Abstract: A conductive pattern structure includes a first insulating interlayer on a substrate, metal wiring on the first insulating interlayer, a second insulating interlayer on the metal wiring, and first and second metal contacts extending through the second insulating interlayer. The first metal contacts contact the metal wiring in a cell region and the second metal contact contacts the metal wiring in a peripheral region. A third insulating interlayer is disposed on the second insulating interlayer. Conductive segments extend through the third insulating interlayer in the cell region and contact the first metal contacts. Another conductive segment extends through the third insulating interlayer in the peripheral region and contacts the second metal contact. The structure facilitates the forming of uniformly thick wiring in the cell region using an electroplating process.Type: GrantFiled: April 5, 2012Date of Patent: November 26, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hei-Seung Kim, Gil-Heyun Choi, Ji-Soon Park, Jong-Myeong Lee
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Patent number: 8586430Abstract: In a method of manufacturing a capacitor, a lower electrode of a capacitor is formed on or above a semiconductor substrate. An ozone gas and an inert gas are simultaneously introduced for a predetermined period into a reaction chamber of an atomic layer deposition apparatus in which the semiconductor substrate is set. Then, the ozone gas is exhausted from the reaction chamber by stopping the introduction of the ozone gas and introducing only the inert gas into the reaction chamber, after the introduction. A capacitive dielectric film is formed on the lower electrode by an atomic layer deposition (ALD) method in the atom layer deposition apparatus. An upper electrode of the capacitor is formed on the capacitive dielectric film after the capacitive dielectric film is formed.Type: GrantFiled: January 24, 2007Date of Patent: November 19, 2013Assignee: Elpida Memory, Inc.Inventor: Kenji Komeda
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Patent number: 8574985Abstract: Methods for depositing high-K dielectrics are described, including depositing a first electrode on a substrate, wherein the first electrode is chosen from the group consisting of platinum and ruthenium, applying an oxygen plasma treatment to the exposed metal to reduce the contact angle of a surface of the metal, and depositing a titanium oxide layer on the exposed metal using at least one of a chemical vapor deposition process and an atomic layer deposition process, wherein the titanium oxide layer comprises at least a portion rutile titanium oxide.Type: GrantFiled: March 3, 2011Date of Patent: November 5, 2013Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Xiangxin Rui, Sunil Shanker, Sandra Malhotra, Imran Hashim, Edward Haywood
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Patent number: 8569819Abstract: A metal oxide first electrode layer for a MIM DRAM capacitor is formed wherein the first and/or second electrode layers contain one or more dopants up to a total doping concentration that will not prevent the electrode layers from crystallizing during a subsequent anneal step. One or more of the dopants has a work function greater than about 5.0 eV. One or more of the dopants has a resistivity less than about 1000 ??cm. Advantageously, the electrode layers are conductive molybdenum oxide.Type: GrantFiled: June 11, 2013Date of Patent: October 29, 2013Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Xiangxin Rui, Hiroyuki Ode
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Patent number: 8563420Abstract: A method for manufacturing a printed wiring board includes forming an uncalcined layer containing a raw ceramic material on a first metal layer, firing the uncalcined layer formed on the first metal layer such that a high dielectric constant layer having a ceramic body calcined in a sheet form is formed on the first metal layer, forming a second metal layer on the high dielectric constant layer on the opposite side of the high dielectric constant layer with respect to the first metal layer such that a layered capacitor having the high dielectric constant layer and first and second layer electrodes sandwiching the high dielectric constant layer is formed, and disposing the layered capacitor in a main body.Type: GrantFiled: July 30, 2012Date of Patent: October 22, 2013Assignee: Ibiden Co., Ltd.Inventors: Takashi Kariya, Akira Mochida
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Patent number: 8557713Abstract: Semiconductor devices and methods of forming the semiconductor device are provided, the semiconductor devices including a first dielectric layer on a substrate, and a second dielectric layer on the first dielectric layer. The first dielectric layer has a carbon concentration lower than the second dielectric layer.Type: GrantFiled: April 3, 2009Date of Patent: October 15, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Ha-Jin Lim, Hyung-Suk Jung, Yun-Ki Choi
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Patent number: 8552515Abstract: Disclosed is a novel non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM device structure on a planar surface using a reduced number of masks and etching steps.Type: GrantFiled: August 8, 2012Date of Patent: October 8, 2013Assignee: Cypress Semiconductor CorporationInventors: Shan Sun, Thomas E. Davenport, John Cronin
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Patent number: 8551837Abstract: Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.Type: GrantFiled: February 29, 2012Date of Patent: October 8, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yih-Ann Lin, Ryan Chia-Jen Chen, Chien-Hao Chen, Kuo-Tai Huang, Yi-Hsing Chen, Jr Jung Lin, Yu Chao Lin
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Publication number: 20130256773Abstract: In an embodiment of the invention, a method of fabricating a floating-gate PMOSFET (p-type metal-oxide semiconductor field-effect transistor) is disclosed. A silicide blocking layer (e.g. oxide, nitride) is used not only to block areas from being silicided but to also form an insulator on top of a poly-silicon gate. The insulator along with a top electrode (control gate) forms a capacitor on top of the poly-silicon gate. The poly-silicon gate also serves at the bottom electrode of the capacitor. The capacitor can then be used to capacitively couple charge to the poly-silicon gate. Because the poly-silicon gate is surrounded by insulating material, the charge coupled to the poly-silicon gate may be stored for a long period of time after a programming operation.Type: ApplicationFiled: May 21, 2013Publication date: October 3, 2013Applicant: Texas Instruments IncorporatedInventors: Shanjen Pan, Allan T. Mitchell, Weidong Tian
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Patent number: 8518792Abstract: Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating a damascene self-aligned F-RAM that allows for the formation of a ferroelectric capacitor with separated PZT layers aligned with a preexisting, three dimensional (3-D) transistor structure.Type: GrantFiled: August 8, 2012Date of Patent: August 27, 2013Assignee: Cypress Semiconductor CorporationInventors: Shan Sun, Thomas E. Davenport, John Cronin
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Patent number: 8518791Abstract: Disclosed is a non-volatile, ferroelectric random access memory (F-RAM) device and a method for fabricating the same in the form of a damascene self-aligned F-RAM device comprising a PZT capacitor built on the sidewalls of an oxide trench, while allowing for the simultaneous formation of two ferroelectric sidewall capacitors.Type: GrantFiled: August 8, 2012Date of Patent: August 27, 2013Assignee: Cypress Semiconductor CorporationInventors: Shan Sun, Thomas E. Davenport, John Cronin
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Patent number: 8513634Abstract: A data storage and a semiconductor memory device including the same are provided, the data storage including a lower electrode, a first discharge prevention layer stacked on the lower electrode, a phase-transition layer on the first discharge prevention layer, a second discharge prevention layer stacked on the phase-transition layer, and an upper electrode stacked on the second discharge prevention layer. The phase transition layer includes oxygen and exhibits two different resistance characteristics depending on whether an insulating property thereof changed. The first and second discharge prevention layers block discharge of the oxygen from the phase transition layer.Type: GrantFiled: June 15, 2009Date of Patent: August 20, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-hyun Lee, Sung-ho Park, Myoung-jae Lee, Young-soo Park
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Patent number: 8513724Abstract: A gate insulating film includes an oxygen-containing insulating film and a high dielectric constant insulating film formed on the oxygen-containing insulating film and containing a first metal. The high dielectric constant insulating film further includes a second metal different from the first metal. Part of the high dielectric constant insulating film having the maximum composition ratio of the second metal is away from an interface between the high dielectric constant insulating film and the oxygen-containing insulating film and an interface between the high dielectric constant insulating film and the gate electrode. The second metal exists also in a portion of the oxygen-containing insulating film near the interface between the high dielectric constant insulating film and the oxygen-containing insulating film.Type: GrantFiled: November 7, 2011Date of Patent: August 20, 2013Assignee: Panasonic CorporationInventor: Shinji Takeoka
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Patent number: 8507355Abstract: A method of manufacturing high performance metal-oxide-metal capacitor device that resolves problems with implementing high capacitance in the metal-oxide-metal region by filling with a low-k material both in the metal-oxide-metal region and the metal interconnection region, utilizing performing selective photolithography and etching of the first dielectric layer to define metal-oxide-metal (MOM for short) region, and filling the MOM region with high dielectric constant (high-k) material to realize a high performance MOM capacitor.Type: GrantFiled: December 29, 2011Date of Patent: August 13, 2013Assignee: Shanghai Huali Microelectronics CorporationInventors: Youcun Hu, Lei Li, Chaos Zhang, Feng Ji, Yuwen Chen
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Patent number: 8507967Abstract: Provided are a method of fabricating a semiconductor device having different kinds of capacitors, and a semiconductor device formed using the same. In a fabrication process, after preparing a substrate including a storage capacitor region and a higher voltage resistance capacitor region, a lower electrode layer may be formed on the storage capacitor region and the higher voltage resistance capacitor region. A first dielectric film may be formed on the lower electrode layer, and the first dielectric film of the storage capacitor region may be selectively removed to expose the lower electrode layer of the storage capacitor region. After forming a second dielectric film on the first dielectric film and the exposed lower electrode layer of the storage capacitor region, an upper electrode layer may be formed on the second dielectric film.Type: GrantFiled: January 30, 2009Date of Patent: August 13, 2013Assignee: Samsung Electronics Co., Ltd.Inventor: Hwa-Sook Shin
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Patent number: 8501560Abstract: A thin film capacitor is characterized by forming a lower electrode, coating a composition onto the lower electrode without applying an annealing process having a temperature of greater than 300° C., drying at a predetermined temperature within a range from ambient temperature to 500° C., and calcining at a predetermined temperature within a range of 500 to 800° C. and higher than a drying temperature. The process from coating to calcining is performed the process from coating to calcining once or at least twice, or the process from coating to drying is performed at least twice, and then calcining is performed once. The thickness of the dielectric thin film formed after the first calcining is 20 to 600 nm. The ratio of the thickness of the lower electrode and the thickness of the dielectric thin film formed after the initial calcining step (thickness of lower electrode/thickness of the dielectric thin film) is preferably in the range 0.10 to 15.0.Type: GrantFiled: June 28, 2011Date of Patent: August 6, 2013Assignees: Mitusbishi Materials Corporation, STMicroelectronics(Tours) SASInventors: Hideaki Sakurai, Toshiaki Watanabe, Nobuyuki Soyama, Guillaume Guegan
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Patent number: 8491799Abstract: A method for forming a magnetic tunnel junction cell includes forming a pinning layer, a pinned layer, a dielectric layer and a free layer over a first electrode, forming a second electrode on the free layer, etching the free layer and the dielectric layer using the second electrode as an etch barrier to form a first pattern, forming a prevention layer on a sidewall of the first pattern, and etching the pinned layer and the pinning layer using the second electrode and the prevention layer as an etch barrier to form a second pattern.Type: GrantFiled: June 30, 2008Date of Patent: July 23, 2013Assignee: Hynix Semiconductor Inc.Inventor: Jin-Ki Jung
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Patent number: 8492258Abstract: A manufacturing method of a semiconductor device of the present invention includes the step of forming an insulating film on a substrate, and the step of forming a high dielectric constant insulating film on the insulating film, and the step of forming a titanium aluminum nitride film on the high dielectric constant insulating film, wherein in the step of forming the titanium aluminum nitride film, formation of an aluminum nitride film and formation of a titanium nitride film are alternately repeated, and at that time, the aluminum nitride film is formed firstly and/or lastly.Type: GrantFiled: December 30, 2011Date of Patent: July 23, 2013Assignee: Hitachi Kokusai Electric Inc.Inventor: Kazuhiro Harada
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Patent number: 8486780Abstract: A metal oxide first electrode layer for a MIM DRAM capacitor is formed wherein the first and/or second electrode layers contain one or more dopants up to a total doping concentration that will not prevent the electrode layers from crystallizing during a subsequent anneal step. One or more of the dopants has a work function greater than about 5.0 eV. One or more of the dopants has a resistivity less than about 1000 ?? cm. Advantageously, the electrode layers are conductive molybdenum oxide.Type: GrantFiled: August 29, 2011Date of Patent: July 16, 2013Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Xiangxin Rui, Hiroyuki Ode
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Publication number: 20130175596Abstract: An integrated circuit includes a transistor and a capacitor. The transistor includes a first semiconductor layer and a gate stack located on the first semiconductor layer. The gate stack includes a metal layer and a first high-k dielectric layer. A gate spacer is located on sidewalls of the gate stack. The first high-k dielectric layer is located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer. A first silicide region is located on a first source/drain region. A second silicide region is located on a second source/drain region. The capacitor includes a first terminal that comprises a third silicide region located on a portion of the second semiconductor. A second high-k dielectric layer is located on the silicide region. A second terminal comprises a metal layer that is located on the second high-k dielectric layer.Type: ApplicationFiled: January 6, 2012Publication date: July 11, 2013Applicant: International Business Machines CorporationInventors: Kangguo CHENG, Bruce Doris, Ali Khakifirooz, Ghavam G. Shahidi
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Patent number: 8481384Abstract: A method of producing a Metal-Insulator-Metal (MIM) capacitor stack through doping to achieve low current leakage and low equivalent oxide thickness is disclosed. A high K dielectric material is deposited on a non-noble electrode; the dielectric material is doped with oxides from group IIA. The dopant increases the barrier height of metal/insulator interface and neutralizes free electrons in dielectric material, therefore reduces the leakage current of MIM capacitor. The electrode may also be doped to increase work function while maintaining a rutile crystalline structure. The method thereby enhances the performance of DRAM MIM capacitor.Type: GrantFiled: February 23, 2011Date of Patent: July 9, 2013Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Hanhong Chen, Pragati Kumar
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Patent number: 8470665Abstract: Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxide buffer layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxide buffer layer acts to improve capacitance and reduce capacitor leakage. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.Type: GrantFiled: October 31, 2007Date of Patent: June 25, 2013Assignee: Micron Technology, Inc.Inventor: Sam Yang
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Patent number: 8466021Abstract: Stable contact hole forming is attained even when an aluminum oxide film is present between layers provided with contact holes. The process comprises the steps of forming a first element layer on a semiconductor substrate; forming a first interlayer insulating film on the first element layer; forming a second element layer on the first interlayer insulating film; forming a second interlayer insulating film on the second element layer; forming a hole resist pattern on the second interlayer insulating film; conducting a first etching for forming of holes by etching the second interlayer insulating film; and conducting a second etching for extending of holes to the first element layer by etching the first interlayer insulating film.Type: GrantFiled: July 25, 2012Date of Patent: June 18, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Yukimasa Miyazaki, Kouichi Nagai, Hideaki Kikuchi
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Publication number: 20130146959Abstract: An ETSOI transistor and a capacitor are formed respectively in a transistor and capacitor region thereof by etching through an ETSOI and thin BOX layers in a replacement gate HK/MG flow. The capacitor formation is compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor or varactor. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch.Type: ApplicationFiled: December 12, 2011Publication date: June 13, 2013Applicant: International Business Machines CorporationInventors: Kangguo Cheng, Bruce Doris, Ali Khakifirooz, Ghavam Shahidi
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Patent number: 8461012Abstract: A method for forming a semiconductor structure includes forming an isolation region in a semiconductor substrate; forming a conductive layer over the isolation region; forming a first dielectric layer over the conductive layer; forming a plurality of conductive vias extending through the first dielectric layer to the conductive layer and electrically contacting the conductive layer; forming a second dielectric layer over the first dielectric layer; and forming a conductive ground plane in the second dielectric layer. Each of the plurality of conductive vias is in electrical contact with the conductive ground plane, and the conductive ground plane includes an opening, wherein the opening is located directly over the conductive layer. At least one interconnect layer may be formed over the second dielectric layer and may include a transmission line which transmits a signal having a frequency of at least 30 gigahertz.Type: GrantFiled: February 26, 2010Date of Patent: June 11, 2013Assignee: Freescale Semiconductor, Inc.Inventor: Vishal P. Trivedi
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Patent number: 8455360Abstract: A method for fabricating a storage node of a semiconductor device includes forming a sacrificial dielectric pattern with a storage node hole on a substrate, forming a support layer on the sacrificial dielectric pattern, forming a storage node, supported by the support layer, in the storage node hole, performing a full dip-out process to expose the outer wall of the storage node, and performing a cleaning process for removing or reducing a bridge-causing material formed on the surface of the support layer.Type: GrantFiled: March 28, 2011Date of Patent: June 4, 2013Assignee: SK Hynix Inc.Inventors: Hyo Geun Yoon, Ji Yong Park, Sun Jin Lee
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Patent number: 8450173Abstract: Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process.Type: GrantFiled: June 28, 2011Date of Patent: May 28, 2013Assignee: Micron Technology, Inc.Inventors: Rishikesh Krishnan, Daniel Gealy, Vidya Srividya, Noel Rocklein
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Patent number: 8441060Abstract: A nonvolatile memory element includes a first electrode (103) formed on a substrate (101), a resistance variable layer (108) and a second electrode (107), wherein the resistance variable layer has a multi-layer structure including at least three layers which are a first transition metal oxide layer (104), a second transition metal oxide layer (106) which is higher in oxygen concentration than the first transition metal oxide layer (104), and a transition metal oxynitride layer (105). The second transition metal oxide layer (106) is in contact with either one of the first electrode (103) and the second electrode (107). The transition metal oxynitride layer (105) is provided between the first transition metal oxide layer (104) and the second transition metal oxide layer (106).Type: GrantFiled: September 29, 2009Date of Patent: May 14, 2013Assignee: Panasonic CorporationInventors: Takeki Ninomiya, Koji Arita, Takumi Mikawa, Satoru Fujii
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Patent number: 8435854Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.Type: GrantFiled: November 11, 2011Date of Patent: May 7, 2013Assignees: Intermolecular, Inc., Elpida Memory, Inc.Inventors: Sandra Malhotra, Hanhong Chen, Wim Deweerd, Hiroyuki Ode
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Patent number: 8435905Abstract: The present invention provides a manufacturing method of a semiconductor device that has a rapid film formation rate and high productivity, and to provide a substrate processing apparatus.Type: GrantFiled: June 13, 2006Date of Patent: May 7, 2013Assignee: Hitachi Kokusai Electric Inc.Inventors: Sadayoshi Horii, Hideharu Itatani, Kazuhiro Harada
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Patent number: 8424177Abstract: A method of forming a metal-insulator-metal capacitor having top and bottom plates separated by a dielectric layer, one of the top and bottom plates having at least one protrusion extending into a corresponding cavity in the other of the top and bottom plates, the method including the steps of growing one or more nanofibers on a base surface.Type: GrantFiled: May 6, 2010Date of Patent: April 23, 2013Assignees: STMicroelectronics (Crolles 2) SAS, NXP B.V. (Dutch Corporation)Inventors: Alexis Farcy, Maryline Thomas, Joaquin Torres, Sonarith Chhun, Laurent-Georges Gosset
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Patent number: 8421140Abstract: A capacitor structure and method of forming it are described. In particular, a high-K dielectric oxide is provided as the capacitor dielectric. The high-K dielectric is deposited in a series of thin layers and oxidized in a series of oxidation steps, as opposed to a depositing a single thick layer. Further, at least one of the oxidation steps is less aggressive than the oxidation environment or environments that would be used to deposit the single thick layer. This allows greater control over oxidizing the dielectric and other components beyond the dielectric.Type: GrantFiled: July 3, 2003Date of Patent: April 16, 2013Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Guy T. Blalock
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Patent number: 8409880Abstract: Disclosed herein is a method of forming electronic device having thin-film components by using trenches. One or more of thin-film components is formed by depositing a thin-film in the trench followed by processing the deposited thin-film to have the desired thickness.Type: GrantFiled: May 10, 2012Date of Patent: April 2, 2013Assignee: Crocus TechnologiesInventors: Jean Pierre Nozieres, Jason Reid
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Patent number: 8410535Abstract: A capacitor and a manufacturing method thereof are provided. The capacitor includes a first electrode, a first metal layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate. The first metal layer is disposed on the first electrode. The dielectric layer is disposed on the first metal layer, wherein the material of the first metal layer does not react with the material of the dielectric layer. The second electrode is disposed on the dielectric layer.Type: GrantFiled: April 25, 2011Date of Patent: April 2, 2013Assignee: Nanya Technology CorporationInventors: Kuo-Hui Su, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 8405167Abstract: Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an integrated circuit. Embodiments of methods of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices. An embodiment may include forming hafnium tantalum titanium oxide film using a monolayer or partial monolayer sequencing process such as atomic layer deposition.Type: GrantFiled: August 12, 2011Date of Patent: March 26, 2013Assignee: Micron Technology, Inc.Inventors: Kie Y. Ahn, Leonard Forbes
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Patent number: 8399320Abstract: Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a variety of electronic systems. The lanthanide yttrium aluminum oxide film may be structured as one or more monolayers. The lanthanide yttrium aluminum oxide film may be formed by a monolayer or partial monolayer sequencing process such as using atomic layer deposition.Type: GrantFiled: January 9, 2012Date of Patent: March 19, 2013Assignee: Micron Technology, Inc.Inventors: Kie Y. Ahn, Leonard Forbes
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Patent number: 8375539Abstract: A method of manufacturing a low capacitance density, high voltage MIM capacitor and the high density MIM capacitor. The method includes depositing a plurality of plates and a plurality of dielectric layers interleaved with one another. The method further includes etching a portion of an uppermost plate of the plurality of plates while protecting other portions of the uppermost plate. The protected other portions of the uppermost plate forms a top plate of a first metal-insulator-metal (MIM) capacitor and the etching exposes a top plate of a second MIM capacitor.Type: GrantFiled: August 5, 2009Date of Patent: February 19, 2013Assignee: International Business Machines CorporationInventors: James Stuart Dunn, Zhong-Xiang He, Anthony K. Stamper
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Patent number: 8372732Abstract: A method for fabricating a non-volatile memory device includes repeatedly stacking interlayer dielectric layers and gate conductive layers on a substrate; etching the interlayer dielectric layers and the gate conductive layers to form cell channel holes that expose the substrate, forming a protective layer along a resultant structure, forming a capping layer on the protective layer to fill the cell channel holes, planarizing the protective layer and the capping layer until an uppermost one of the interlayer dielectric layers is exposed, forming a gate conductive layer for select transistors and an interlayer dielectric layer for select transistors on a resultant structure, etching the interlayer dielectric layer and the gate conductive layer, to form select transistor channel holes that expose the capping layer while removing the capping layer buried in the cell channel holes, and removing the protective layer.Type: GrantFiled: October 21, 2011Date of Patent: February 12, 2013Assignee: Hynix Semiconductor Inc.Inventor: In-Hoe Kim
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Patent number: 8372748Abstract: A method for manufacturing semiconductor device includes forming an interlayer dielectric layer including a contact plug defined therein to electrically couple a semiconductor substrate on which a cell region and a dummy region are defined. A sacrificial layer is formed over the interlayer dielectric layer. An etch stop pattern is formed over the sacrificial layer, the etch stop pattern being vertically aligned to the dummy region. A storage electrode region through the sacrificial layer is defined to expose a first storage electrode contact of the cell region, the second storage electrode contact of the dummy region remaining covered by the sacrificial layer. A conductive layer is deposited within the storage electrode region to form a storage electrode contacting the first storage electrode contact of the cell region.Type: GrantFiled: July 9, 2010Date of Patent: February 12, 2013Assignee: Hynix Semiconductor Inc.Inventors: Dae Jin Park, Jong Won Jang
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Patent number: 8367561Abstract: The present invention relates to a method for enhancing uniformity of metal oxide coatings formed by Atomic Layer Deposition (ALD) or ALD-type processes. Layers are formed using alternating pulses of metal halide and oxygen-containing precursors, preferably water, and purging when necessary. An introduction of modificator pulses following the pulses of the oxygen-containing precursor affects positively on layer uniformity, which commonly exhibits gradients, particularly in applications with closely arranged substrates. In particular, improvement in layer thickness uniformity is obtained. According to the invention, alcohols having one to three carbon atoms can be used as the modificator.Type: GrantFiled: July 2, 2008Date of Patent: February 5, 2013Assignee: Beneq OyInventors: Jarmo Maula, Kari Harkonen
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Patent number: 8349696Abstract: A bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a composition that is resistant to oxidation during subsequent anneal steps and have rutile templating capability. Examples include SnO2 and RuO2. The capacitor stack including the bottom layer is subjected to a PMA treatment to reduce the oxygen vacancies in the dielectric layer and reduce the interface states at the dielectric/second electrode interface. The other component of the bilayer (i.e. top layer) is a high work function, high conductivity metal or conductive metal compound.Type: GrantFiled: August 1, 2011Date of Patent: January 8, 2013Assignee: Intermolecular, Inc.Inventors: Hanhong Chen, Hiroyuki Ode
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Patent number: 8344439Abstract: Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.Type: GrantFiled: June 28, 2011Date of Patent: January 1, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-hyoung Choi, Jung-hee Chung, Cha-young Yoo, Young-sun Kim, Se-hoon Oh
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Patent number: 8329534Abstract: The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material, the hard mask layer having an original thickness, performing at least two partial etching processes on the hard mask layer to thereby define a patterned hard mask layer above the layer of insulating material, wherein each of the partial etching processes is designed to etch through less than the original thickness of the hard mask layer, the hard mask layer having openings formed therein that correspond to a digitline contact and a plurality of storage node contacts for the dual bit memory cell, and performing at least one etching process to form openings in the layer of insulating material for the digitline contact and the plurality of storage node contacts using the patterned hard mask layer as an etch mask.Type: GrantFiled: September 28, 2010Date of Patent: December 11, 2012Assignee: Micron Technology, Inc.Inventor: Jonathan Doebler