Having High Dielectric Constant Insulator (e.g., Ta2o5, Etc.) Patents (Class 438/240)
  • Patent number: 8105896
    Abstract: A method of forming a capacitor includes forming a conductive first capacitor electrode material comprising TiN over a substrate. TiN of the TiN-comprising material is oxidized effective to form conductive TiOxNy having resistivity no greater than 1 ohm·cm over the TiN-comprising material where x is greater than 0 and y is from 0 to 1.4. A capacitor dielectric is formed over the conductive TiOxNy. Conductive second capacitor electrode material is formed over the capacitor dielectric. Other aspects and implementations are contemplated, including capacitors independent of method of fabrication.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: January 31, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishwanath Bhat, Noel Rocklein, F. Daniel Gealy
  • Patent number: 8105930
    Abstract: In one embodiment, the method of forming a dielectric layer includes supplying a first precursor at a temperature less than 400 degrees Celsius to a chamber including a substrate. The first precursor includes dysprosium. A first reaction gas is supplied to the chamber to react with the first precursor. A second precursor is supplied at a temperature less than 400 degrees Celsius to the chamber, and the second precursor includes scandium. A second reaction gas is supplied to the chamber to react with the second precursor.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: January 31, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoonsang Choi, Bongjin Kuh, Sunjung Kim, Youngsun Kim, Seunghwan Lee, Sangwook Lim, Chunhyung Chung
  • Patent number: 8102022
    Abstract: In a semiconductor device manufacturing method, an amorphous or microcrystalline metal oxide film is formed over a first metal film which is preferentially oriented along a predetermined crystal plane. After that, a ferroelectric film is formed by a MOCVD method. When the ferroelectric film is formed, the metal oxide film formed over the first metal film is reduced to a second metal film and the ferroelectric film is formed over the second metal film. When the ferroelectric film is formed, the amorphous or microcrystalline metal oxide film is apt to be reduced uniformly. As a result, the second metal film the orientation of which is good is obtained and the ferroelectric film the orientation of which is good is formed over the second metal film. After the ferroelectric film is formed, an upper electrode is formed over the ferroelectric film.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: January 24, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Wensheng Wang
  • Patent number: 8093118
    Abstract: A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a resistor and a metal gate structure. The substrate has a first area and a second area. The resistor is disposed in the first area, wherein the resistor does not include any metal layer. The metal gate structure is disposed in the second area.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: January 10, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Szu Tseng, Che-Hua Hsu, Cheng-Wen Fan, Chih-Yu Tseng, Victor Chiang Liang
  • Patent number: 8093070
    Abstract: A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: January 10, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Francis Gabriel Celii, Kezhakkedath R. Udayakumar, Gregory B. Shinn, Theodore S. Moise, Scott R. Summerfelt
  • Patent number: 8088659
    Abstract: High dielectric films of mixed transition metal oxides of titanium and tungsten, or titanium and tantalum, are formed by sequential chemical vapor deposition (CVD) of the respective nitrides and annealing in the presence of oxygen to densify and oxidize the nitrides. The resulting film is useful as a capacitative cell and resists oxygen diffusion to the underlying material, has high capacitance and low current leakage.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: January 3, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Jiong-Ping Lu, Ming-Jang Hwang
  • Patent number: 8071476
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a cobalt titanium oxide film on a substrate for use in a variety of electronic systems. The cobalt titanium oxide film may be structured as one or more monolayers. The cobalt titanium oxide film may be formed by atomic layer deposition.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: December 6, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8062943
    Abstract: A capacitor with zirconium oxide and a method for fabricating the same are provided. The method includes: forming a storage node; forming a multi-layered dielectric structure on the storage node, the multi-layered dielectric structure including a zirconium oxide (ZrO2) layer and an aluminum oxide (Al2O3) layer; and forming a plate electrode on the multi-layered dielectric structure.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: November 22, 2011
    Assignee: Hynix Semiconductor
    Inventor: Kee-jeung Lee
  • Patent number: 8062966
    Abstract: Semiconductor devices and fabrication methods are provided, in which metal transistor replacement gates are provided for CMOS transistors. The process provides dual or differentiated work function capability (e.g., for PMOS and NMOS transistors) in CMOS processes.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: November 22, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Freido Mehrad, James J. Chambers, Shaofeng Yu
  • Patent number: 8048735
    Abstract: The present invention provides an MIM capacitor using a high-k dielectric film preventing degradation of breakdown field strength of the MIM capacitor and suppressing the increase of the leakage current. The MIM capacitor comprises a first metal interconnect, a fabricated capacitance film, a fabricated upper electrode, and a third metal interconnect. The MIM capacitor is realized by forming an interlayer dielectric film comprising silicon oxide so as to cover the first metal interconnect, then forming a first opening in the interlayer dielectric film to a region corresponding to a via hole layer in the interlayer dielectric film just above the first metal interconnect so as not to expose the upper surface of the first metal interconnect, then forming a second opening to the inside of the first opening so as to expose the surface of the first metal interconnect and then forming a capacitance film and a third metal interconnect.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: November 1, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Kenichi Takeda, Tsuyoshi Fujiwara, Toshinori Imai
  • Patent number: 8049117
    Abstract: A method for manufacturing a printed circuit board with a capacitor embedded therein which has a dielectric film using laser lift off, and a capacitor manufactured thereby. In the method, a dielectric film is formed on a transparent substrate and heat-treated. A first conductive layer is formed on the heat-treated dielectric film. A laser beam is irradiated onto a stack formed, from below the transparent substrate, to separate the transparent substrate from the stack. After the transparent substrate is separated from the stack, a second conductive layer is formed with a predetermined pattern on the dielectric film. Also, an insulating layer and a third conductive layer are formed on the first and second conductive layers to alternate with each other in a predetermined number.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: November 1, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jung Won Lee, Yul Kyo Chung, In Hyung Lee
  • Patent number: 8044452
    Abstract: The present invention provides a high-quality semiconductor device in which deterioration in transistor characteristics and an increase in interface layer due to a gate insulating film are suppressed, and a method for manufacturing the same. In the present invention, an interface layer, a diffusion suppressing layer and a high dielectric constant insulating film are formed sequentially in this order on one surface of a silicon substrate.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: October 25, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Tominaga Koji, Iwamoto Kunihiko, Yasuda Tetsuji, Nabatame Toshihide
  • Patent number: 8039759
    Abstract: A method for manufacturing a printed circuit board with a capacitor embedded therein which has a dielectric film using laser lift off, and a capacitor manufactured thereby. In the method, a dielectric film is formed on a transparent substrate and heat-treated. A first conductive layer is formed on the heat-treated dielectric film. A laser beam is irradiated onto a stack formed, from below the transparent substrate, to separate the transparent substrate from the stack. After the transparent substrate is separated from the stack, a second conductive layer is formed with a predetermined pattern on the dielectric film. Also, an insulating layer and a third conductive layer are formed on the first and second conductive layers to alternate with each other in a predetermined number.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: October 18, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jung Won Lee, Yul Kyo Chung, In Hyung Lee
  • Patent number: 8034680
    Abstract: Provided are a memory device formed using one or more source materials not containing hydrogen as a constituent element and a method of manufacturing the memory device.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: October 11, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kihwan Kim, Youngsoo Park, Junghyun Lee, Changjung Kim, Bosoo Kang
  • Patent number: 8022448
    Abstract: Apparatus and methods for evaporating metal onto semiconductor wafers are disclosed. One such apparatus can include an evaporation chamber that includes a wafer holder, such as a dome, and a test wafer holder that is separate and spaced apart from the wafer holder. In certain implementations, the test wafer can be coupled to a cross beam supporting at least one shaper. A metal can be evaporated onto production wafers positioned in the wafer holder while metal is evaporated on a test wafer positioned in a test wafer holder. In some instances, the production wafers can be GaAs wafers. The test wafer can be used to make a quality assessment about the production wafers.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: September 20, 2011
    Assignee: Skyworks Solutions, Inc.
    Inventors: Lam T. Luu, Shiban K. Tiku, Richard S. Bingle, Jens A. Riege, Heather L. Knoedler, Daniel C. Weaver
  • Patent number: 8021948
    Abstract: A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: September 20, 2011
    Assignee: IMEC
    Inventors: Bogdan Govoreanu, Stefan De Gendt, Sven Van Elshocht, Tom Schram
  • Patent number: 8012824
    Abstract: A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: September 6, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Liang-Gi Yao, Ming-Fang Wang, Shih-Chang Chen, Mong-Song Liang
  • Publication number: 20110212585
    Abstract: A semiconductor device including a capacitor and a proximate high-voltage gate having a boron-barrier layer that ideally serves as part of both the capacitor dielectric and the (high voltage) HV gate oxide. The boron-barrier layer is preferably formed over a poly oxide layer that is in turn deposited on a substrate infused to create a neighboring wells, and N-well over which the capacitor will be formed, and P-well to be overlaid by the HV gate. The boron-barrier helps to reduce or eliminate the harmful effects of boron diffusion from the P-well during TEOS deposition of the gate oxide material.
    Type: Application
    Filed: May 9, 2011
    Publication date: September 1, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chyi-Chyuan Huang, Shyh-An Lin, Chen-Fu Hsu
  • Patent number: 8003462
    Abstract: A first electrode film containing TiAlN and a main dielectric film containing tantalum oxide are formed over a semiconductor substrate. Anneal is performed in the state that the first electrode film and the main dielectric film are formed, to react aluminum (Al) in the first electrode film with oxygen (O) in the main dielectric film and form a subsidiary dielectric film containing aluminum oxide at an interface between the first electrode film and the main dielectric film. A second electrode film is formed facing the first electrode film via the main dielectric film and the subsidiary dielectric film.
    Type: Grant
    Filed: February 4, 2009
    Date of Patent: August 23, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Masaaki Nakabayashi
  • Patent number: 7981741
    Abstract: Deposited thin-film dielectrics having columnar grains and high dielectric constants are formed on heat treated and polished metal foil. The sputtered dielectrics are annealed at low oxygen partial pressures.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: July 19, 2011
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Lijie Bao, Zhigang Rick Li, Damien Reardon, James F. Ryley, Cengiz A. Palanduz
  • Patent number: 7977150
    Abstract: In manufacturing a device using an organic TFT, it is essential to develop an element in which a channel length is short or a channel width is narrow to downsize a device. Based on the above, it is an object of the present invention to provide an organic TFT in which characteristic is improved. In view of the foregoing problem, one feature of the present invention is that an element is baked after an organic semiconductor film is deposited. More specifically, one feature of the present invention is that the organic semiconductor film is heated under atmospheric pressure or under reduced pressure. Moreover, a baking process may be carried out in an inert gas atmosphere.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: July 12, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiharu Hirakata, Tetsuji Ishitani, Shuji Fukai, Ryota Imahayashi
  • Patent number: 7973352
    Abstract: Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: July 5, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-hyoung Choi, Jung-hee Chung, Cha-young Yoo, Young-sun Kim, Se-hoon Oh
  • Patent number: 7955869
    Abstract: Nonvolatile memory devices and methods of fabricating the same are provided. In some embodiments, a nonvolatile memory device includes a lower conductive member formed on an upper part of or inside a substrate, a ferroelectric organic layer formed on the lower conductive member, a protective layer formed on the ferroelectric organic layer, and an upper conductive member formed on the protective layer to cross the lower conductive member.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: June 7, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yasue Takahiro, Byeong-Ok Cho, Moon-Sook Lee
  • Patent number: 7955926
    Abstract: In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region; forming a high-k gate dielectric on the substrate including the at least one semiconducting region, wherein oxygen barrier material separates the high-k gate dielectric from the at least one oxygen source material; and forming a gate conductor atop the high-k gate dielectric.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: June 7, 2011
    Assignee: International Business Machines Corporation
    Inventors: Wesley C. Natzle, Renee T. Mo, Rashmi Jha, Kathryn T. Schonenberg, Richard A. Conti
  • Patent number: 7939353
    Abstract: A method of forming an integrated circuit includes forming a fluorine-passivated surface of a substrate. A device quality silicon oxide layer is formed by causing the fluorine-passivated surface to interact with an oxygen-containing gas. Hydroxyl groups are substantially formed on a surface of the device quality silicon oxide layer. A high dielectric constant (high-k) gate dielectric layer is formed on the surface of the device quality silicon oxide layer.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: May 10, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jeff J. Xu
  • Patent number: 7939872
    Abstract: A multi-dielectric film including at least one first dielectric film that is a composite film made of zirconium-hafnium-oxide and at least one second dielectric film that is a metal oxide film made of amorphous metal oxide. Adjacent ones of the dielectric films are made of different materials.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: May 10, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Cheol Lee, Sang-Yeol Kang, Ki-Vin Lim, Hoon-Sang Choi, Eun-Ae Chung
  • Patent number: 7935996
    Abstract: In a BST thin film being a capacitor film in a capacitor element, the capacitor film is formed such that two kinds of chemical states of Sr(I) and Sr(II) exist at a portion of which depth is up to 2.5 nm from a surface thereof (surface layer portion of which thickness is 2.5 nm), an average concentration of Sr(I) is set as AC(I), an average concentration of Sr(II) is set as AC(II), and when “R=AC(II)/AC(I)”, a value of “R” is adjusted to be “0” (zero)<R?0.3, more preferably, “0” (zero)<R?0.1.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: May 3, 2011
    Assignee: Fujitsu Limited
    Inventors: John D. Baniecki, Kazuaki Kurihara, Masatoshi Ishii
  • Patent number: 7932166
    Abstract: By forming a highly non-conformal stressed overlayer, such as a contact etch stop layer, the efficiency of the stress transfer into the respective channel region of a field effect transistor may be significantly increased. For instance, non-conformal PECVD techniques may be used for forming highly stressed silicon nitride in a non-conformal manner, thereby achieving higher transistor performance for otherwise identical stress conditions.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: April 26, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kai Frohberg, Frank Feustel, Thomas Werner
  • Patent number: 7932167
    Abstract: A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: April 26, 2011
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, John G. Gaudiello, Mark Charles Hakey, Steven J. Holmes, David V. Horak, Charles William Koburger, III, Chung Hon Lam
  • Patent number: 7927890
    Abstract: A method of manufacturing a semiconductor device including forming a lower electrode over a substrate, increasing the temperature of the substrate with the lower electrode to a predetermined temperature under mixture gas atmosphere of inert gas and oxygen gas, forming a dielectric film on the lower electrode by using an organic metal raw material after the temperature reaches the predetermined temperature, and forming an upper electrode on the dielectric film.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: April 19, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Wensheng Wang
  • Patent number: 7927990
    Abstract: A method is provided to form densely spaced metal lines. A first set of metal lines is formed by etching a first metal layer. A thin dielectric layer is conformally deposited on the first metal lines. A second metal is deposited on the thin dielectric layer, filling gaps between the first metal lines. The second metal layer is planarized to form second metal lines interposed between the first metal lines, coexposing the thin dielectric layer and the second metal layer at a substantially planar surface. In some embodiments, planarization continues to remove the thin dielectric covering tops of the first metal lines, coexposing the first metal lines and the second metal lines, separated by the thin dielectric layer, at a substantially planar surface.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: April 19, 2011
    Assignee: SanDisk Corporation
    Inventors: Kang-Jay Hsia, Calvin K Li, Christopher J Petti
  • Patent number: 7923323
    Abstract: Disclosed is a metal capacitor including a lower electrode having hemispherical metal grains thereon. The metal capacitor includes a lower metal electrode containing Ti, hemispherical metal grains containing Pd and formed on the lower metal electrode containing Ti, a dielectric layer formed on the lower metal electrode containing Ti and the hemispherical metal grains containing Pd, and an upper metal electrode formed on the dielectric layer.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: April 12, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Woo Hong, Chang-Huhn Lee, Jae-Hun Kim
  • Patent number: 7923324
    Abstract: A method for manufacturing a capacitor of a semiconductor device includes forming a lower metal layer over a substrate, forming a dielectric layer over the lower metal layer, forming an upper metal layer over the dielectric layer, forming an upper electrode and a dielectric layer pattern by performing a reactive ion etching process with respect to the upper metal layer using the dielectric layer as an etch stop layer, and exposing a top surface of the lower metal layer, and performing a chemical down-stream etch (CDE) process to remove a by-product of a sidewall of the upper electrode.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: April 12, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Taek-Seung Yang
  • Patent number: 7910428
    Abstract: A capacitor includes a pillar-type storage node, a supporter filling an inner empty crevice of the storage node, a dielectric layer over the storage node, and a plate node over the dielectric layer.
    Type: Grant
    Filed: June 29, 2008
    Date of Patent: March 22, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kee-Jeung Lee, Han-Sang Song, Deok-Sin Kil, Young-Dae Kim, Jin-Hyock Kim, Kwan-Woo Do, Kyung-Woong Park
  • Patent number: 7902632
    Abstract: A pumping MOS capacitor includes a substrate which is conductive and includes an irregular surface, a dielectric film formed along the irregular surface of the substrate and a gate formed on the dielectric film.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: March 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jun-Ki Choi
  • Patent number: 7897415
    Abstract: Provided are a ferroelectric recording medium and a method of manufacturing the same. The ferroelectric recording medium includes a substrate, a plurality of supporting layers which are formed on the substrate, each of the supporting layers having at least two lateral surfaces; and data recording layers formed on the lateral surfaces of the supporting layers. First and second data recording layers may be respectively disposed on two facing lateral surfaces of each of the supporting layers. The supporting layers may be polygonal pillars having at least three lateral surfaces. A plurality of the supporting layers can be disposed at uniform intervals in a two-dimensional array.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: March 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Simon Buehlmann, Seung-bum Hong
  • Patent number: 7892917
    Abstract: A bismuth titanium silicon oxide having a pyrochlore phase, a thin film formed of the bismuth titanium silicon oxide, a method for forming the bismuth-titanium-silicon oxide thin film, a capacitor and a transistor for a semiconductor device including the bismuth-titanium-silicon oxide thin film, and an electronic device employing the capacitor and/or the transistor are provided. The bismuth titanium silicon oxide has good dielectric properties and is thermally and chemically stable. The bismuth-titanium-silicon oxide thin film can be effectively used as a dielectric film of a capacitor or as a gate dielectric film of a transistor in a semiconductor device. Various electronic devices having good electrical properties can be manufactured using the capacitor and/or the transistor having the bismuth-titanium-silicon oxide film.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: February 22, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jin Cho, Yo-sep Min, Young-soo Park, Jung-hyun Lee, June-key Lee, Yong-kyun Lee
  • Patent number: 7888231
    Abstract: A capacitor and a method of fabricating the capacitor are provided herein. The capacitor can be formed by forming two or more dielectric layers and a lower electrode, wherein at least one of the two or more dielectric layers is formed before the lower electrode is formed.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: February 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-hyun Lee, Sung-ho Park, Sang-jun Choi
  • Patent number: 7888726
    Abstract: A capacitor for a semiconductor device having a dielectric film between an upper electrode and a lower electrode is featured in that the dielectric film includes an alternately laminated film of hafnium oxide and titanium oxide at an atomic layer level.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: February 15, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Toshiyuki Hirota, Masami Tanioku
  • Patent number: 7883906
    Abstract: The use of a conductive bidimensional perovskite as an interface between a silicon, metal, or amorphous oxide substrate and an insulating perovskite deposited by epitaxy, as well as an integrated circuit and its manufacturing process comprising a layer of an insulating perovskite deposited by epitaxy to form the dielectric of capacitive elements having at least an electrode formed of a conductive bidimensional perovskite forming an interface between said dielectric and an underlying silicon, metal, or amorphous oxide substrate.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: February 8, 2011
    Assignees: STMicroelectronics S.A., Universite Francois Rabelais
    Inventors: Ludovic Goux, Monique Gervais
  • Patent number: 7883961
    Abstract: A manufacturing method for a ferroelectric memory device including: forming a lower electrode; forming an electrode oxide film composed of an oxide of a constituent material of the lower electrode; forming a first ferroelectric layer on the lower electrode by reaction between organometallic source material gas and oxygen gas; forming a second ferroelectric layer on the first ferroelectric layer by reaction between organometallic source material gas and oxygen gas; and forming an upper electrode on the second ferroelectric layer. In the method, the oxygen gas in the forming of the first ferroelectric layer is in an amount less than the amount of oxygen necessary for reaction of the organometallic source material gas. In the method, the oxygen gas in the forming of the second ferroelectric layer is in an amount greater than the amount of oxygen necessary for reaction of the organometallic source material gas.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: February 8, 2011
    Assignees: Seiko Epson Corporation, Fujitsu Semiconductor Limited
    Inventors: Hiroaki Tamura, Masaki Kurasawa, Hideki Yamawaki
  • Patent number: 7879739
    Abstract: Embodiments of the invention provide a method to form a high-k dielectric layer on a group III-V substrate with substantially no oxide of the group III-V substrate between the substrate and high-k dielectric layer. Oxide may be removed from the substrate. An organometallic compound may form a capping layer on the substrate from which the oxide was removed. The high-k dielectric layer may then be formed, resulting in a thin transition layer between the substrate and high-k dielectric layer and substantially no oxide of the group III-V substrate between the substrate and high-k dielectric layer.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: February 1, 2011
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, James Blackwell, Suman Datta, Jack T. Kavalieros, Mantu K. Hudait
  • Patent number: 7881092
    Abstract: An integrated circuit including a resistive memory element and a method of manufacturing the integrated circuit are described. The method of manufacturing the integrated circuit includes depositing a switching layer material and intentionally forming inhomogeneously distributed defects within the switching layer material to increase a number of switching cycles of the resistive memory element. The resistive memory element includes a switching layer that selectively switches between a low resistance state and a high resistance state. The switching layer contains intentionally formed defects that increase the number of switching cycles of the switching layer.
    Type: Grant
    Filed: July 24, 2007
    Date of Patent: February 1, 2011
    Assignee: Rising Silicon, Inc.
    Inventor: Klaus Ufert
  • Patent number: 7879626
    Abstract: A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: February 1, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetsuya Ohnishi, Naoyuki Shinmura, Shinobu Yamazaki, Takahiro Shibuya, Takashi Nakano, Masayuki Tajiri, Shigeo Ohnishi
  • Patent number: 7880241
    Abstract: A gate electrode structure is provided, which includes, from bottom to top, an optional, yet preferred metallic layer, a Ge rich-containing layer and a Si rich-containing layer. The sidewalls of the Ge rich-containing layer include a surface passivation layer. The inventive gate electrode structure serves as a low-temperature electrically activated gate electrode of a MOSFET in which the materials thereof as well as the method of fabricating the same are compatible with existing MOSFET fabrication techniques. The inventive gate electrode structure is electrically activated at low processing temperatures (on the order of less than 750° C.). Additionally, the inventive gate electrode structure also minimizes gate-depletion effects, does not contaminate a standard MOS fabrication facility and has sufficiently low reactivity of the exposed surfaces that renders such a gate electrode structure compatible with conventional MOSFET processing steps.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: February 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: John C. Arnold, Stephen W. Bedell, Keith E. Fogel, Devendra K. Sadana
  • Patent number: 7867788
    Abstract: A Spin-Dependent Tunnelling cell comprises a first barrier layer of a first material and a second barrier layer of a second material sandwiched between a first ferromagnetic layer and a second ferromagnetic layer. The first and second barrier layers are formed to a combined thicknesses so that a Tunnelling Magnetoresistance versus voltage characteristic of the cell has a maximum at a non-zero bias voltage.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: January 11, 2011
    Assignees: Freescale Semiconductor, Inc., Centre National de la Recherché Scientifique (CNRS), STMicroelectronics (Crolles 2) SAS
    Inventors: De Come Buttet, Michel Hehn, Stephane Zoll
  • Patent number: 7863060
    Abstract: A method for forming a MTJ in a STT-MRAM is disclosed in which the easy-axis CD is determined independently of the hard-axis CD. One approach involves two photolithography steps each followed by two plasma etch steps to form a post in a hard mask which is transferred through a MTJ stack of layers. The hard mask has an upper Ta layer with a thickness of 300 to 400 Angstroms and a lower NiCr layer less than 50 Angstroms thick. The upper Ta layer is etched with a fluorocarbon etch while lower NiCr layer and underlying MTJ layers are etched with a CH3OH. Preferably, a photoresist mask layer is removed by oxygen plasma between the fluorocarbon and CH3OH plasma etches. A lower hard mask layer made of NiCr or the like is inserted to prevent formation and buildup of Ta etch residues that can cause device shunting.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: January 4, 2011
    Assignee: MagIC Technologies, Inc.
    Inventors: Rodolfo Belen, Tom Zhong, Witold Kula, Chyu-Jiuh Torng
  • Patent number: 7855114
    Abstract: A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of dielectric material formed upon the second oxide layer, the dielectric material having a second dielectric constant that is greater than the first dielectric constant, and a gate electrode formed upon the layer of dielectric material.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: December 21, 2010
    Assignee: Spansion LLC
    Inventors: Wei Zheng, Mark Randolph, Hidehiko Shiraiwa
  • Patent number: 7846795
    Abstract: A bit line of a semiconductor device includes a first interlayer dielectric film disposed on a semiconductor substrate, a plurality of bit line stacks disposed on the first interlayer dielectric film, a plurality of bit line spacers disposed on side walls of the bit line stacks, and a buffer film disposed on the bit line spacers, the first interlayer dielectric film and the bit line stacks; and a method for fabricating the same.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: December 7, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jie Won Chung
  • Patent number: 7829476
    Abstract: A method of manufacturing a semiconductor device has forming a capacitor having electrodes and a ferroelectric film provided therebetween above a substrate, forming a pad electrode electrically connected to one of the electrodes of the capacitor above the substrate, forming a protective film covering the pad electrode over the substrate, forming an opening in the protective film exposing at least a part of the pad electrode, bringing a measurement terminal into contact with the exposed surface of the pad electrode, etching the surface of the pad electrode after the measurement terminal is brought into contact therewith, and forming a hydrogen absorbing film on the protective film and the pad electrode exposed through the opening.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: November 9, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kouichi Nagai, Kaoru Saigoh