Abstract: A full phase shifting mask (FPSM) can define substantially all of the features of an integrated circuit using pairs of shifters having opposite phase. In particular, cutting patterns for working with the polysilicon, or gate, layers and active layers of static random access memory (SRAM) cells are considered. To resolve phase conflicts between shifters, one or more cutting patterns can be selected. These cutting patterns include cuts on contact landing pads. This cut simplifies the FPSM layout while ensuring greater critical dimension control of the more important features and reducing mask misalignment sensitivity.

Abstract: Disclosed is a method of manufacturing semiconductor devices, which can improve electrical characteristics of semiconductor devices.

Abstract: The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass comprises silicon and the second mass comprises silicon oxide. A sacrificial layer is formed over the first mass. While the sacrificial layer is over the first mass, a nitrogen-containing material is formed across the second mass. After the nitrogen-containing material is formed, the sacrificial layer is removed. Subsequently, a silicon nitride layer is formed to extend across the first and second masses, with the silicon nitride layer being over the nitrogen-containing material. Also, a conductivity-enhancing dopant is provided within the first mass. The invention also pertains to methods of forming capacitor constructions.

Abstract: The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second semiconductor structure comprising a second monocrystalline semiconductor substrate. The first semiconductor substrate has a semiconductive material projection extending therefrom, and the second semiconductor substrate has an electrically conductive interconnect extending therethrough. The interconnect electrically connects with the semiconductive material projection, and comprises a different dopant type than the semiconductor material projection. The invention also includes a method of bonding a first monocrystalline semiconductor substrate construction to a second monocrystalline semiconductor substrate construction, wherein the first construction is doped to a first dopant type, and the second construction is doped to a second dopant type different from the first dopant type.

Abstract: The invention includes a method of forming an array of memory cells. A series of capacitor constructions is formed, with the individual capacitor constructions having storage nodes. The capacitor constructions are defined to include a first set of capacitor constructions and a second set of capacitor constructions. A series of electrically conductive transistor gates are formed over the capacitor constructions and in electrical connection with the capacitor constructions. The transistor gates are defined to include a first set that is in electrical connection with the storage nodes of the first set of capacitor constructions, and a second set that is in electrical connection with the storage nodes of the second set of capacitor constructions. A first conductive line is formed over the transistor gates and in electrical connection with the first set of transistor gates, and a second conductive line is formed over the first conductive line and in electrical connection with the second set of transistor gates.

Abstract: To fabricate an integrated semiconductor product with integrated metal-insulator-metal capacitor, first of all a dielectric protective layer (5) and a dielectric auxiliary layer (16) are deposited on a first electrode (2). The protective layer and the auxiliary layer (16) are then opened up (17) via the first electrode. Then, a dielectric layer (6) is produced, and the metal track stack (7, 8, 9) for the second electrode is then applied to the dielectric layer (6). This is followed by the patterning of the metal-insulator-metal capacitor using known etching processes. This makes it possible to produce dielectric capacitor layers of any desired thickness using materials which can be selected as desired. In particular, this has the advantage that via etches can be carried out significantly more easily than in the prior art, since it is not necessary to etch through the residual dielectric capacitor layer above the metal tracks.

Abstract: A method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution controls the defined pitches of the target layer by use of polymer spacer, photo-insensitive polymer plug and polymer mask during the process, so as to achieve the minimum pitch of the target layer beyond photolithographic resolution. Applied to memory manufacture, this method is capable of simultaneously overcoming the process difficulty of significant difference between polysilicon pitches in memory array region and periphery region.

Abstract: A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.

Abstract: Disclosed is a method for depositing a silicon nitride layer of a semiconductor device. The method includes the steps of providing Al-based compound as a catalyst, and reacting DCS with NH3 by using the Al catalyst, thereby depositing the silicon nitride layer. DCS is reacted with NH3 by using the Al catalyst when depositing the silicon nitride layer, so dissolution of DCS is promoted by means of the Al catalyst, so that the silicon nitride layer is deposited at a high speed, thereby improving productivity of semiconductor devices. The silicon nitride layer is deposited by using DCS under a low-temperature condition of about 500 to 800° C., without deteriorating device characteristics.

Abstract: A method and apparatus for forming shallow and deep isolation trenches in a substrate so that the shallow and deep isolation trenches are aligned without mis-registration. The method includes forming a plurality of shallow trenches, covering a portion of the plurality of shallow trenches, then etching the uncovered shallow trenches to create deeper trenches.

Abstract: A method of fabricating an X-ray detector array element. A gate and a gate insulation layer are formed on a substrate. A silicon island is formed on the insulation layer in a transistor area. A common line is formed on the insulation layer, simultaneously; source and drain are formed on the island to form a TFT. A bottom electrode is formed on the insulation layer in a capacitor area and covers the common line. A passivation layer is formed on the insulation layer, the bottom electrode and the TFT. A first via hole penetrates the passivation layer to expose the source. A planarization layer is formed on the passivation layer and fills the first via hole. Second and third via holes penetrate the planarization layer. The second via hole exposes the source. The third via hole exposes part of the passivation layer. A top electrode is formed on the planarization layer and connects the source.

Abstract: An improved magnetic memory element is provided in which a magnetic sense layer is formed of two ferromagnetic material layers separated by a spacer layer. The two ferromagnetic layers are formed as a synthetic ferrimagnet with stray field coupling and antiferromagnetic exchange coupling across the spacer layer.

Abstract: A manufacturing method of an integrated chip. The integrated chip includes at least two devices with different functions. The method uses a first production line to form a first device on a semiconductor wafer and then uses a second production line to form a second device on the semiconductor wafer so as to complete the integrated chip.

Abstract: A method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line forming trench, and memory array storage node vias within a dielectric mass using only two masking steps. Conductive material is simultaneously deposited to within the buried bit line forming trench, the bit line vias, and the memory storage node vias within the dielectric mass. Other aspects and implementations are contemplated.

Abstract: A semiconductor memory cell includes a semiconductor substrate that defines a trench having trench walls. The semiconductor memory cell also includes a floating gate electrode positioned within the trench and insulated from the trench walls by a first insulation region; a control gate electrode surrounding the trench; and a second insulation layer on the surface of the semiconductor substrate. The semiconductor memory cell further includes a conductive layer positioned on the second insulation layer. The conductive layer includes a channel region positioned above the floating gate electrode. The semiconductor memory cell also includes a source region and a drain region. The source region and the drain region are each formed in the conductive layer. The source region and the drain region are also connected to the channel region.

Abstract: A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating fi

Abstract: An alignment aid for semiconductor devices. The alignment aid includes an area having a high level of reflectivity and an adjacent area having a of low level of reflectivity. The area having a low level of reflectivity includes at least one layer of tiles located in an interconnect layer of a semiconductor device and located over active circuitry of the semiconductor device. In some examples, the spacings between the tiles in a scan direction of the alignment aid is less than the wavelength of a light (e.g. a laser light) used to scan the alignment aid. In other examples, the width of the tiles in a scan direction of the alignment aid is less than the wave length of a laser used to scan the alignment aid.

Abstract: According to the present invention, there is provided a semiconductor memory having a memory cell array region and peripheral circuit region, comprising, a gate electrode formed on a semiconductor substrate via a first insulating film in each of said memory cell array region and peripheral circuit region, and including a conductive layer which at least partially includes a silicon layer, and a second insulating film, a first oxide film formed on side surfaces of said conductive layer included in said gate electrode and on said semiconductor substrate in said memory cell array region, a second oxide film formed on side surfaces of said conductive layer included in said gate electrode and on said semiconductor substrate in said peripheral circuit region, and having a film thickness smaller than that of said first oxide film, a first nitride film formed on side surfaces of said gate electrode in said memory cell array region, and a second nitride film formed on side surfaces of said gate electrode in said periph

Abstract: A semiconductor memory device includes first and second semiconductor layers, a buried insulating layer, a trench comprising a retreated portion, and the trench defining a first opening width at the second semiconductor layer, a first capacitor electrode formed in the first semiconductor layer, a capacitor insulating film formed in the trench, a second capacitor electrode formed in the trench in the first semiconductor layer, an insulating film formed on a side surface of the retreated portion and defining second and third opening widths, the second opening width serving as a width at the buried insulating layer and being not more than the first opening width, and the third opening width serving as a width at a boundary portion between the buried insulating layer and first semiconductor layer, and a connection portion electrically connected to the second capacitor electrode.

Abstract: This invention relates to a method and resulting structure, wherein a DRAM may be fabricated by using silicon midgap materials for transistor gate electrodes, thereby improving refresh characteristics of access transistors. The threshold voltage may be set with reduced substrate doping requirements. Current leakage is improved by this process as well.

Abstract: A floating gate transistor is formed by simultaneously creating buried contact openings on both EEPROM transistor gates and DRAM access transistor source/drain diffusions. Conventional DRAM process steps are used to form cell storage capacitors in all the buried contact openings, including buried contact openings on EEPROM transistor gates. An EEPROM transistor gate and its associated cell storage capacitor bottom plate together forms a floating gate completely surrounded by insulating material. The top cell storage capacitor plate on an EEPROM transistor is used as a control gate to apply programming voltages to the EEPROM transistor. Reading, writing, and erasing the EEPROM element are analogous to conventional floating-gate tunneling oxide (FLOTOX) EEPROM devices. In this way, existing DRAM process steps are used to implement an EEPROM floating gate transistor nonvolatile memory element.

Abstract: A technique is provided which makes it possible to achieve both of a reduction in contact resistance in a memory device and a reduction in contact resistance in a logic device even when oxidation is performed during formation of dielectric films of capacitors. Conductive barrier layers (82) are provided in the top ends of contact plugs (83b) electrically connected to ones of source/drain regions (59). Lower electrodes (70) of capacitors (73) are formed in contact with the conductive barrier layers (82) of the contact plugs (83b) and then dielectric films (71) and upper electrodes (72) of the capacitors (73) are sequentially formed. In the logic region, contact plugs (25) are formed in an upper layer so that they are in contact respectively with contact plugs (33) electrically connected to source/drain regions (9).

Abstract: A method for fabricating features on a substrate having reduced dimensions. The features are formed by defining a first mask on regions of the substrate. The first mask is defined using lithographic techniques. A second mask is then conformably formed on one or more sidewalls of the first mask. The features are formed on the substrate by removing the first mask and then etching the substrate using the second mask as an etch mask.

Abstract: An EPROM structure includes a NMOS transistor integrated with a capacitor. The terminal names of the NMOS transistor follow the conventional nomenclature: drain, source, body and gate. The gate of the NMOS transistor is connected directly and exclusively to one of the capacitor plates. In this configuration, the gate is now referred to as the “floating gate”. The remaining side of the capacitor is referred to as the “control gate”.

Abstract: A gate process and a gate process for an embedded memory device. A semiconductor silicon substrate has a memory cell area and a logic circuit area. A first dielectric layer is formed overlying the semiconductor silicon substrate, and then a gate structure is formed overlying the first dielectric layer of the memory cell area. Next, a protective layer is formed overlying the first dielectric layer and the top and sidewall of the gate structure. Next, an insulating spacer is formed overlying the protective layer disposed overlying the sidewall of the gate structure. Next, a pre-cleaning process is performed to remove the protective layer and the first dielectric layer overlying the logic circuit area. Next, a second dielectric layer is formed overlying the logic circuit area, and then a gate layer is formed overlying the second dielectric layer of the logic circuit area.

Abstract: Disclosed is a method for fabricating a silicide layer of a flat cell memory device.

Abstract: A method and structure for a memory storage cell in a semiconductor substrate includes forming a dopant source material over a lower portion of a deep trench formed in the substrate. An upper portion of the trench is shaped to a generally rectangular configuration, and the dopant source material is annealed so as to form a buried plate of a trench capacitor. The buried plate is self aligned to the shaped upper portion of the trench.

Abstract: A method of preventing decreasing threshold voltage of a MOS transistor by formation of shallow trench isolation. Shallow trenches are formed to isolate first active regions and second active regions. The first active regions are located within a core circuit region, while the second active regions are located within a peripheral circuit region. A first ion implantation to form well regions is performed on the first and second active regions, respectively. A second ion implantation is performed on the second active region and edges of the first active regions to form second channel doping regions and to increase ion concentration at the edges of the first active regions, respectively. A third ion implantation is further performed on the first active regions to form first channel doping regions.

Abstract: The method of the present invention comprises the steps of: (a) laying on a prior layer, a first oxide layer doped in one form; (b) laying on said first oxide layer, a second oxide layer doped in a different form; (c) patterning said layers; (d) etching the second layer with an etchant having high selectivity to said second doped oxide layer; and (e) etching the first layer with an etchant having high selectivity to said first doped oxide layer. As the etch rate is higher for the highly doped oxide than that for the lightly doped oxide, high selectivity of etching between such layers can therefore be attained. A lightly doped silicon oxide layer may therefore be used to stop etching at an optimal thickness over the complicated layer of substrate. The lightly doped silicon oxide area may be covered with a layer of highly doped silicon oxide layer which may be etched with a specific etchant.

Abstract: The present invention provides a hydrogen barrier layer able to prevent diffusions of hydrogen into a capacitor and a method for fabricating a semiconductor device having the same. The inventive method includes the steps of: forming a capacitor on an upper portion of a substrate providing a transistor; forming a first hydrogen barrier layer covering the capacitor, the first hydrogen barrier layer containing Al and Ti; forming a metal line connecting the capacitor to the transistor; forming a second hydrogen barrier layer containing Al and Ti on the metal line; and forming a protection layer on the second hydrogen barrier layer.

Abstract: A memory is described having a semiconductor substrate of a first conductivity type, a first and a second junction region of a second conductivity type, whereby said first and said second junction region are part of respectively a first and a second bitline. A select gate is provided which is part of a wordline running perpendicular to said first and said second bitline. Read, write and erase functions for each cell make use of only two polysilicon layers which simplifies manufacture and each memory cell has at least two locations for storing a charge representing at least one bit.

Abstract: A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell array formed on the semiconductor substrate, and including a first gate insulator having a first thickness. The device further includes a high-voltage transistor circuit formed on the semiconductor substrate, and including a second gate insulator having a second thickness greater than the first thickness, and a peripheral circuit formed on the semiconductor substrate, and including the second gate insulator.

Abstract: A method for making a semiconductor device is described. In that method, a metal layer is formed on a dielectric layer, which is formed on a substrate. After forming a masking layer on the metal layer, the sides of the masking layer are lined with a sacrificial layer.

Abstract: A method for manufacturing a semiconductor device wherein a cylindrical capacitor is formed by selectively etching an oxide film in a cell area for preventing bridging between cells during a wet etching process of the oxide film in the cell area is described herein. A step difference between the interlayer insulating film formed in the cell area and the interlayer insulating film formed in the peripheral circuit area is minimized by covering the peripheral circuit area by the photoresist film and selectively etching the oxide film in the cell area to form a cylindrical capacitor, thereby simplifying the manufacturing process. In addition, bridging between the cells is prevented by performing a simple wet etching process using a single wet station, without performing a separate dry etching process for removing the oxide film and the photoresist film pattern, thereby improving the yield of the device.

Abstract: A semiconductor device includes a nitride film between a gate electrode and an ohmic electrode contacting to a diffusion region adjacent to the gate electrode, at least on a side of the gate electrode facing the ohmic electrode.

Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

Abstract: A new processing sequence is provided for the creation of a metal gate electrode. At least two polysilicon gate electrodes are provided over the surface of a substrate, these polysilicon gate electrodes having a relatively thick layer of gate dielectric making these polysilicon gate electrodes suitable for high-voltage applications. The two polysilicon gate electrodes are divided into a first and a second gate electrode, both gate electrodes are imbedded in a layer of Intra Metal Dielectric (IMD). The first gate electrode is removed by applying a lift-off process to this first gate electrode, creating an opening in the layer of IMD. The second gate structure is shielded by a photoresist mask during the removal of the first gate electrode. A metal gate electrode is created in the opening created in the layer of IMD, using a thin layer of gate dielectric.

Abstract: An integrated circuit includes memory cells having array transistors separated by minimum lithographic feature and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without compromise of performance including an effective channel, silicided contacts for low source/drain contact resistance, extension and halo implants for control of short channel effects and a dual work function semiconductor gate having a high impurity concentration and correspondingly thin depletion layer thickness commensurate with state of the art gate dielectric thickness. This structure is achieved by development of thick/tall structures of differing materials using a mask or anti-spacer, preferably of an easily planarized material, and using a similar mask planarized to the height of the structures of differing materials to decouple substrate and gate implantations in the logic transistors.

Abstract: A method for manufacturing a semiconductor memory device having a memory region and a peripheral region, including forming a memory cell on the memory region and a peripheral transistor on the peripheral region, the memory cell having a first gate electrode and a first diffusion layer, the peripheral transistor having a second gate electrode and a second diffusion layer; forming a silicon nitride layer above an upper surface and a side surface of the first gate electrode of the memory cell and above an upper surface and a side surface of the second gate electrode of the peripheral transistor; removing the silicon nitride layer that is formed above the upper surface of the second gate electrode of the peripheral transistor; forming an interlayer insulating film above the memory cell and the peripheral transistor; forming a first contact hole that reaches the upper surface of the second gate electrode of the peripheral transistor by removing a portion of the interlayer insulating film; and forming a conductive

Abstract: The present invention discloses a semiconductor memory device having a bit line and a metal contact stud, wherein the metal contact stud is formed on a different layer from a layer on which the bit lines are formed.

Abstract: An image sensor includes a plurality of unit pixels for sensing a light beam to generate an image data. Each of the unit pixels includes, a photoelectric element for sensing a light beam incident thereto and generating photoelectric charges, a transistor including a gate dielectric formed adjacent to the photoelectric element and a gate electrode formed on top of the gate dielectric and a capacitor structure including an insulating film formed on a portion of the photoelectric element and a bottom electrode, wherein the insulating film and the gate dielectric are made of a same material and the bottom electrode and the gate electrode are made of a same material.

Abstract: A CMOS imager having an improved signal to noise ratio and improved dynamic range is disclosed. The CMOS imager provides improved charge storage by fabricating a storage capacitor in parallel with the photocollection area of the imager. The storage capacitor may be a flat plate capacitor formed over the pixel, a stacked capacitor or a trench imager formed in the photosensor. The CMOS imager thus exhibits a better signal-to-noise ratio and improved dynamic range. Also disclosed are processes for forming the CMOS imager.

Abstract: A method to fabricate a 1T-RAM device, comprising the following steps. A semiconductor substrate having an access transistor area and an exposed bottom plate within a capacitor area proximate the access transistor area is provided. A gate with an underlying gate dielectric layer within the access transistor area are formed. The gate and underlying gate dielectric layer having sidewall spacers formed over their respective exposed side walls. A top plate with an underlying capacitor layer over the bottom plate within the capacitor area are formed. The top plate and underlying capacitor layer having sidewall spacers formed over their respective exposed side walls. A patterned resist protect oxide (RPO) layer is formed over at least the drain of the structure not to be silicided. Metal silicide portions are formed over the structure not protected by the RPO layer.

Abstract: A method for integrating copper with an MIM capacitor during the formation the MIM capacitor. The MIM capacitor is generally formed upon a substrate and at least one copper layer is deposited upon the substrate and layers thereof to form at least one metal layer from which the MIM capacitor is formed, such that the MIM capacitor may be adapted for use with an embedded DRAM device. The MIM capacitor comprises a low-temperature MIM capacitor. At least one DRAM crown photo layer may be formed upon the substrate and layers thereof to form the MIM capacitor. The number of additional lithographic steps required in BEOL manufacturing operations is thus only one, while the capacitance of the MIM capacitor can be improved greatly because the sequential process of the DRAM crown photo patterning steps may be altered.

Abstract: A method of fabricating an integrated circuit device having capacitors is provided. The capacitors can include a first electrode, a dielectric layer and a second electrode. An interlayer insulating layer is formed on the capacitor. The interlayer insulating layer is patterned to form a metal contact hole that exposes a region of the second electrode. The exposed region of the second electrode is reduced to remove excessive oxygen atoms that can exist in the second electrode.

Abstract: A method for forming a storage node contact plug of a dynamic random access memory includes forming insulating layers on an overall surface of a semiconductor substrate having a plurality of buried contact plugs, etching the insulating layers down to a top surface of the buried contact plugs to form first contact holes on the buried contact plugs, forming a photoresist pattern on the insulating layers and the first contact holes, etching the insulating layers to form second contact holes on the second insulating layer, and filling the first and second contact holes with conductive material.

Abstract: A non-volatile memory device comprises an active region disposed in a predetermined region of a semiconductor substrate, a selection gate electrode crossing over the active region, and a floating gate electrode disposed on the active region parallel to the selection gate electrode and spaced apart from the selection gate electrode. The non-volatile memory device further comprises a tunnel insulating layer intervening between the active region and each of the selection gate electrode and the floating gate electrode, a separation insulating pattern intervening between the selection gate electrode and the floating gate electrode, an erasing gate electrode disposed over the floating gate electrode and crossing over the active region parallel to the selection gate electrode, and an erasing gate insulating layer intervening between the erasing gate electrode and the floating gate electrode. The selection gate electrode is formed without a photoresist pattern.

Abstract: A photoresist (6) is formed on an element isolation insulating film (2) so as to cover the upper and side surfaces of a polysilicon film (4R) which functions as a resistance element. With the photoresist (6) as an implantation mask, n-type impurities (7) such as phosphorus are ion-implanted from a direction substantially normal to the upper surface of a silicon substrate (1). The dose is in the order of 1013/cm2. Through this processing, an LDD region (8) of MOSFET is formed inside the upper surface of the silicon substrate (1) within a transistor forming region. The impurities (7) are also implanted in a polysilicon film (4G). On the other hand, as the polysilicon film (4R) is covered by the photoresist (6), the impurities (7) are not implanted into the polysilicon film (4R).

Abstract: A buried gate electrode of a buried MOS transistor formed within a trench in an active region wherein a gate oxide film and a gate electrode are buried in the trench, and a lower electrode of a PIP capacitor formed on a device isolation, are simultaneously formed by etching of polycrystalline silicon formed on an entire surface of the structure.

Abstract: Mutual diffusion of impurities in a gate electrode is suppressed near a boundary between an n-channel type MISFET and a p-channel type MISFET, which adopt a polycide's dual-gate structure. Since a gate electrode of an n-channel type MISFET and a gate electrode of a p-channel type MISFET are of mutually different conductivity types, they are separated to prevent the mutual diffusion of the impurities and are electrically connected to each other via a metallic wiring formed in the following steps. In a step before a gate electrode material is patterned to separate the gate electrodes, the mutual diffusion of the impurities before forming the gate electrodes is prevented by performing no heat treatment at a temperature of 700° C. or higher.