Abstract: A new method and structure is provided for the creation of a 1T-RAM cell. Shallow Trench Isolation (STI) regions are provided over a substrate. A 3D capacitor area is defined over the substrate, a patterned layer of polysilicon or HSG polysilicon is created aligned with the 3D capacitor area, providing the bottom plate of a 3D capacitor. Gate oxide is grown to form a dielectric for CMOS gate electrodes and the 3D capacitor dielectric. A patterned layer of polysilicon is created, defining gate electrodes and 3D capacitor upper plates.

Abstract: A method for forming a semiconductor device having a trench top isolation layer. A collar insulating layer is formed over a lower portion of the sidewall of the trench formed in a substrate. A first conductive layer is formed in the lower portion of the trench and protrudes the collar insulating layer, and a second conductive layer is formed overlying the first conductive layer and covers the collar insulating layer. An insulating spacer is formed over an upper portion of the sidewall of the trench and separated from the second conductive layer by a gap. The second conductive layer is partially thermally oxidized to form an oxide layer thereon whereby the gap is filled. After the oxide layer is removed, a reverse T-shaped insulating layer is formed thereon by chemical vapor deposition to serve as a trench top isolation layer. Finally, the insulating spacer is removed.

Abstract: A method for forming high-density self-aligned contacts and interconnect structures in a semiconductor device. A dielectric layer thick enough to contain both interconnect and contact structures is formed on a substrate. A patterned hardmask is formed on the dielectric layer to define both the interconnect and contact structures. The openings for interconnect features are first formed by partially etching the dielectric layer selective to the hardmask. A second mask (e.g., a resist) is used to define the contact openings, and the dielectric layer is etched through the second mask, also selective to the hardmask, to expose the diffusion regions to be contacted. The patterned hardmask is used to help define the contact openings. Conductive material is then deposited in the openings which results in contacts and interconnects that are self-aligned. By first forming the openings for both interconnect and contacts, savings in processing steps may be obtained.

Abstract: A unique cell structure for use in flash memory cell and a method of fabricating the memory cell. More particularly, a vertically integrated transistor having a pair of floating gates is fabricated within a trench in a substrate. The floating gates are fabricated using sidewall spacers within the trench. A doped region is buried at the bottom of the trench. The structure can be fabricated such that the buried doped region provides a connecting layer in a multi-bit flash memory cell. Alternatively, the buried doped region may be used as a buried bitline in a single bit flash memory cell.

Abstract: A trench capacitor DRAM cell in an SOI wafer uses the silicon device layer in the array as part of passing wordlines, stripping the silicon device layer in the array outside the wordlines and uses the BOX layer as the array top oxide separating the passing wordlines from the substrate.

Abstract: A pixel cell having two capacitors connected in series where each capacitor has a capacitance approximating that at of the periphery capacitors and such that the effective capacitance of the series capacitors is smaller than that of each of the periphery capacitors. The series-connected capacitors are coupled to the floating diffusion (FD) region for receiving “surplus” charge from the FD region during saturation conditions.

Abstract: A double diffused MOS (DMOS) transistor structure is provided that uses a trench trough suitable for high-density integration with mixed signal analog and digital circuit applications. The DMOS device can be added to any advanced CMOS process-using shallow trench isolation by adding additional process steps for trench trough formation, a trench implant and a P-body implant. The trench trough and trench implant provide a novel method of forming a drain extension for a high-voltage DMOS device.

Abstract: A semiconductor device having a capacitor of an MIM structure and a method of forming the same are described. The semiconductor device includes a semiconductor substrate; a first bottom interconnection formed over the semiconductor substrate; an intermetal dielectric layer formed over the semiconductor substrate; a plurality of openings exposing the first bottom interconnection through the intermetal dielectric layer; a bottom electrode conformally formed on the inside wall of the openings, on the exposed surface of the first bottom interconnection and on the intermetal dielectric layer between the openings; a dielectric layer and an upper electrode sequentially stacked on the bottom electrode; and a first upper interconnection disposed on the upper electrode. According to the present invention, an effective surface area per a unit planar area of a capacitor with an MIM structure is enlarged to increase capacitance thereof.

Abstract: A method of producing an integrated circuit having a vertical MOS transistor includes doping a substrate to form a layer adjacent to its surface and forming a lower doped layer serving as the transistor's first source/drain region. The transistor's channel region is formed by doping a central layer above the lower layer. A second source/drain region is formed by doping an upper layer above the central layer. The upper, central and lower layers form a layer sequence having opposed first and second faces. A connecting structure is formed on the first face to electrically connect the channel region and the substrate. The connecting structure laterally adjoins at least the central layer and the lower layer, and extends into the substrate. A gate dielectric and adjacent gate electrode are formed on the second face.

Abstract: A method and structure for an improved DRAM (dynamic random access memory) dielectric structure, whereby a new high-k material is implemented for both the support devices used as the gate dielectric as well as the capacitor dielectric. The method forms both deep isolated trench regions used for capacitor devices, and shallow isolated trench regions for support devices. The method also forms two different insulator layers, where one insulator layer with a uniform high-k dielectric constant is used for the deep trench regions and the support regions. The other insulator layer is used in the array regions in between the shallow trench regions.

Abstract: A method for forming substantially uniformly thick, thermally grown, silicon dioxide material on a silicon body independent of axis. A trench is formed in a surface of the silicon body, such trench having sidewalls disposed in different crystallographic planes, one of such planes being the <100> crystallographic plane and another one of such planes being the <110> plane. A substantially uniform layer of silicon nitride is formed on the sidewalls. The trench, with the substantially uniform layer of silicon nitride, is subjected to a silicon oxidation environment with sidewalls in the <110> plane being oxidized at a higher rate than sidewalls in the <100> plane producing silicon dioxide on the silicon nitride layer having thickness over the <110> plane greater than over the <100> plane.

Abstract: A memory module and a method for fabricating the memory module are described. The memory module has a memory cell that is disposed in a vertical trench. The memory cell has a first and a second transistor connected in series and the first transistor is able to be turned on via a first word line and the second transistor is able to be turned on via a charge of a capacitor. The two transistors are connected between a voltage source and a bit line. In this way, the charge state of the capacitor is evaluated by the second transistor. If the capacitor has a positive charge, then the second transistor is turned on. If, moreover, the first word line is driven, then the first transistor is also turned on. As a consequence, the bit line is connected to the voltage source and supplied with a sufficiently strong signal for evaluation.

Abstract: A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.

Abstract: A vertical transistor DRAM structure is disclosed by the present invention, in which a trench structure comprises a deep-trench region having a vertical transistor and a second-type shallow-trench-isolation region being formed in a side portion of the deep-trench region and a common-drain structure comprises different implant regions being formed under a common-drain diffusion region in another side portion of the deep-trench region. The vertical transistor DRAM structure is, used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated. with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common-drain conductive bit-lines.

Abstract: A semiconductor device and method of making the same is provided having enhanced isolation between the bit line contact and the gate region of the semiconductor device. A gate conductor spacer and a recess fill material provide the enchanced isolation. The recess fill material substantially fills a recess defined by the gate conductor spacer and has a different composition than the gate conductor spacer.

Abstract: A method for fabricating a semiconductor device comprising forming an insulating layer and a nitride layer sequentially on a semiconductor substrate; selectively removing the layers to form a first contact hole; forming a silicon layer in the first contact hole; forming a trench by selective removal of the silicon layer; forming a source region in the semiconductor substrate and a drain region on the trench; forming a gate oxide layer and gates sequentially at the side walls of the trench; forming a planarization layer on the resultant structure; forming a second contact hole that exposes the gate, the drain region, and the source region; and forming plugs in the exposed second contact hole.

Abstract: The distance between buried straps in a DRAM array of trench capacitor/vertical transistor cells is increased by offsetting adjacent cells by a vertical offset distance, so that the total distance between adjacent straps is increased without increasing the horizontal distance between cells.

Abstract: A semiconductor memory device having a trench capacitor, comprising: a semiconductor substrate of a fist conductivity type, having a trench which is formed from an upper surface of the semiconductor substrate to a predetermined depth; a capacitor formed in a lower portion of the trench and the semiconductor substrate of the fist conductivity type which is adjacent to the lower portion of the trench; a first conductive layer formed in the first trench and right above the first capacitor to which the first conductive layer is electrically connected; a first insulation film formed in the trench and right above the first conductive layer; a first diffusion layer formed in the semiconductor substrate of the fist conductivity type which is adjacent to the first conductive layer and the first insulation film, the first diffusion layer served as a source/drain electrode; a gate insulation film formed on a predetermined portion of the trench, the predetermined portion being located above the first insulation film; a s

Abstract: A dynamic random access memory cell comprising: a trench capacitor formed in a silicon substrate; a vertical MOSFET formed in a silicon substrate above the trench capacitor, the vertical MOSFET having a gate electrode, a first source/drain region extending from a surface of the silicon substrate into the silicon substrate, a buried second source/drain region electrically contacting the trench capacitor, a channel region formed in the silicon substrate between the first source/drain region and the buried second source/drain region and a gate oxide layer disposed between the gate electrode and the channel region; the first source/drain region also belonging to an adjacent vertical MOSFET, the adjacent vertical MOSFET having a buried third source/drain region electrically connected to an adjacent trench capacitor, the buried second and third source/drain regions extending toward one another; and a punch through prevention region disposed between the buried second and third source/drain regions.

Abstract: A double diffused MOS (DMOS) transistor structure is provided that uses a trench trough suitable for high-density integration with mixed signal analog and digital circuit applications. The DMOS device can be added to any advanced CMOS process using shallow trench isolation by adding additional process steps for trench trough formation, a trench implant and a P-body implant. The trench trough and trench implant provide a novel method of forming a drain extension for a high-voltage DMOS device.

Abstract: A semiconductor memory device includes a trench type SRAM(Static Random Access Memory) cell having a higher integration than a stack type SRAM. The SRAM cell memory device is provided with a trench formed in a semiconductor substrate and having four side walls therein, wherein a source and drain region of a drive transistor is formed in two of the four side walls, respectively, a pair of active layers respectively having a source and drain regions of a first load transistor is formed on the substrate adjacent to the side walls, and a gate electrode common to the load transistor is formed on a gate oxide film, whereby the gate electrode of the access transistor is vertically formed toward a direction vertical to the semiconductor substrate instead of being formed on the substrate for thereby decreasing an area to be occupied by transistor.

Abstract: A touch-sensitive semiconductor chip having a physical interface to the environment, where the surface of the physical interface is coated with a fluorocarbon polymer. The polymer is highly scratch resistant and has a characteristic low dielectric constant for providing a low attenuation to electric fields. The polymer can be used instead of conventional passivation layers, thereby allowing a thin, low dielectric constant layer between the object touching the physical interface, and the capacitive sensing circuits underlying the polymer.

Abstract: A method is provided for forming a vertical transistor memory cell structure with back-to-back FET cells which are formed in a planar semiconductor substrate with a plurality of deep trenches having vertical FET devices and a plurality of capacitors each located in a separate trench that is formed in the semiconductor substrate. Bilateral outdiffusion strap regions are formed extending into a doped semiconductor well region in the substrate. There are confronting pairs of outdiffusion strap regions extending from adjacent deep benches into the doped well region. An isolation diffusion region is formed in the doped well separating the confronting isolation diffusion regions by extending therebetween.

Abstract: A semiconductor device includes a substrate forming a trench, the trench including a storage node disposed within the trench. A wordline is disposed within the substrate and adjacent to a portion of the substrate. A vertically disposed transistor is included wherein the wordline functions as a gate, the storage node and a bitline function as one of a source and a drain such that when activated by the wordline the transistor conducts between the storage node and the bitline. The invention further includes a method of fabricating the semiconductor device with vertical transistors.

Abstract: A self-aligned vertical transistor DRAM structure comprising a self-aligned trench structure and a self-aligned common-drain structure are disclosed by the present invention, in which the self-aligned trench structure comprises a deep-trench capacitor region having a vertical transistor and a second-type shallow-trench-isolation region being defined by a spacer technique and the self-aligned common-drain structure comprises a common-drain region being defined by another spacer technique. The self-aligned vertical transistor DRAM structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common-drain conductive bit-lines.

Abstract: For particularly simple and targeted formations of a diffusion region, an interfacial region of a semiconductor substrate is subjected to a thermal transformation process and thereby carry out the thermally activated diffusion of a dopant in a substantially directed form, in particular in substantially a preferential direction, by interaction of a provided dopant with a transforming interfacial region.

Abstract: A capacitor having improved size for enhanced capacitance and a method of forming the same are disclosed. In one embodiment, the capacitor is a stacked container capacitor used in a dynamic random access memory circuit. The capacitor provides a capacitor that has high storage capacitance which provides an increased efficiency for a cell without an increase in the size of the cell.

Abstract: A memory cell structure for a folded bit line memory array of a dynamic random access memory device includes buried bit and word lines, with the access transistors being formed as a vertical structure on the bit lines. Isolation trenches extend orthogonally to the bit lines between the access transistors of adjacent memory cells, and a pair of word lines are located in each of the isolation trenches. The word lines are oriented vertically widthwise in the trench and are adapted to gate alternate access transistors, so that both an active and a passing word line can be contained within each memory cell to provide a folded bit line architecture. The memory cell has a surface area that is approximately 4 F2, where F is a minimum feature size. Also disclosed are processes for fabricating the DRAM cell using bulk silicon or a silicon on insulator processing techniques.

Abstract: The present invention provides a process for fabricating a metal oxide semiconductor field effect transistor (MOSFET) having a double-gate and a double-channel wherein the gate region is self-aligned to the channel regions and the source/drain diffusion junctions. The present invention also relates to the FIN MOSFFET structure which is formed using method of the present invention.

Abstract: Embodiment of the present invention are directed to improving the performance of a DMOS transistor. A method of fabricating a DMOS transistor comprises providing a semiconductor substrate having a gate oxide and a trenched gate, and implanting first conductive dopants into a surface of the semiconductor substrate adjacent to the trenched gate to form a first doping region. An insulating layer is deposited over the semiconductor substrate; and selectively etching the insulating layer to form a source contact window over a central portion of the first doping region and to leave an insulator structure above the trenched gate. The source contact window of the insulating layer has an enlarged top portion which is larger in size than a bottom portion of the source contact window closer to the first doping region than the enlarged top portion. The enlarged top portion is typically bowl-shaped.

Abstract: Form a bitline contact to deep trench gates separated from a substrate body by gate oxide with sources next to the gates near the top of the body and drains formed in the body of the substrate connected to a deep trench capacitor, with sidewall spacers between the gates and upper sidewalls of the deep trench. Form a patterning mask over the device exposing a portion of an upper surface of a gate electrode at the top surface of the substrate with a patterning mask patterned by a line shaping master mask. Etch a divot reaching down into the gate electrode alongside a deep trench sidewall spacer juxtaposed with a source. Fill the divot with a dielectric material. Form a wordline stack with a wordline and a silicon nitride cap in contact with the gate electrode. Form an etch resistant conformal liner and then form a planarized ILD layer and a glass layer covering the ILD layer.

Abstract: An improved isolation structure for use in an integrated circuit and a method for making the same is disclosed. In a preferred embodiment, an silicon dioxide, polysilicon, silicon dioxide stack is formed on a crystalline silicon substrate. The active areas are etched to expose the substrate, and sidewall oxides are formed on the resulting stacks to define the isolation structures, which in a preferred embodiment constitute dielectric boxes containing the polysilicon in their centers. Epitaxial silicon is grown on the exposed areas of substrate so that it is substantially as thick as the isolation structure, and these grown areas define the active areas of the substrate upon which electrical structures such as transistors can be formed. While the dielectric box provides isolation, further isolation can be provided by placing a contact to the polysilicon within the box and by providing a bias voltage to the polysilicon.

Abstract: A method and system for manufacturing an MIM capacitor for utilization with a logic-based embedded DRAM device. At least one transistor, an interlayer dielectric, at least one contact and at least one metal one layer are generally formed on a substrate during a front end manufacturing operation of the capacitor on the substrate. An inter-metal dielectric layer is deposited upon the substrate, followed thereafter by a chemical mechanical polishing operation. Additionally, a lithographic operation is performed upon the substrate. Also, at least one dielectric deposition layer is generally on the substrate, followed thereafter by a chemical mechanical polishing operation and a stop on an oxide layer formed on the substrate. At least one metal two layer may then be formed on substrate and associated layers thereof, thereby resulting in the formation of a capacitor fully compatible with logic-based devices and processes thereof.

Abstract: A memory cell structure including a planar semiconductor substrate. A deep trench is in the semiconductor substrate. The deep trench has a plurality of side walls and a bottom. A storage capacitor is at the bottom of the deep trench. A vertical transistor extends down at least one side wall of the deep trench above the storage capacitor. The transistor has a source diffusion extending in the plane of the substrate adjacent the deep trench. An isolation extends down at least one other sidewall of the deep trench opposite the vertical transistor. Shallow trench isolation regions extend along a surface of the substrate in a direction transverse to the sidewall where the vertical transistor extends. A gate conductor extends within the deep trench. A wordline extends over the deep trench and is connected to the gate conductor. A bitline extends above the surface plane of the substrate and has a contact to the source diffusion between the shallow trench isolation regions.

Abstract: A method for processing a semiconductor memory device is disclosed, the memory device including an array area and a support area thereon. In an exemplary embodiment of the invention, the method includes removing, from the array area, an initial pad nitride material formed on the device. The initial pad nitride material in the support area, however, is still maintained. Active device areas are then formed within the array area, wherein the initial pad nitride maintained in the support area helps to protect the support area from wet etch processes implemented during the formation of active device areas within the array area.

Abstract: Disclosed are a semiconductor integrated circuit device and a method of manufacturing the same capable of improving the characteristics of the semiconductor integrated circuit device by reducing a leakage current of a capacitor used in a DRAM memory cell. A data storage capacitor connected to a data transfer MISFET in a memory cell forming area via plugs is formed in the following manner. That is, a lower electrode composed of an Ru film is formed in a hole in a silicon oxide film, and then, a tantalum oxide film is deposited on the lower electrode. Thereafter, a first thermal treatment in an oxidizing atmosphere is performed to the film at a temperature sufficient to repair an oxygen defect and having no influence on the materials below the tantalum oxide film. Further, a second thermal treatment in an inactive atmosphere is performed at a temperature at which the tantalum oxide film is not completely crystallized (650° C.) and higher than that applied in the later process.

Abstract: A vertical power transistor trench-gate semiconductor device has an active area (100) accommodating transistor cells and an inactive area (200) accommodating a gate electrode (25) (FIG. 6). While an n-type layer (14) suitable for drain regions still extends to the semiconductor body surface (10a), gate material (11) is deposited in silicon dioxide insulated (17) trenches (20) and planarised to the top of the trenches (20) in the active (100) and inactive (200) areas. Implantation steps then provide p-type channel-accommodating body regions (15A) in the active area (100) and p-type regions (15B) in the inactive area (200), and then source regions (13) in the active area (100). Further gate material (111) is then provided extending from the gate material (11) in the inactive area (200) and onto a top surface insulating layer (17B) for contact with the gate electrode (25).

Abstract: A vertical read-only memory (ROM) is provided, which includes a gate on a substrate, a source/drain at the bottom of a trench in the substrate, a polysilicon bit-line in the trench, and a dielectric layer separating the polysilicon bit-line and the side-walls of the trench. The polysilicon bit-line electrically connects with the source/drain. The substrate of the side-wall of the trench adjacent to the gate serves as a coding region.

Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 &mgr;m or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

Abstract: An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device.

Abstract: A trench top isolation (TTI) layer (148) and method of forming thereof for a vertical DRAM. A first assist layer (134) is disposed over trench sidewalls (133) and trench capacitor top surfaces (131). A second assist layer (136) is disposed over the first assist layer (134). The second assist layer (136) is removed from over the trench capacitor top surface (131), and the first assist layer (134) is removed from the trench capacitor top surface (131) using the second assist layer (136) as a mask. The second assist layer (136) is removed, and a first insulating layer (140) is disposed over the first assist layer (134) and trench capacitor top surface (131). A second insulating layer (142) is disposed over the first insulating layer (140), and the second insulating layer (142) is removed from the trench sidewalls (133). The first insulating layer (140) and the first assist layer (134) are removed from the trench sidewalls (133).

Abstract: The present invention provides an easy post GC etch treatment that can remove vertical GC residues without affecting the support devices while ensuring a robust GC to vertical gate contact in all alignment scenarios. The conductive vertical gate contact of the present invention, in conjunction with any DT top isolation approach, allows for an aggressive post GC etch treatment to avoid gate to bit line shorts without compromising the contact between the GC and the vertical gate.

Abstract: An integrated circuit chip is provided having both a conventional DRAM vertical transfer device and an integrated vertical storage capacitor or anti-fuse that can be accessed directly without having to turn on a transfer gate. The mechanism for accessing the integrated capacitor or anti-fuse directly can be a modified doping profile within the vertical cell that provides a low resistance punch-through FET. Alternatively, the mechanism can be a pair of overlapping or nearly overlapping diffusions within the vertical cell.

Abstract: A dynamic random access memory (DRAM) device having a vertical transistor and an internally-connected strap (ICS) to connect the transistor to the capacitor. The ICS makes no direct contact with the substrate. The DRAM cell operates at a substantially lower cell capacitance than that required for a conventional buried strap trench (BEST) cell without causing any negative impact on device performance. The lower cell capacitance also extends the feasibility of deep trench capacitor manufacturing technology without requiring new materials or processing methods. A method of manufacturing the DRAM includes forming a very thin Si layer on top of a DT cell while at the same time the method forms an isolated layer replacing a conventional collar. The formation of the SOI by internal thermal oxidation (ITO) makes the structure in such a manner that the device may be fully depleted.

Abstract: Structures and method for programmable memory address and decode circuits with ultra thin vertical body transistors are provided. The memory address and decode circuits includes a number of address lines and a number of output lines such that the address lines and the output lines form an array. A number of vertical pillars extend outwardly from a semiconductor substrate at intersections of output lines and address lines. Each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer. A number of single crystalline ultra thin vertical floating gate transistors that are selectively disposed adjacent the number of vertical pillars.

Abstract: The process first forms trench capacitors in a substrate, which are filled with a trench fill and in which a first insulating layer is disposed over the conductive trench fill. The first insulating layer is then overgrown laterally by a selectively grown epitaxial layer. The selective epitaxial layer is so structured that a ridge is formed from it. Next, the ridge is partially undercut, whereby the etch selectivity of the ridge relative to the first insulating layer is utilized for a wet-chemical etching procedure. Next, a contact layer is arranged in the undercut region, which connects the ridge and a transistor that has been formed in the ridge to the conductive trench fill. Lateral margin ridges are then formed next to the ridge as a gate, and a doped region is incorporated into the ridge as a source/drain zone of the transistor.

Abstract: A dynamic random access memory (DRAM) device comprises a substrate, a plurality of substantially parallel word lines, and a plurality of substantially parallel bit lines. A plurality of memory cells are formed at intersections of the word lines and bit lines. Each of the memory cells includes a pillar of semiconductor material which extends outward from the substrate. A storage node plug extends from a storage node through the pillar to a storage node contact and one of a drain and a source of a MOS transistor. A bit line plug extends from the bit line inwardly to the outer surface of the pillar to form a bit line contact and the other of the drain and the source of the MOS transistor. A word line plug extends from the word line through the pillar and a portion of the word line plug forms a gate of the MOS transistor. The storage node plug, bit line plug, and word line plug can be formed asymmetrically as substantially solid, unitary structures having a desired thickness for ease in manufacturing.

Abstract: A MOS transistor includes an upper source/drain region, a channel region, and a lower source/drain region that are stacked as layers one above the other and form a projection of a substrate. A gate dielectric adjoins a first lateral area of the projection. A gate electrode adjoins the gate dielectric. A conductive structure adjoins a second lateral area of the projection in the region of the channel region. The conductive structure adjoins the gate electrode.

Abstract: In a gas-phase treating process of a semiconductor wafer using hydrogen, there is provided a technique for safely eliminating the hydrogen in an exhaust gas discharged from a gas-phase treating apparatus. The profile at the end portions of the side walls of gate electrodes of a poly-metal structure is improved by forming the gate electrodes over a semiconductor wafer IA having a gate oxide film and then by supplying the semiconductor wafer 1A with a hydrogen gas containing a low concentration of water, as generated from hydrogen and oxygen by catalytic action, to oxidize the principal face of the semiconductor wafer 1A selectively. After this, the hydrogen in the exhaust gas, as discharged from an oxidizing furnace, is completely converted into water by causing it to react with oxygen by a catalytic method.

Abstract: A trench DMOS transistor cell is provided, which is formed on a substrate of a first conductivity type. A body region, which has a second conductivity type, is located on the substrate. At least one trench extends through the body region and the substrate. An insulating layer lines the trench. The insulating layer includes first and second portions that contact one another at an interface. The first portion of the insulating layer has a layer thickness greater than the second portion. The interface is located at a depth above a lower boundary of the body region. A conductive electrode is formed in the trench so that it overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench.