Including Device Responsive To Nonelectrical Signal Patents (Class 438/24)
  • Publication number: 20100207127
    Abstract: A light emitting diode (LED) includes a substrate, a temperature detecting pattern, and a semiconductor structure. The temperature detecting pattern is formed on the substrate. Then the semiconductor structure is formed on the temperature detecting pattern and the substrate. The semiconductor structure includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer. Per above-mentioned structural design, the temperature detecting pattern directly integrated into the LED can measure the actual temperature of PN junction with high precision.
    Type: Application
    Filed: September 22, 2009
    Publication date: August 19, 2010
    Applicants: SILITEK ELECTRONIC (GUANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATION
    Inventor: Chen-Yu Chen
  • Patent number: 7777240
    Abstract: An optoelectronic device such as a light-emitting diode chip is disclosed. It includes a substrate, a multi-layer epitaxial structure, a first metal electrode layer, a second metal electrode layer, a first bonding pad and a second bonding pad. The multi-layer epitaxial structure on the transparent substrate comprises a semiconductor layer of a first conductive type, an active layer, and a semiconductor layer of a second conductive type. The first bonding pad and the second bonding pad are on the same level. Furthermore, the first metal electrode layer can be patterned so the current is spread to the light-emitting diode chip uniformly.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: August 17, 2010
    Assignee: Epistar Corporation
    Inventors: Jin-Ywan Lin, Jen-Chau Wu, Chih-Chiang Lu, Wei-Chih Peng, Ching-Pu Tai, Shih-I Chen
  • Publication number: 20100200760
    Abstract: The invention relates to a radiation detector and a method for producing such a detector, wherein the detector comprises a stack of the scintillator elements and photodiode arrays. The PDAs extend with electrical leads into a rigid body filling a border volume lateral of the scintillator elements, wherein said leads end in a contact surface of the border volume. Moreover, a redistribution layer is disposed on the contact surface, wherein electrical lines of the redistribution layer contact the leads of the PDAs.
    Type: Application
    Filed: February 2, 2010
    Publication date: August 12, 2010
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Christian BAEUMER, Oliver MUELHENS, Roger STEADMAN BOOKER, Christoph HERRMANN
  • Patent number: 7772585
    Abstract: A nitride semiconductor crystal substrate is produced by forming a network mask repeating a closed loop unit shape upon an undersubstrate, growing a nitride semiconductor crystal in vapor phase, producing convex facet hills covered with facets on exposed parts ?, forming outlining concavities on mask-covered parts , not burying the facets, maintaining the convex facet hills on ? and the network concavities on , excluding dislocations in the facet hills down to the outlining concavities on , forming a defect accumulating region H on , decreasing dislocations in the facet hills and improving the facet hills to low defect density single crystal regions Z, producing a rugged nitride crystal, and slicing and polishing the nitride crystal into mirror nitride crystal wafers. After the fabrication of devices on the nitride wafer, dry-etching or wet etching of hot KOH or NaOH divides the device-carrying wafer into chips by corroding the network defect accumulating region H.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: August 10, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Koji Uematsu, Fumitaka Sato, Ryu Hirota, Seiji Nakahata, Hideaki Nakahata
  • Patent number: 7771532
    Abstract: A nitride semiconductor crystal substrate is produced by forming a network mask repeating a closed loop unit shape upon an undersubstrate, growing a nitride semiconductor crystal in vapor phase, producing convex facet hills covered with facets on exposed parts ?, forming outlining concavities on mask-covered parts , not burying the facets, maintaining the convex facet hills on ? and the network concavities on , excluding dislocations in the facet hills down to the outlining concavities on , forming a defect accumulating region H on , decreasing dislocations in the facet hills and improving the facet hills to low defect density single crystal regions Z, producing a rugged nitride crystal, and slicing and polishing the nitride crystal into mirror nitride crystal wafers. After the fabrication of devices on the nitride wafer, dry-etching or wet etching of hot KOH or NaOH divides the device-carrying wafer into chips by corroding the network defect accumulating region H.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: August 10, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Koji Uematsu, Fumitaka Sato, Ryu Hirota, Seiji Nakahata, Hideaki Nakahata
  • Patent number: 7772017
    Abstract: In the solid-state imaging device of the present invention having a photoelectric conversion section and a charge transfer section equipped with a charge transfer electrode for transferring an electric charge generated in the photoelectric conversion section, the charge transfer electrode has an alternate arrangement of a first layer electrode comprising a first layer electrically conducting film and a second layer electrode comprising a second layer electrically conducting film, which are formed on a gate oxide film comprising a laminate film consisting of a silicon oxide film and a metal oxide thin film, and the first layer electrode and the second layer electrode are separated by insulation with an interelectrode insulating film comprising a sidewall insulating film formed by a CVD process to cover the lateral wall of the first layer electrode.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: August 10, 2010
    Assignee: Fujifilm Corporation
    Inventor: Maki Saito
  • Patent number: 7768032
    Abstract: A light-emitting device comprises first and second dot members. The first dot member is formed so that it makes contact with the second dot member. The first dot member comprises a plurality of first quantum dot layers. Each of the plurality of first quantum dot layers comprises a plurality of first quantum dots and a silicon dioxide film. The first quantum dot comprises an n-type silicon dot. The second dot member comprises a plurality of second quantum dot layers. Each of the plurality of second quantum dot layers comprises a plurality of second quantum dots and a silicon dioxide film. The second quantum dot comprises a p-type silicon dot.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: August 3, 2010
    Assignee: Hiroshima University
    Inventors: Katsunori Makihara, Seiichi Miyazaki, Seiichiro Higashi
  • Patent number: 7763900
    Abstract: Disclosed are a light emitting device having a plurality of light emitting cells connected in series and a method of fabricating the same. The light emitting device includes a buffer layer formed on a substrate. A plurality of rod-shaped light emitting cells are located on the buffer layer to be spaced apart from one another. Each of the light emitting cells has an n-layer, an active layer and a p-layer. Meanwhile, wires connect the spaced light emitting cells in series or parallel. Accordingly, arrays of the light emitting cells connected in series are connected to be driven by currents flowing in opposite directions. Thus, there is provided a light emitting device that can be directly driven by an AC power source.
    Type: Grant
    Filed: July 4, 2005
    Date of Patent: July 27, 2010
    Assignee: Seoul Opto Device Co., Ltd.
    Inventor: Chung Hoon Lee
  • Patent number: 7763479
    Abstract: A method for fabricating pixel structures is disclosed. Specifically, the present invention deposits a conductive layer, a gate dielectric layer, and an aluminum layer on a gate dielectric layer, and performs an isotropic etching process to evenly etch a portion of the aluminum layer in the horizontal and vertical direction. By following this process, the number of photomasks used before the formation of the source/drain region can be reduced, and the conductive layer and the aluminum layer disposed on the capacitor electrode in the capacitor region can be used to increase the capacitance of the capacitor.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: July 27, 2010
    Assignee: AU Optronics Corp.
    Inventors: Ta-Wei Chiu, Yi-Sheng Cheng, Shih-Yi Yen
  • Patent number: 7754506
    Abstract: A method of fabricating submicron objects that includes the following steps: depositing a void layer on a support, depositing a transfer layer on the void layer, producing the objects in the transfer layer, producing a hard mask on a portion of the transfer layer to delimit a region comprising a portion of the objects, and etching the combination formed by the hard mask, the transfer layer and the void layer to eliminate the hard mask and the portion of the transfer layer in the region and to open up the portion of the void layer under the region so that the objects are suspended, the rate of etching the void layer being greater than the rate of etching the transfer layer and the hard mask.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: July 13, 2010
    Assignee: Altis Semiconductor
    Inventors: Pierre Vekeman, Sodonie Lefebvre, Thierry Hoc, Pascal Deconinck
  • Publication number: 20100171120
    Abstract: In the case of forming switching elements and light sensor elements over the same substrate, an increase in the film thickness of active layers in an attempt to enhance the sensitivity of the light sensor elements would adversely affect the characteristics of the switching elements (TFTs). In a configuration of a display in which a channel layer 25 for constituting thin film transistors to form the switching elements for pixels and a photoelectric conversion layer 35 for constituting the light sensor elements are provided over a gate insulating film 24 on a glass substrate 5 to be provided with a plurality of pixels arranged in a matrix pattern, the photoelectric conversion layer 35 is formed to be thicker than the channel layer 25, and/or the photoelectric conversion layer 35 is formed of a material different from the material for the channel layer 25, whereby the light absorption coefficient of the photoelectric conversion layer 35 is made to be higher than that of the channel layer 25.
    Type: Application
    Filed: September 18, 2008
    Publication date: July 8, 2010
    Applicant: SONY CORPORATION
    Inventors: Dharam Pal Gosain, Tsutomu Tanaka, Makoto Takatoku
  • Patent number: 7745246
    Abstract: A light emitting device wafer is fabricated, having a light emitting layer section, composed of AlGaInP, based on a double heterostructure and a GaP light extraction layer disposed on the light emitting layer portion, having a first main surface thereof appearing on the first main surface of the wafer, so as that a P-rich off-angled {100} surface, having a higher existence rate of P atoms than an exact {100} surface, appears on the first main surface the GaP light extraction layer. The main first surface of the GaP light extraction layer is etched with an etching solution FEA so as to form surface roughening projections. Therefore, it provides a method of fabricating a light emitting device capable of applying surface roughening easily to the GaP light extraction surface having the {100} surface, off-angled to be P-rich, as a main surface thereof.
    Type: Grant
    Filed: May 29, 2006
    Date of Patent: June 29, 2010
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Yukari Suzuki, Hitoshi Ikeda
  • Publication number: 20100155731
    Abstract: The present invention relates to a touching-type electronic paper and method for manufacturing the same. The touching-type electronic paper includes a TFT substrate and a transparent electrode substrate which are disposed as a cell. The transparent electrode substrate includes a common electrode, microcapsule electronic ink and light guiding poles as light transmitting passages, all of which are formed on a first substrate. The TFT substrate comprises displaying electrodes, first TFTs for driving the displaying electrodes, second TFTs for detecting lights transmitting through the light guiding poles and for producing level signals, and third TFTs for reading the level signals and sending the level signals to a back-end processing system, all of which are formed on a second substrate. The light guiding poles are opposite to the second TFTs respectively.
    Type: Application
    Filed: September 10, 2009
    Publication date: June 24, 2010
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: ZENGHUI SUN, Wenjie Hu, Zhuo Zhang, Gang Wang, Xibin Shao
  • Patent number: 7742677
    Abstract: A method for producing an optoelectronic component is disclosed. The method includes the steps of providing a substrate, applying a semiconductor layer sequence to the substrate, applying at least two current expansion layers to the semiconductor layer sequence, applying and patterning a mask layer, patterning the second current expansion layer by means of an etching process during which sidewalls of the mask layer are undercut, patterning the first current expansion layer by means of an etching process during which the sidewalls of the mask layer are undercut at least to a lesser extent than during the patterning of the second current expansion layer, and removing the mask layer.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: June 22, 2010
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Franz Eberhard, Uwe Strauss, Ulrich Zehnder, Andreas Weimar, Raimund Oberschmid
  • Patent number: 7736923
    Abstract: An optical semiconductor device includes: a first conductivity type first semiconductor region; a first conductivity type second semiconductor region formed on the first semiconductor region; a second conductivity type third semiconductor region formed on the second semiconductor region; a photodetector section formed of the second semiconductor region and the third semiconductor region; a micro mirror formed of a trench formed selectively in a region of the first semiconductor region and the second semiconductor region except the photodetector section; and a semiconductor laser element held on the bottom face of the trench. A first conductivity type buried layer of which impurity concentration is higher than those of the first semiconductor region and the second semiconductor region is selectively formed between the first semiconductor region and the second semiconductor region in the photodetector section.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: June 15, 2010
    Assignee: Panasonic Corporation
    Inventor: Takaki Iwai
  • Publication number: 20100140631
    Abstract: Provided are a display device in which variation in output characteristics of the photodiode is suppressed, and a method for manufacturing the display device. The display device is provided with the active matrix substrate (2) and photodiode (6). First, on a substrate of glass (12), a silicon film (8) and an interlayer insulation film (15) for covering the silicon film (8) are formed in this order. Then, a metal film is formed, and metal lines (10, 11) traversing the silicon film (8) are formed by etching the metal film. Then, p-type impurity ions are implanted by using a mask that has an opening (24a) that exposes a portion that overlaps a region where a p-layer (9a) is to be formed, a part of the opening (24a) being formed with the metal line (10). Furthermore, n-type impurity ions are implanted by using a mask that has an opening (25b) that exposes a portion that overlaps a region where an n-layer (9c) is to be formed, a part of the opening (25a) being formed with the metal line (11).
    Type: Application
    Filed: April 17, 2008
    Publication date: June 10, 2010
    Inventors: Masaki Yamanaka, Hiromi Katoh, Christopher Brown
  • Publication number: 20100142881
    Abstract: A circuit includes a flexible circuit having an optical waveguide embedded therein, a first device attached to the flexible circuit and configured to convert a first electrical signal to an optical signal, the first device positioned to emit the optical signal to an input end of the optical waveguide, and a second device attached to the flexible circuit and configured to convert the optical signal into a second electrical signal, the second device positioned to receive the optical signal from an output end of the optical waveguide.
    Type: Application
    Filed: December 5, 2008
    Publication date: June 10, 2010
    Inventors: David William Vernooy, Samhita Dasgupta
  • Patent number: 7732232
    Abstract: Series interconnection of optoelectronic device modules is disclosed. Each device module includes an active layer disposed between a bottom electrode and a transparent conducting layer. An insulating layer is disposed between the bottom electrode of a first device module and a backside top electrode of the first device module. One or more vias are formed through the active layer, transparent conducting layer and insulating layer of the first device module. Sidewalls of the vias are coated with an insulating material such that a channel is formed through the insulating material to the backside top electrode of the first device module. The channel is at least partially filled with an electrically conductive material to form a plug that makes electrical contact between the transparent conducting layer and the backside top electrode of the first device module.
    Type: Grant
    Filed: October 1, 2007
    Date of Patent: June 8, 2010
    Assignee: Nanosolar, Inc.
    Inventors: James R. Sheats, Sam Kao, Gregory A. Miller, Martin R. Roscheisen
  • Patent number: 7732229
    Abstract: Methods and devices are provided for absorber layers formed on foil substrate. In one embodiment, a method of manufacturing photovoltaic devices may be comprised of providing a substrate comprising of at least one electrically conductive aluminum foil substrate, at least one electrically conductive diffusion barrier layer, and at least one electrically conductive electrode layer above the diffusion barrier layer. The diffusion barrier layer may prevent chemical interaction between the aluminum foil substrate and the electrode layer. An absorber layer may be formed on the substrate. In one embodiment, the absorber layer may be a non-silicon absorber layer. In another embodiment, the absorber layer may be an amorphous silicon (doped or undoped) absorber layer. Optionally, the absorber layer may be based on organic and/or inorganic materials.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: June 8, 2010
    Assignee: Nanosolar, Inc.
    Inventors: Craig Leidholm, Brent Bollman, James R. Sheats, Sam Kao, Martin R. Roscheisen
  • Patent number: 7727786
    Abstract: An optical memory cell having a material layer associated with a pixel capable of emitting and receiving light. The material layer has phosphorescent material formed therein for storing data as light received from and emitted to the pixel.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: June 1, 2010
    Inventor: Terry L. Gilton
  • Patent number: 7727785
    Abstract: A method for balancing layer-caused compressive or tensile stress in a semiconductor die, die wafer or similar substrate uses a stress-balancing layer (SBL) attached to an opposite side from a stress-causing layer before the semiconductor die or wafer is significantly warped are provided. The SBL may also serve as, or support, an adhesive layer for die attach and be of a markable material for an enhanced marking method.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: June 1, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Michael E. Connell, Tongbi Jiang
  • Patent number: 7723140
    Abstract: A pixel cell with controlled leakage is formed by modifying the location and gate profile of a high dynamic range (HDR) transistor. The HDR transistor may have the gate profile of a transfer gate or a reset gate. The HDR transistor may be located on a side of the photodiode that is the same, opposite to, or perpendicular to the transfer gate. The leakage through the HDR transistor may be controlled by modifying the photodiode implants around the transistor. The photodiode implants at the HDR transistor may be placed similarly to the implants at the transfer gate. However, when the photodiode implants are moved away from the HDR transistor, leakage is reduced. When the photodiode implants are moved farther under the HDR transistor, leakage is increased to the extent desirable. The leakage through the HDR transistor may also be controlled by applying a voltage across the transistor.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: May 25, 2010
    Assignee: Aptina Imaging Corporation
    Inventor: Howard E. Rhodes
  • Patent number: 7718991
    Abstract: A lighting device comprises a solid state light emitter, first and second electrodes connected to the emitter, an encapsulant region comprising a silicone compound and a supporting region. The encapsulant region extends to an external surface of the lighting device. At least a portion of the first electrode is surrounded by the supporting region. The encapsulant region and the supporting region together define an outer surface which substantially encompasses the emitter. A method of making a lighting device, comprises electrically connecting first and second electrodes to an emitter; inserting the emitter into mold cavity; inserting an encapsulant composition comprising a one silicone compound; and then inserting a second composition to substantially surround at least a portion of the first electrode.
    Type: Grant
    Filed: May 22, 2007
    Date of Patent: May 18, 2010
    Assignee: Cree LED Lighting Solutions, Inc.
    Inventor: Gerald H. Negley
  • Patent number: 7713767
    Abstract: A method of making a circuitized substrate (e.g., PCB) including at least one and possibly several internal optical pathways as part thereof such that the resulting substrate will be capable of transmitting and/or receiving both electrical and optical signals. The method involves forming at least one opening between a side of the optical core and an adjacent upstanding member such that the opening is defined by at least one angular sidewall. Light passing through the optical core material (or into the core from above) is reflected off this angular sidewall. The medium (e.g., air) within the opening thus also serves as a reflecting medium due to its own reflective index in comparison to that of the adjacent optical core material. The method utilizes many processes used in conventional PCB manufacturing, thereby keeping costs to a minimum.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: May 11, 2010
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Benson Chan, How T. Lin, Roy H. Magnuson, Voya R. Markovich, Mark D. Poliks
  • Patent number: 7714333
    Abstract: A solid-state element has: a semiconductor layer formed on a substrate, the semiconductor layer having a first layer that corresponds to an emission area of the solid-state element to and a second layer through which current is supplied to the first layer; a light discharge surface through which light emitted from the first layer is externally discharged, the light discharge surface being located on the side of the substrate; and an electrode having a plurality of regions that are of a conductive material and are in ohmic-contact with the second layer.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: May 11, 2010
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Yoshinobu Suehiro, Seiji Yamaguchi
  • Patent number: 7709358
    Abstract: Optoelectronic device including integrated light emitting device and photodiode. The optoelectronic device includes a light emitting device such as a vertical cavity surface emitting laser (VCSEL) or resonant cavity light emitting diode (RCLED). A photodiode is also included in the optoelectronic device. Between the light emitting device and the photodiode is a transition region. At least part of the transition region is shorted. A metal contact provides a contact to both the light emitting device and the photodiode.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: May 4, 2010
    Assignee: Finisar Corporation
    Inventors: James Guenter, James R. Biard
  • Publication number: 20100099206
    Abstract: A manufacturing method of a thin film transistor array substrate is provided. In the method, a substrate having a display region and a sensing region is provided. At least a display thin film transistor is formed in the display region, a first sensing electrode is formed in the sensing region, and an inter-layer dielectric layer is disposed on the substrate, covers the display thin film transistor, and exposes the first sensing electrode. A patterned photo sensitive dielectric layer is then formed on the first sensing electrode. A patterned transparent conductive layer is subsequently formed on the substrate, wherein the patterned transparent conductive layer includes a pixel electrode coupled to the corresponding display thin film transistor and includes a second sensing electrode located on the patterned photo sensitive dielectric layer. A manufacturing method of a liquid crystal display panel adopting the aforementioned thin film transistor array substrate is also provided.
    Type: Application
    Filed: December 22, 2009
    Publication date: April 22, 2010
    Applicant: AU OPTRONICS CORPORATION
    Inventors: An-Thung Cho, Chia-Tien Peng, Yuan-Jun Hsu, Ching-Chieh Shih, Chien-Sen Weng, Kun-Chih Lin, Hang-Wei Tseug, Ming-Huang Chuang
  • Publication number: 20100096004
    Abstract: A solar cell comprising at least one nanostructure-film electrode is discussed. The solar cell may further comprise a different conducting material, such as a conducting polymer, to fill pores in the nanostructure-film. Additionally or alternatively, the solar cell may comprise an electrode grid superimposed on the nanostructure-film. Likewise, the solar cell may have a single or multiple active layer(s), wherein nanostructure-film(s) may form at least semi-transparent anode(s) and/or cathode(s) through use of buffer layer(s).
    Type: Application
    Filed: October 25, 2006
    Publication date: April 22, 2010
    Applicant: UNIDYM, INC.
    Inventors: Liangbing Hu, David Hecht, George Gruner
  • Patent number: 7696098
    Abstract: A unipolar semiconductor laser is provided in which an active region is sandwiched in a guiding structure between an upper and lower cladding layer, the lower cladding layer being situated on a semiconducting substrate. The unipolar semiconductor laser comprises a raised ridge section running from end to end between end mirrors defining the laser cavity. The ridge section aids in optical and electrical confinement. The ridge waveguide is divided in a plurality of cavity segments (at least two). Lattice structures can be arranged on and/or adjacent to these cavity segments. Each cavity segment is in contact with upper metallic electrodes. A metallic electrode coupled to the bottom surface of the semiconducting substrate facilitates current injection through the device.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: April 13, 2010
    Assignee: Nanoplus GmbH
    Inventors: Marc Fischer, Alfred Forchel
  • Publication number: 20100084958
    Abstract: A light emitting diode (LED) structure, a manufacturing method thereof and a LED module are provided. The LED structure has temperature sensing function. The LED structure comprises a composite substrate and an LED. The composite substrate comprises a diode structure whose P-type semiconductor region or N-type semiconductor region has a predetermined doping concentration. The diode structure is a temperature sensor, and the sensitivity of the temperature sensor is based on the predetermined doping concentration. The LED is disposed on the composite substrate. The diode structure is used for sensing the heat emitted from the LED.
    Type: Application
    Filed: September 25, 2009
    Publication date: April 8, 2010
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Tsung Shih, Chen-Peng Hsu, Hung-Lieh Hu
  • Patent number: 7692256
    Abstract: A method for manufacturing a wafer scale package including at least one substrate having replicated optical elements. The method uses two substrates, at least one of which is pre-shaped and has at least one recess in its front surface. Optical elements are replicated on a first substrate by causing a replication tool to abut the first substrate. The second substrate is then attached to the first substrate in an abutting relationship in such a way that the optical element is contained in a cavity formed by the recess in one of the substrates in combination with the other substrate. Thereby, a well defined axial distance between the optical elements and the second substrate is achieved. Consequently, a well defined axial distance between the optical elements and any other objects attached to the second substrate, e.g. further optical elements, image capturing devices, light sources, is also established.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: April 6, 2010
    Assignee: Heptagon Oy
    Inventors: Hartmut Rudmann, Stephan Heimgartner, Markus Rossi
  • Patent number: 7687811
    Abstract: A light emitting device having a vertical structure and a method for manufacturing the same, which are capable of increasing light extraction efficiency, are disclosed. The method includes forming a light extraction layer on a substrate, forming a plurality of semiconductor layers on the light extraction layer, forming a first electrode on the semiconductor layers, forming a support layer on the first electrode, removing the substrate, and forming a second electrode on a surface from which the substrate is removed.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: March 30, 2010
    Assignees: LG Electronics Inc., LG Innotek Co., Ltd.
    Inventors: Jun Ho Jang, Yong Tae Moon
  • Publication number: 20100072486
    Abstract: A light emitting device (1) is provided and comprises a light emitting diode (2) and a self-supporting wavelength converting element (3) arranged to receive at least part of the light emitted by said light emitting diode (2). The wavelength converting element has a flat light receiving surface (4), a light output surface (5) and lateral edge surfaces (6), wherein said lateral edge surfaces (6) are provided with a reflecting material (7). The reflecting edge surfaces increases the color homogeneity of the light exiting the device and the device is suitable for mass production.
    Type: Application
    Filed: October 30, 2007
    Publication date: March 25, 2010
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Paulus Hubertus Gerardus Offermans, Emanuel Johannes Wilhelmus Maria Lenders
  • Publication number: 20100072450
    Abstract: A phase change memory device includes a semiconductor substrate having a conductive region, a heater electrode formed on the semiconductor substrate and including a connection element which is composed of carbon nanotubes electrically connected with the conductive region, and a phase change pattern layer contacting the connection element of the heater electrode.
    Type: Application
    Filed: December 29, 2008
    Publication date: March 25, 2010
    Inventor: Min Seok SON
  • Publication number: 20100051956
    Abstract: A thin film transistor array panel includes a substrate; a first gate line disposed on the substrate and including a gate electrode; a storage electrode disposed in a layer which is the same layer as a layer of the first gate line; a gate insulating layer disposed on the first gate line and the storage electrode; a semiconductor disposed on the gate insulating layer and including a channel portion; a data line disposed on the semiconductor and including a source electrode; a drain electrode disposed on the semiconductor and facing the source electrode; a passivation layer disposed on the gate insulating layer, the data line, and the drain electrode, the passivation layer including a contact hole which exposes a portion of the drain electrode; and a pixel electrode disposed on the passivation layer and electrically connected to the drain electrode through the contact hole, wherein the gate insulating layer and the passivation layer are interposed between the pixel electrode and the substrate except for a regio
    Type: Application
    Filed: January 15, 2009
    Publication date: March 4, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Chun-Gi YOU
  • Patent number: 7657995
    Abstract: A method of fabricating a MEMS switch that is fully integratable in a semiconductor fabrication line. The method consists of forming two posts, each end thereof terminating in a cap; a rigid movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; forming upper and lower electrode pairs and upper and lower interconnect wiring lines connected and disconnected by the rigid movable conductive plate. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: February 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Louis Hsu, Timothy Dalton, Lawrence Clevenger, Carl Radens, Kwong Hon Wong, Chih-Chao Yang
  • Publication number: 20100029026
    Abstract: The invention relates to a method of fabricating an optical device for analysing a scene, comprising an emitter and a detector in the mid-infrared or far-infrared, characterized in that it comprises: the production of a stack of semiconductor layers grown epitaxially on the surface of a semiconductor substrate, certain layers of which are doped; the production of a first, quantum cascade laser emission device (L) emitting an analysis beam in the mid-infrared or far-infrared, from a first level called the emission level, into the stack of semiconductor layers; and the production of a second, quantum detector device (D) capable of detecting a beam backscattered by the scene to be analysed, at the same level in the stack as the emission level.
    Type: Application
    Filed: July 31, 2009
    Publication date: February 4, 2010
    Applicant: Thales
    Inventors: Vincent Berger, Mathieu Carras
  • Patent number: 7655960
    Abstract: Seeds are implanted in a regular pattern upon an undersubstrate. An AlxInyGa1?x?yN (0?x?1, 0?y?1, 0<x+y?1) mixture crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and make closed defect accumulating regions (H) under the facet bottoms. The closed defect accumulating regions (H) arrest dislocations permanently. Release of dislocations, radial planar defect assemblies and linear defect assemblies are forbidden. The surrounding accompanying low dislocation single crystal regions (Z) and extra low dislocation single crystal regions (Y) are low dislocation density single crystals.
    Type: Grant
    Filed: August 10, 2006
    Date of Patent: February 2, 2010
    Assignee: Sumito Electric Industries, Ltd.
    Inventors: Seiji Nakahata, Ryu Hirota, Kensaku Motoki, Takuji Okahisa, Kouji Uematsu
  • Patent number: 7651877
    Abstract: The present invention provides a two-dimensional image detecting apparatus including a mold structure which apparatus can be applied to mammography, and a manufacturing method thereof. The manufacturing method includes: a conversion layer formation step of forming a conversion layer (3) on an active matrix substrate (2); a counter substrate formation step of disposing a spacer material (5) and disposing the counter substrate (6) so as to be opposite to the active matrix substrate (2) via the spacer material (5); a mold resin layer formation step of forming a mold structure layer (8) in a space surrounded by the conversion layer (3), the spacer material (5), and the counter substrate (6); and a cutting step of cutting at least the active matrix substrate (2) so that cut surfaces of the constituent members are flush with each other; and a sealing step of securing a sealing material (7) to the cut surface.
    Type: Grant
    Filed: October 18, 2005
    Date of Patent: January 26, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yoshihiro Izumi
  • Publication number: 20100007621
    Abstract: A touch screen panel having an improved reflectance difference between sensing patterns. The touch screen panel includes a transparent substrate; a plurality of first sensing patterns on the transparent substrate and connected along a first direction; a first insulating layer on the first sensing patterns; and a plurality of second sensing patterns on the first insulating layer and connected along a second direction. The second sensing patterns are alternately disposed with the first sensing patterns and not overlapped with the first sensing patterns. The touch screen panel further includes a plurality of dummy patterns in at least one of first dummy regions between the first sensing patterns and second dummy regions between the second sensing patterns.
    Type: Application
    Filed: May 12, 2009
    Publication date: January 14, 2010
    Inventors: Sung-Ku Kang, Tae-Hyeog Jung, Jin-Guen Kim, Gi-Min Kim
  • Patent number: 7632692
    Abstract: A thin film transistor array panel is provided, which includes: a gate line formed on an insulating substrate; a gate insulating layer on the gate line; a semiconductor layer on the gate insulating layer; a data line formed on the gate insulating layer; a drain electrode formed at least in part on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode; a color filter formed on the data line and the drain electrode; a second passivation layer formed on the color filter; and a pixel electrode formed on the color filter, connected to the drain electrode, overlapping the second passivation layer, and enclosed by the second passivation layer.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: December 15, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dong-Gyu Kim
  • Patent number: 7632691
    Abstract: A surface mountable device having a circuit device and a base section. The circuit device includes top and bottom layers having a top contact and a bottom contact, respectively. The base section includes a substrate having a top base surface and a bottom base surface. The top base surface includes a top electrode bonded to the bottom contact, and the bottom base surface includes first and second bottom electrodes that are electrically isolated from one another. The top electrode is connected to the first bottom electrode, and the second bottom electrode is connected to the top contact by a vertical conductor. An insulating layer is bonded to a surface of the circuit device and covers a portion of a vertical surface of the bottom layer. The vertical conductor includes a layer of metal bonded to the insulating layer.
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: December 15, 2009
    Assignee: Bridgelux, Inc.
    Inventor: Frank T. Shum
  • Patent number: 7625603
    Abstract: A silicon oxide layer is formed by oxidation or decomposition of a silicon precursor gas in an oxygen-rich environment followed by annealing. The silicon oxide layer may be formed with slightly compressive stress to yield, following annealing, an oxide layer having very low stress. The silicon oxide layer thus formed is readily etched without resulting residue using HF-vapor.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: December 1, 2009
    Assignee: Robert Bosch GmbH
    Inventors: Aaron Partridge, Markus Lutz, Silvia Kronmueller
  • Publication number: 20090286336
    Abstract: A manufacturing method of a thin film transistor array substrate incorporating the manufacture of a photo-sensor is provided. In the manufacturing method, a photo-sensing dielectric layer is formed between a transparent conductive layer and a metal electrode for detecting ambient light. Since the transparent conductive layer is adopted as an electrode, the ambient light can pass through the transparent conductive layer and get incident light into the photo-sensing dielectric layer. Therefore, the sensing area of the photo-sensor can be enlarged and the photo-sensing efficiency is improved. In addition, the other side of the photo sensitive dielectric layer may be a metal electrode. The metal electrode can block the backlight from getting incident into the photo-sensing dielectric layer and thus reduce the background noise. A manufacturing method of a liquid crystal display panel adopting the aforementioned thin film transistor array substrate is also provided.
    Type: Application
    Filed: April 20, 2009
    Publication date: November 19, 2009
    Applicant: AU OPTRONICS CORPORATION
    Inventors: An-Thung Cho, Chia-Tien Peng, Yuan-Jun Hsu, Ching-Chieh Shih, Chien-Sen Weng, Kun-Chih Lin, Hang-Wei Tseug, Ming-Huang Chuang
  • Patent number: 7619258
    Abstract: In a light emitting device using a light emitting element, the invention provides a sealing structure capable of preventing ingress of moisture from the outside and obtaining adequate reliability. The light emitting device has a light emitting element comprising a light emitting layer formed between a first electrode and a second electrode and a pixel portion comprising the light emitting element. The entire surface of the pixel portion is covered with the second electrode. An impermeable insulating film is formed in contact with the first electrode of the light emitting element. The edge of the first electrode and the impermeable insulating film are covered with a partition wall. An opening is formed along the circumference of the pixel portion in the partition wall. The opening passes through the partition wall in the thickness direction, and the side wall and the bottom face thereof are covered with the second electrode.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: November 17, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kaoru Tsuchiya, Hideyuki Ebine, Masayuki Sakakura, Takeshi Nishi, Yoshiharu Hirakata
  • Publication number: 20090278121
    Abstract: A system for displaying images includes a thin film transistor array substrate including a substrate with thin film transistors array and at least one light-sensing element containing an amorphous silicon layer formed on the substrate, wherein the light-sensing element has a current flow direction perpendicular to the substrate.
    Type: Application
    Filed: April 21, 2009
    Publication date: November 12, 2009
    Applicant: TPO Displays Corp.
    Inventors: Ramesh Kakkad, Keiichi Sano, Fu-Yuan Hsueh, Chih-Chung Liu, Sheng-Wen Chang
  • Patent number: 7615792
    Abstract: Light-emitting devices capable of preventing separation or alteration of a first electrode to obtain high performance, methods of manufacturing the light-emitting device, and display units are provided. A first electrode as an anode, an insulating film, an organic layer including a light-emitting layer, and a second electrode as a cathode are laminated in this order on a substrate with a planarizing layer as a base layer in between. The first electrode has a structure in which an adhesive layer, a reflective layer and a barrier layer is laminated in this order from the substrate. Alteration of the reflective layer can be prevented by the barrier layer, and the reflective layer can be prevented from being separated from the planarizing layer by the adhesive layer. The first electrode is formed through forming the adhesive layer, the reflective layer and the barrier layer on the planarizing layer, and then patterning them in order from the barrier layer.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: November 10, 2009
    Assignee: Sony Corporation
    Inventors: Seiichi Yokoyama, Koji Hanawa, Takanori Shibasaki, Takashi Hirano
  • Publication number: 20090272978
    Abstract: An image display system and manufacturing method are disclosed. According to the present invention, the image display system comprises a substrate, a switching TFT, a driving TFT, a photo sensor and a capacitor. A buffer layer is formed on a substrate. A separation layer is formed in a first area for forming a switching TFT, but no heat sink layer is formed thereon. A heat sink layer is formed on a second area for forming the driving TFT, the photo sensor and the capacitor, and then, the separation layer is formed thereafter. The present invention can form poly silicon layers with different crystal grain sizes on the first area and on the second area in a single laser crystallization process by utilizing the heat sink phenomenon of ELA with or without the heat sink layer. Therefore, the image display system of the present invention can operate with good luminance uniformity.
    Type: Application
    Filed: April 29, 2009
    Publication date: November 5, 2009
    Applicant: TPO Displays Corp.
    Inventors: Yu-Chung Liu, Te-Yu Lee
  • Patent number: 7611969
    Abstract: A negative dielectric is induced by the application of a dc bias-electric field in aggregates of oxide nano-particles whose surfaces have been specially treated. The magnitude of the dielectric constant and the frequency where the negative dielectric constant occurs can be adjusted. Such material systems have profound implications in novel devices as well as in science development, e.g. unusual wave propagation, secured communication and ultra-high temperature superconductivity.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: November 3, 2009
    Assignee: University of Houston
    Inventors: Ching-Wu Chu, Feng Chen, Yu-Yi Xue, Jason Shulman, Stephen Tsui
  • Publication number: 20090267084
    Abstract: An integrated circuit includes a device stack including: a memory device with a first wireless coupling element, and a semiconductor device with a second wireless coupling element. The first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and the semiconductor device.
    Type: Application
    Filed: April 25, 2008
    Publication date: October 29, 2009
    Applicant: QIMONDA AG
    Inventors: Christoph Bilger, Peter Gregorius, Michael Bruennert, Maurizio Skerlj, Wolfgang Walthes, Johannes Stecker, Hermann Ruckerbauer, Dirk Scheideler, Roland Barth