Abstract: A semiconductor device, such as a dynamic RAM, and method of making it. A number of stacked cell capacitors are placed at a prescribed spacing in an alignment direction on top of a p.sup.- -type silicon substrate (1). Each capacitor has a nearly perpendicular cylindrical lower electrode (cylindrical polysilicon layer (96)), a dielectric film (silicon nitride film (77)), and upper electrode (plate electrode (78) made of polysilicon). The spacing in the alignment direction is smaller than the inner diameter of the lower electrode.

Abstract: A method is provided for use on a DRAM (dynamic random access memory) device for forming a data storage capacitor with a wide electrode area, and thus a high capacitance, for the DRAM device. The high capacitance allows the data storage capacitor to preserve high data retaining capability when the DRAM device is downsized for high integration. The method is characterized in the forming of silicon-nitride based sidewall spacers and polysilicon-based sidewall spacers in openings formed in oxide layers that allows the subsequently formed contact window to be narrowed to a reduced width, thereby preventing the subsequent etching process to damage the nearby polysilicon-based bit lines and gate electrodes due to misalignment in the etching. Moreover, the method allows the resultant data storage capacitor to have a wide electrode area that helps increase the capacitance thereof, thereby allowing the DRAM device to preserve a high and reliable data retaining capability to the data stored therein.

Abstract: The method of fabricating a capacitor of a memory cell is disclosed including the steps of forming a transistor on a semiconductor substrate; sequentially forming an etch stop layer, an insulating layer and a first conductive layer on the semiconductor substrate and the transistor; converting a portion of the first conductive layer into a first porous layer through anodization; patterning a predetermined portion of the first porous layer to form a storage node contact; forming a second conductive layer on the semiconductor substrate and the first porous layer; converting a portion of the second conductive layer into a second porous layer through anodization; patterning a portion of the second porous layer and forming a storage node electrode pattern through an etching process; forming a dielectric layer on an overall surface of the storage node electrode pattern; and forming a third conductive layer on an overall surface of the dielectric layer.

Abstract: A method for forming an electrode for an integrated circuit device includes the steps of forming a first conductive layer on a surface of a microelectronic substrate, and forming a patterned photoresist layer on the first conductive layer. A spacer is formed along sidewalls of the patterned photoresist layer, and the first conductive layer is etched to a predetermined depth less than a thickness of the first conductive layer using the patterned photoresist layer and the spacer as an etch mask thereby defining a hole in the first conductive layer. A protective layer is formed in the hole which covers exposed portions of the first conductive layer, and the patterned photoresist layer is removed. The first conductive layer is then etched using the spacer and the protective layer as an etching mask to form a vertical electrode structure. Related structures are also discussed.

Abstract: A method for forming a capacitor (36) outwardly from a semiconductor substrate (10). Alternating layers of first and second materials (20 and 22) are formed outwardly from a semiconductor substrate. A first set of vias (24) is formed through the layers of first and second materials (20 and 22) to the semiconductor substrate(10). A second set of vias (26) is formed through the layers of first and second materials (20 and 22). Each via in the second set (26) is formed in a location that is adjacent to one of the vias of the first set (24). A trunk (28) of the first plate (34) of the capacitor (36) is formed by selectively depositing a semiconductor material, such as poly-silicon, to fill the first set of vias (24). A set of fins (30) and a dome (32) are formed on the trunk (28) to complete the first plate (34) by removing the alternating layers of first layers (20) and selectively depositing a semiconductor material between the second layers (22).

Abstract: A method for forming a microstructure includes photolithographically forming a vertically extending post on a portion of a surface of a substrate to provide a first structure. A flowable, sacrificial material is deposited over a surface of the first structure. The flowable, sacrificial materially flows off the top surface and sidewall portions of the post onto adjacent portions of the surface of the substrate to provide a second structure. A non-sacrificial material is deposited over a surface of the second structure. The non-sacrificial material is deposited to conform to the surface of the second structure. The non-sacrificial is deposited over the sacrificial material, over the sidewall portions and over the top surface of the post. The deposited sacrificial material is selectively removed while the non-sacrificial material remains to form a third structure with a horizontal member provided by the non-sacrificial material.

Abstract: A method for making a cell capacitor of a semiconductor device such as a dynamic random access memory includes steps for increasing the height of a capacitor electrode. With increased height, the capacitance of the fabricated capacitor is increased while allowing high integration.

Abstract: A semiconductor memory device including a semiconductor substrate having a trench; a dielectric film formed on the substrate; a storage node electrode formed on the dielectric film; a first insulating film formed on the storage node electrode corresponding to the trench; a gate electrode formed on the first insulating film; a second insulating film formed on the gate electrode; a gate insulating film formed on at least one the side of gate electrode; a semiconductor layer formed on the at least one side of the first and second insulating films; and impurity regions formed in the semiconductor layer at the sides of the first and second insulating films.

Abstract: A method and structure are described for making DRAM devices having bit line contacts for memory cells and landing plugs for peripheral devices with a Ti/TiN barrier layer patterned to form bit lines and local interconnections. FETs are formed on the substrate for memory cells and for devices in the peripheral area. A planar first insulating layer is deposited, and contact openings are formed to the devices. A Ti/TiN barrier layer is deposited in the contact openings and a tungsten (W) layer is deposited and selectively etched back to the barrier layer. The barrier layer is then patterned to form bit lines and local interconnections. A second insulating layer is deposited, and capacitor node contact openings are etched and filled with polysilicon to form node contacts on which capacitors are fabricated. A planar third insulating layer is formed and multilevel contact openings are etched to landing plugs.

Abstract: This invention discloses a novel design to fabricate a ring-like capacitor in a semiconductor memory device for increasing the area of the capacitor electrodes. The ring-like conductive structure of the electrode of the capacitor includes a mushroom-shaped member having a flat-headed cap and a stem coupled to the source region of the semiconductor memory device, a solid cylindrical member disposed on the cap of the mushroom-shaped member, and a side-wall spacer being a hollow cylindrical member disposed on the cap of said mushroom-shaped member to increase the area of the capacitor electrodes thereby increasing the capacitance of the capacitor to provide a sufficient capacitance while maintaining high integration in semiconductor memory cells.

Abstract: A method of fabricating single-side corrugated cylindrical capacitor of high density Dynamic Random Access Memory (DRAM) cells. The corrugated capacitor shape is achieved by depositing the thermal chemical vapor deposition (CVD) oxide and the plasma-enhanced CVD (PECVD) oxide alternating layers. Then, the thermal CVD oxide and the PECVD oxide layers are lateral etched by hydrofluoric acid (HF). Because hydrofluoric acid (HF) etches the thermal CVD oxide at a slower rate than etches the PECVD oxide, a cavity (undercut) is formed in each PECVD oxide layer. Therefore, the single-side corrugated shape capacitor surface is created that increases the surface area of the capacitor considerably. The cylindrical capacitor storage node of the DRAM capacitor of this method has much greater surface area so as to increase the capacitance value of the DRAM capacitor, that can achieve high packing density of the integrated circuit devices.

Abstract: A method of producing a semiconductor device includes the steps of (a) preparing a substrate having a semiconductor element formed in a predetermined region of a surface of the substrate, (b) forming a first layer on the substrate, where the first layer is made of silicon oxide including at least one of boron and phosphor, (c) forming a second layer on a surface of the first layer, where the second layer is made of a material selected from a group consisting of silicon nitride and silicon oxide nitride, (d) coating a resist layer on the entire surface of the substrate, (e) exposing and developing a predetermined region of the resist layer using a reticle having a first opening so as to form a second opening in the resist layer, where the first opening has a polygonal shape having n corners respectively having obtuse angles and n is a natural number satisfying n.gtoreq.5, and (f) etching the second and first layers via the second opening.

Abstract: A dynamic random access memory cell (20) with increased capacitance and a method of fabricating the cell, including forming a corrugated post capacitor (21) is provided. The method includes depositing a first film (80) having a first etched selectivity and depositing on the first film a second film (82) having a second etched selectivity. These steps of depositing a first film and a second film are repeated at least once to form a plurality of first film layers (80) alternated with a plurality of second film layers (82). A void (58) is etched in the plurality of first and second film layers. The plurality of first and second layers are selectively etched to form a plurality of undercut areas. Silicon is then selectively deposited in the void, and by overgrowing the selectively deposited silicon a portion of the undercut areas is filled with silicon to form a corrugated post storage electrode. The pluralities of first (80) and second (82) film layers are then removed.

Abstract: A method for forming a contact hole of a capacitor of a DRAM cell is disclosed. The method includes forming a first conductive layer on a semiconductor substrate, and forming a first dielectric layer on the first conductive layer. After patterning to etch the first dielectric layer and the first conductive layer, a second dielectric layer is formed on the semiconductor substrate and the first dielectric layer. Next, the second dielectric layer is anisotropically etched back to form a first spacer on sidewalls of the first dielectric layer and the first conductive layer. A first silicon oxide layer is formed over the semiconductor substrate, the first dielectric layer, the first spacer, followed by patterning to etch the first silicon oxide layer, wherein the first spacer and the first dielectric layer are used for facilitating self-aligned etching.

Abstract: A method of fabricating a semiconductor memory device including a substrate with a transfer transistor formed thereon. A first insulating layer is formed on the substrate, covering the transfer transistor. A first conductive layer is formed, penetrating at least the first insulating layer and electrically coupling to a source/drain region of the transfer transistor. A second insulating layer and a stack layer are formed, and a third insulating layer is formed on the sidewalls of the stack layer. A fourth insulating layer is formed and an opening is made to expose a portion of the first conductive layer. A second conductive layer is formed over the stack layer and second insulating layer and filling the opening. The second conductive layer is defined and the stack layer and the second insulating layer below the stack layer are removed. The first and the second conductive layers are defined to form a storage electrode of the charge storage capacitor.

Abstract: A method for forming an electrode for an integrated circuit device includes the steps of forming a first insulating layer on a semiconductor substrate and forming a conductive mesa on the first insulating layer. The insulating layer has a contact hole therein exposing a portion of the substrate, and the conductive mesa covers and extends into the contact hole so that the conductive mesa is electrically connected to the substrate. A second insulating layer is formed on the first insulating layer wherein the second insulating layer surrounds the conductive mesa and wherein the second insulating layer has a second thickness greater than the first thickness. Accordingly, sidewalls of the second insulating layer are exposed adjacent the conductive mesa. Spacers are formed on the conductive mesa along the sidewalls of the second insulating layer, and the conductive mesa is etched using the second insulating layer and the spacers as an etching mask.

Abstract: A DRAM capacitor structure and its manufacturing include covering a semiconductor substrate with a first conducting layer. A first insulating layer and a second insulating layer are alternately stacked at least once above the first conducting layer to form a multi-layered structure. A contact window opening is formed in the multi-layered structure to expose a source/drain region located above the semiconductor substrate. A pattern is etch-defined on the multi-layered structure, using the first insulating layer as an etching stop layer. Part of the second insulating layer is etched away to form a cross-sectional profile similar to twin towers, with each tower having the form of a vertical T-stack. A second conducting layer covers the multi-layered structure. The first insulating layer and the second insulating layer of the multi-layered structure, as well as the second conducting layer in a top part of the multi-layered structure, are etched away to form a lower electrode.

Abstract: A method of forming a stacked capacitor of a DRAM. A number of doped polysilicon layers and a number of tungsten silicide layers are alternately formed. The doped polysilicon layers and the tungsten silicide layers are then patterned to form a lower electrode of the stacked capacitor. The doped polysilicon layers and the tungsten silicide layers are selectively etched to form a number of lateral trenches at the sidewall of the lower electrode so that the surface area of the lower electrode is increased. A dielectric layer is formed over the exposed surface of the doped polysilicon layers and the tungsten silicide layers. A conductive layer is formed on the dielectric layer as an upper electrode of the stacked capacitor so that the stacked capacitor is completed.

Abstract: A new method for the manufacturing of a capacitor for a DRAM is disclosed herein. The method for manufacturing a capacitor on a semiconductor wafer including the following steps. Firstly, sequentially forming a first dielectric layer, a first conductive layer, a second dielectric layer and a third dielectric layer formed on the semiconductor wafer. Secondary, the third dielectric layer and a portion of the second dielectric layer are etched. The portion of the second dielectric layer is isotropically etched to form a hemispherical cavity. Next, the second dielectric layer, the first conductive layer and the first dielectric layer is etched sequentially to form a hole in contact with a portion of the semiconductor wafer by using the third dielectric layer as a mask. Subsequently, the third dielectric layer is removed when etching the first dielectric layer. Afterword, a second conductive layer is formed on the second dielectric layer and in the hole.

Abstract: A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a storage node electrode, for the STC structure, with increased surface area, resulting from the formation of protruding polysilicon shapes. The protruding polysilicon shapes are obtained using dielectric regions as a mask during a selective, anisotropic RIE procedure, used to define the storage node electrode shape. The dielectric regions are created via oxygen ion implantation into exposed regions of a polysilicon layer. An anneal is used to convert the oxygen implanted polysilicon regions, to dielectric regions.

Abstract: A method for making semicrown stacked capacitors for DRAM devices is achieved. A first insulating layer, a second insulating etch-stop layer, and a high-etch-rate third insulating layer are sequentially formed on a substrate over the memory cell areas having FETs with source/drain areas. Recesses are etched in the third and second insulating layers for bottom electrodes, aligned over device areas. Node contact openings are plasma etched in the first insulating layer exposed in the recesses to one of each source/drain area. A first polysilicon layer is deposited to form node contacts and the bottom electrodes. A high-etch-rate fourth insulating layer is used to fill the recesses. The fourth insulating layer and the first polysilicon layer are etched or chem/mech polished back to form the array of bottom electrodes having oxide plugs. The plugs and third insulating layer are wet etched to the etch-stop layer to form the semicrown bottom electrodes.

Abstract: DRAM cells having self-aligned node-contacts-to-bit lines with tungsten landing plug contacts for reduced aspect ratio contact openings and via holes is achieved. A planar insulating layer is formed, and openings for bit line contacts, node contacts, and landing plugs on the chip periphery are concurrently etched. A W/TiN layer is patterned to form bit lines, capacitor node, and multilevel contact landing plugs on the DRAM chip. The landing plugs reduce the aspect ratio of the openings for the multilevel contacts. Bit line sidewall spacers are formed, and a BPSG is deposited and planarized. Capacitor openings are etched in the BPSG aligned over the node contacts. A conformal conducting layer is deposited, and a polymer is deposited and planarized. The polymer and the conducting layer are polished back to complete the capacitor bottom electrodes in the capacitor openings. The polymer is removed.

Abstract: DRAM devices are made having self-aligned tungsten landing plug contacts to gate electrodes for capacitor-under-bit line (CUB) for reduced aspect ratio contact openings. A planar insulating layer is formed, and openings for bit line contacts, node contacts, and contacts on the chip periphery are concurrently etched for metal landing plugs. A TiN/Ti/N.sup.+ polysilicon multilayer is deposited and annealed to form low contact resistance to the substrate A tungsten (W) layer is then deposited and etched back to form W landing plug contacts in the contact openings, which reduce the aspect ratio for the multilevel contacts. A Si.sub.3 N.sub.4 etch-stop layer and a BPSG are deposited and planarized. Capacitor openings are etched in the BPSG aligned over the node contacts. A conformal conducting layer and a planarized polymer are deposited and polished back to complete the bottom electrodes in the capacitor openings.

Abstract: A capacitor construction includes, a) first and second electrically conductive capacitor plates separated by an intervening capacitor dielectric layer, the first capacitor plate comprising first and second container members, the second container member being received inside of the first container member, the first and second container members comprising a respective ring portion and a respective base portion; and b) a pedestal disk positioned elevationally intermediate the first container member base and the second container member base to space and support the second container member relative to the first container member. The structure is preferably produced by using a series of alternating first and second layers of semiconductive material provided over a molding layer within a container contact opening therein. One of the first and second layers has an average conductivity enhancing dopant concentration of greater than about 5.times.10.sup.19 ions/cm.sup.

Abstract: A structure and manufacturing method for DRAM capacitors includes providing a semiconductor substrate with a MOS transistor having a gate and source/drain regions formed thereon. A first insulating layer covers the semiconductor substrate. A multi-layered stack, with at least one pair of an alternately deposited second insulating layer followed by a third insulating layer, is formed above the first insulating layer. An opening is formed through the multi-layered structure and the first insulating layer exposing the source/drain region. Then, a plurality of trenches are formed on the sidewalls of the opening. A second conducting layer is formed over the exposed surfaces of the aforementioned layers. A pattern is defined on the second conducting layer so as to form a lower electrode structure. A dielectric layer is formed over the lower electrode layer. A third conducting layer is formed over the dielectric layer, and a pattern is defined on the third conducting layer to form the upper electrode structure.

Abstract: A method for fabricating capacitors of a DRAM by employing the liquid-phase deposition. Since the working temperature required for performing liquid-phase deposition is low, selective deposition can be performed on the area not covered by photoresist with the presence of the photoresist layer. The foregoing method comprises: filling up the contact hole with photoresist, and keeping up coating photoresist upward and horizontally; selectively depositing oxide on the area, that is not coated with photoresist, by utilizing the liquid-phase deposition process; removing the photoresist for forming an opening which forms the profile of the lower electrode of a capacitor; forming a conductive layer on the inner walls of the opening, and having the contact hole filled as well to form the lower electrode.

Abstract: A method for manufacturing a DRAM capacitor whose lower electrode has a greater surface area, and is thereby able to increase the capacitance of the capacitor. The method comprises the steps of providing a substrate with a target conductive region and then depositing a first dielectric layer, an etching stop layer and a second dielectric layer sequentially over the target conductive region and the substrate. Next, a deep opening leading to the target conductive region is etched through the various layers, and a first conductive material is deposited to fill the deep opening completely. Thereafter, the second dielectric layer is patterned and etched to form a shallow opening exposing a portion of the first conductive layer and the etching stop layer. Then, a second conductive material is deposited into the exposed first conductive layer and etching stop layer.

Abstract: An exemplary embodiment of the present invention includes a memory cell in a semiconductor device, comprising a substantially vertical-gated, access transistor having its gate electrode surrounding a pillar portion of a silicon material, a first source/drain electrode in an upper portion of the pillar portion and a second source/drain electrode in a silicon material extending substantially horizontally about the base of the pillar portion; and a storage capacitor having its storage electrode connecting to the first source/drain electrode. The structure of the storage capacitor may configured as desired which includes a stacked capacitor structure or a cylindrical capacitor structure.

Abstract: The present invention discloses a method for making low-topography buried capacitor including the steps of first depositing oxide layers, and then forming a small pre-contact hole by a dry etch method and a large contact hole by a wet etch method while using silicon nitride caps and sidewall spacers previously deposited on the word lines and on the bit lines as etch stop layers. A buried capacitor that has significantly improved topography can be fabricated in a semiconductor device.

Abstract: An improved semiconductor device fabrication method capable of improving the insulation characteristic between neighboring electrodes, which includes the steps of a first step which coats a conductive material on an active region of a semiconductor substrate having an active region and a non-active region divided by a field oxide film and forms a first conductive layer; a second step which deposits a first cap layer and a second cap layer in order so as to insulate between the first conductive layer and an upper layer and etches the same mask; a third step which provides ion on the semiconductor substrate with a mask of the thusly etched first conductive layer, a first cap layer, and a second cap layer and forms a source/drain region; a fourth step which forms a side wall spacer at the side surface of the first conductive layer, the first cap layer and the second cap layer and deposits in order a protection film and a contact oxide film at the front surface of the layer made thereby; a fifth step which forms

Abstract: A stacked capacitor of a DRAM cell has an increased storage electrode without increasing the total area and fabrication complexity of the DRAM cell. By disposing the storage electrode of a memory capacitor on an especially made rugged stacked oxide layer, the area of the storage electrode is enlarged and thus provides the higher capacitance. Then, by removing the rugged stacked oxide layer to expose the rugged surface of the storage electrode, the capacitance of a memory capacitor is additionally increased after covering the whole rugged surface of a of the storage electrode with a dielectric film.

Abstract: A structure of a capacitor in a DRAM includes: A dielectric layer with a contact window for later connecting use is formed on a substrate. Then, a first-conductive layer is formed over the dielectric and is coupled to either the source or the drain of a TFET through the contact window. Subsequently, a number of insulating layers and second-conductive layers are superposed alternatively together to form a stacked layer. By using the space occupied by the insulating layers, a number of third-conductive layers replacing the inner portion of the insulating layers are formed in between the second-conductive layers. After removing the insulating layers between the second-conductive layers, a structure of a horn-like in a sectional view is formed. The first-conductive layer, the second-conductive layers and the third-conductive layers are coupled together to act as a lower electrode of the capacitor. Then, a dielectric thin film is formed over the lower electrode.

Abstract: A method for fabricating an electrode structure of an integrated circuit device comprises the following steps. Initially, a conductive layer is formed on a substrate. A photoresist layer is formed on the conductive layer, wherein said photoresist layer includes a hole exposing a portion of said conductive layer. A portion of the conductive layer is then etched to a predetermined thickness that is less than a thickness of the conductive layer using said photoresist layer as an etching mask. The hole in the photoresist layer is enlarged by removing a portion of the photoresist layer, thereby exposing a surface portion of the conductive layer outside the etched portion of the conductive layer. An insulating layer is then formed on the surface portion of the conductive layer and the etched portion of the first conductive layer. The insulating layer is used as an etching mask for etching the conductive layer to form an electrode structure.

Abstract: A method for creating stacked capacitor structures, with increased surface area, obtained using storage node electrode structures comprised of an HSG silicon layer, on a heavily doped amorphous silicon layer, both overlying polysilicon storage node shapes, has been developed. A dilute hydrofluoric acid pre-clean procedure is used prior to depositing a heavily doped amorphous silicon layer, on underlying polysilicon storage node shapes. An overlying second amorphous silicon layer is in situ deposited, in the same furnace used for the prior deposition of heavily doped amorphous silicon layer, followed by an in situ seeding/annealing procedure, converting the second amorphous silicon layer to an HSG silicon layer. This invention features the use of the acid pre-clean, to improve adhesion of the heavily doped amorphous silicon layer, to underlying polysilicon storage node shapes.

Abstract: This invention discloses a novel design for increasing the surface area of a stacked capacitor used in DRAM devices. The upper and lower plates of the capacitor comprises of several concave structures. The concave structures are first produces on an LS-SOG layer using focused ion beam lithography, which is then mapped to the lower plate of the capacitor. A dielectric layer is deposited, after which an upper plate is formed. The concave structures increases the plate area, thereby increasing charge storage capacity.

Abstract: A method for fabricating electrodes of a capacitor over a semiconductor substrate is disclosed. The method includes the steps of: forming a base insulating layer over the semiconductor substrate; forming a stacked layer, including an insulating layer and a mask layer, over the base insulating layer; defining the stacked layer to form an opening to the base insulating layer; forming a first conducting layer over the stacked layer; forming a spacer on the sidewall of the first conducting layer in the opening; etching the bottom of the opening by using the mask layer and the spacer as a mask to expose a portion of the semiconductor substrate; forming a second conducting layer in the opening to electrically connect the exposed semiconductor substrate; and removing the spacer to leave the first and the second conducting layers as a capacitor electrode.

Abstract: A lower electrode of a capacitor is formed by a cylindrical conductive film and a pillar shaped conductive film disposed coaxially within the cylindrical conductive film. Consequently, in this capacitor, even if a plane area of the lower electrode is so small that double cylinder type cannot be realized, opposing area of the lower electrode and upper electrode is larger as compared to a structure in which the lower electrode is of single cylinder type. This invention proposes such a capacitor and a method of manufacturing thereof. As a result, it is possible to increase electric storage capacity if the plane area of the capacitor is the same and further miniaturize the capacitor if the electric storage capacity is the same.

Abstract: A method of forming a capacitor includes, a) providing a series of alternating first and second layers of semiconductive material over a node location, a first of the first and second layers having an average conductivity enhancing dopant concentration of greater than about 5.times.10.sup.19 ions/cm.sup.3, a second of the first and second layers having an average conductivity enhancing dopant concentration from 0 ions/cm.sup.3 to about 5.times.10.sup.19 ions/cm.sup.

Abstract: A structure and a method to increase the capacitance of a DRAM capacitor by forming a capacitor electrode with cellular voids to add surface area. According to the method: a transfer transistor with a gate electrode and source-drain electrode regions is formed on a semiconductor substrate. An insulating layer is formed on the semiconductor substrate and the transfer transistor, and the insulating layer is etched to form a contact void for exposing the surface of one of the source-drain electrode areas as a contact. A first conductive layer is formed on the insulating layer and is coupled to the contact through the contact void. On the first conductive layer, at least one middle insulating layer and one middle conductive layer are formed alternately to construct a multiple layer structure. Within the middle insulating layer(s), intercommunicating voids are formed through which the middle conductive layer is coupled to the first conductive layer is coupled to the first conductive layer.

Abstract: A method for fabricating a crown-shaped DRAM capacitor comprising the steps of providing a substrate having transistors already formed thereon, then sequentially forming a first insulating layer and a second insulating layer over the substrate and the transistors. The second insulating layer has an upper opening that exposes portions of the first insulating layer, and the first insulating layer has a contact opening that exposes a source/drain region in the substrate. Thereafter, a first conducting layer is formed over the second insulating layer and the exposed first insulating layer. Then, spacers are formed on the sidewalls of the first conducting layer. Next, a second conducting layer is deposited over the first conducting layer and the spacers. Subsequently, the second conducting layer is etched to form conducting pillars next to the spacers. Finally, the spacers and the second insulating layer are removed to form a crown-shaped lower electrode for the capacitor.

Abstract: A method for fabricating a semiconductor memory device with a tree-type capacitor having increased area for reliable storage of electrical charges representative of data thereon. The tree-type capacitor includes a storage electrode having a trunk-like conductive layer coupled to at least one branch-like conductive layer, which can be structured in various shapes that allow the branch-like conductive layer to have increased surface area. The branch-like conductive layers are formed by successively depositing at least one insulating layer and at least one conductive layer over the substrate such that the conductive layer makes a series of twists and turns, defining the shape of the branch-like conductive layer. The surface of the built-up wafer is removed until the conductive layer is divided into a number of segments. A contact hole is formed through the conductive layer to a drain/source region of a transistor in the device, and is filled with a conductive layer, forming the trunk-like layer.

Abstract: A method and structure is described for a DRAM cell having a double wall tub shaped capacitor. The structure of the capacitor has two embodiments: a double wall tub shaped capacitor and a double wall cup shaped capacitor. In a first embodiment for the tub shaped capacitor, the method comprises using two masks to form a tub shaped hole partial through an insulating layer and a concentric contact hole over the source. A polysilicon layer is formed over the insulating layer. Oxide spacers are formed on the sidewalls of the tub shaped hole. The polysilicon layer is patterned to separate adjacent electrodes. Next, a polysilicon inner wall is formed on the spacer sidewalls. The oxide spacers are then removed. The dielectric and top electrode are formed next thus completing the double wall tub shaped capacitor. The second embodiment for forming the cup shaped capacitor comprises forming an insulating layer the substrate surface and forming a photoresist layer with an opening over a source region.

Abstract: A method is provided for use on a DRAM (dynamic random access memory) device for forming a data storage capacitor with a wide electrode area, and thus a high capacitance, for the DRAM device. The high capacitance allows the data storage capacitor to preserve high data retaining capability when the DRAM device is downsized for high integration. The method is characterized in the forming of silicon-nitride based sidewall spacers in openings formed in oxide layers that allows the subsequently formed contact window to be formed with a reduced width, thereby preventing the subsequent etching process to damage the nearby polysilicon-based bit lines and gate electrodes due to misalignment in the etching. Moreover, the method allows the resultant data storage capacitor to have a wide electrode area that helps increase the capacitance thereof, thereby allowing the DRAM device to preserve a high and reliable data retaining capability to the data stored therein.

Abstract: A method for forming a capacitor of a semiconductor device, by which a three dimensional structure of a storage electrode occupying small space but having a great surface area is formed between word lines or bit lines. According to the method, an additional planarization layer is not formed on the word lines or the bit lines, so as to make the three dimensional structure high. Thus, the storage electrode comes to have an enlarged surface area enough to allow the formation of a capacitor with a sufficient capacitance for the high integration of semiconductor devices and thus to improve the properties and the reliability of semiconductor devices.

Abstract: An array of DRAM cells having double-crown capacitors with a center post to increase capacitance is achieved. A planar insulating layer is formed over FETs in an array of cells. Node contact openings are etched to each FET. A first polysilicon layer is deposited to fill the node contact openings and provide a polysilicon planar surface. A thick insulating layer is deposited on the first polysilicon layer, and patterned leaving portions having essentially vertical sidewalls over the contact openings. A conformal second polysilicon layer is deposited and etched back to form first polysilicon spacers and the thick insulating layer is removed. A conformal doped silicon oxide layer is deposited over the first polysilicon spacers and etched back to form inner and outer insulating sidewall spacers.

Abstract: A method of fabricating a DRAM which includes a capacitor and a metal oxide semiconductor field effect transistor. A field oxide layer is formed on a silicon substrate. A gate oxide layer is formed on the silicon substrate. A first polysilicon layer is deposited on the gate oxide layer. An insulator is deposited on the first polysilicon layer. A first silicon nitride layer is deposited on the insulator. The first silicon nitride layer, the insulator, the first polysilicon layer and the gate oxide layer are processed to form a gate electrode. First spacers are formed between the insulator and the substrate on sidewall on opposite sides of the gate electrode. Source-drain regions are formed on the substrate on the opposite sides of the gate electrode. A contact window is formed on the drain electrode. Second spacers are formed on surfaces of the first spacers which are adjacent to the contact window.

Abstract: An etching process is used to etch the polysilicon layer. Then, Polymers are formed on the polysilicon layer after an ash step is performed. An organic layer is formed on the surface of the polysilicon layer, and on the polymers. An anisotropically etch is carried out to etch the organic layer, thereby forming organic side wall spacers on the side walls of the polysilicon layer. The etching is continuously performed to etch the polysilicon layer using the polymers and organic side wall spacers as masks. Next, an ash and a RCA clean procedure are performed to remove the residual polymers and the organic layer. A dielectric layer is then deposited on the surface of the polysilicon. A conductive layer is deposited over the dielectric layer.

Abstract: The present invention is a method of manufacturing a high density capacitors for use in semiconductor memories. High etching selectivity between BPSG (borophososilicate glass) and CVD-oxide (chemical vapor deposition oxide) is used to fabricate a crown shape capacitor with a plurality of horizontal fins. First, a first polysilicon layer is formed on a semiconductor substrate. A composition layer consists of BPSG and silicon oxide formed on a the first polysilicon layer. Then a contact hole is formed in the composition layer and the first polysilicon layer. A highly selective etching is then used to etch the BPSG sublayers of the composition layer. Next, a second polysilicon layer is formed in the contact hole and the composition layer. Then photolithgraphy and etching process is used to etch the second polysilicon layer, composition layer and first polysilicon layer. A third polysilicon layer is subsequently formed on the second polysilicon layer.

Abstract: A method of forming DRAMs that utilizes cap layers and spacers to surround the gate and bit line so that the necessary contact openings in DRAM can be formed in two self-aligned contact opening processing operations. Furthermore, the DRAM capacitor is formed by alternately depositing two types of insulating layers, one over the other, with each insulating layer having a different etching rate, and then performing an etching operation. Therefore, a deer antler-shaped mold is formed that can ultimately be used to fabricate a storage electrode with a large surface area.

Abstract: A method for fabricating a capacitor on a semiconductor substrate is disclosed. The method includes forming a first TEOS layer, a polysilicon layer and a second TEOS layer over the semiconductor substrate. A window is formed through the second TEOS layer to expose a portion of the polysilicon surface. Defined by a first dielectric spacer in the window, the polysilicon layer is etched to expose a portion of the first TEOS layer. The second TEOS layer and the exposed portion of the first TEOS layer are then removed to form a trench extending down to the semiconductor substrate. A polysilicon plug is filled in the trench and a first polysilicon spacer is formed around the first dielectric spacer. A lower electrode including the polysilicon plug, the polysilicon layer and the first polysilicon spacer is therefore formed by removing the first dielectric spacer. Moreover, a dielectric layer and an upper electrode are formed over the lower electrode.