Abstract: A method of forming a capacitor for a DRAM includes the steps of: forming an insulating layer with a contact hole on a substrate; forming a first conductive layer on the insulating layer and in the contact hole; forming a temporary layer pattern on a portion of the first conductive layer corresponding to the contact hole; forming a second conductive layer on the first conductive layer and on the temporary layer pattern; selectively implanting oxygen ions into the first and second conductive layers except a portion of the second conductive layer corresponding to a side face of the temporary layer pattern; heat treating so as to convert the oxygen-ion-implanted first and second conductive layer portions into an oxide; removing the oxide and temporary layer pattern; forming a dielectric layer on the surface of the first and second conductive layers; and forming a third conductive layer on the dielectric layer.

Abstract: A method for fabricating a capacitor for a semiconductor device includes the steps of depositing an insulating layer on a substrate, selectively removing the insulating layer and forming a contact hole, forming a first electrode in the contact hole, removing the insulating layer to expose a portion of the first electrode, and sequentially forming a dielectric layer and a second electrode on the exposed portion of the first electrode.

Abstract: A capacitor in a semiconductor device having a dielectric film formed of high dielectric material and a manufacturing method therefor are provided. The capacitor consists of electrodes including a dielectric film and an amorphous SiC layer. Thus, the diffusion of oxygen atoms through a grain boundary into an underlayer and the formation of an oxide layer on the surface of the SiC layer can both be prevented, providing for a highly reliable capacitor electrode and an equivalent oxide thickness which is no thicker than required.

Abstract: Methods of producing ferroelectric capacitors where the electrodes are formed in a contact hole. These methods include the steps of forming an insulating layer on an integrated circuit substrate. A contact hole is then formed through the insulating layer layer to expose a region of the integrated circuit substrate and to define a storage node pattern. A layer of oxidation-resistant conductive material is formed in the contact hole and the insulating layer removed to define a first storage electrode by exposing the layer of oxidation-resistant conductive material. A ferroelectric layer is then formed on the first storage electrode and a second storage electrode is formed on the ferroelectric layer opposite the first storage electrode.

Abstract: A method of fabricating double-side corrugated cylindrical capacitor of high density Dynamic Random Access Memory (DRAM) cells. The corrugated capacitor shape is achieved by depositing the thermal chemical vapor deposition (CVD) oxide and the plasma-enhanced CVD (PECVD) oxide alternating layers. Then, the thermal CVD oxide and the PECVD oxide layers are vertically etched to form two trenches followed by laterally etched by hydrofluoric acid (HF). Because hydrofluoric acid (HF) etches the thermal CVD oxide at a slower rate than etches the PECVD oxide, a cavity is formed in each PECVD oxide layer along the trenches. Finally, polysilicon layer is deposited filling into the trenches. Therefore, the double-side corrugated shape capacitor surface is created that increases the surface area of the capacitor considerably.

Abstract: The present invention provides a method of manufacturing a capacitor for a high density memory device. The capacitor has a bottom electrode 70 having cylindrical walls 54A more closely spaced than the minimum photolithography dimensions. The method begins by providing a first conductive layer 30 that contacts the substrate. A polyoxide layer 36A is used to form an opening over the first conductive layer 30 that defines a dielectric stud 50. An important feature is the polyoxide layer 36A makes the opening 38A smaller than the photolithographic limits. Cylindrical walls 54A are formed on the sidewalls of the dielectric stud 50. Subsequent etches are used to form the bottom electrode 54A, 30B (70). The electrode of the present invention is smaller than the conventional minimum photo ground rules and the method is cost effective and highly manufacturable.

Abstract: A trenched stack-capacitor applied in a memory unit is formed through a simple process of manufacturing a stack capacitor with high density.

Abstract: Used nearer to a MOS transistor (25, 29(1), 29(2)) together with another capacitor electrode (39) with a dielectric film (37) interposed for use in a DRAM, a capacitor electrode is manufactured to include a conductor pole (53) and a tray-shaped conductor layer (55) which is held by the conductor pole and to include a plate portion (57) extended perpendicular to a pole axis and having a plate periphery and a peripheral portion (59) extended parallel to the pole axis from the plate periphery towards a pole end. Preferably, the tray-shaped conductor layer is held by the pole on a plurality of levels. A planar conductor layer may additionally be held at the pole end perpendicular to the pole axis. Word (41) and bit (49) lines are embedded in an insulator layer (43, 51) for the capacitor and the transistor.

Abstract: An improved method for forming a dynamic random access memory (DRAM) cell capacitor with increased capacitance is disclosed. The method includes forming a planarized dielectric layer on a semiconductor substrate. Then a minimum dimension trench is formed to expose the source region of the DRAM cell MOSFET, thereby forming the node contact for the bottom storage node of the DRAM cell capacitor. A thick doped polysilicon layer is then formed over the dielectric layer, filling the trench. A nitride layer is formed on the dielectric layer. Thereafter, a photoresist layer is formed on the silicon nitride layer and patterned to form a minimum dimension mask aligned with the polysilicon filled trench in the dielectric layer. The photoresist mask is then etched, causing the photoresist mask to be narrower than the minimum dimension. The silicon nitride layer is then anisotropically etched to expose the polysilicon layer. After stripping the photoresist mask, a silicon nitride mask is formed on the polysilicon layer.

Abstract: A stacked capacitor DRAM is formed on a substrate having a pass transistor and a wiring line covered by a layer of insulator. A self-aligned contact process is used to expose the surface of one of the source/drain regions of the pass transistor and three layer stack is deposited over the layer of insulator. The lowest, first layer is polysilicon in contact with the one source/drain region of the pass transistor, the second layer is silicon oxide, and the third, topmost layer of the stack is either silicon nitride or polysilicon. A mask is formed over the third layer to laterally define the capacitor structure and then the third and second layers are etched down to the surface of the first, polysilicon layer. Differential etching is then performed to laterally etch the second layer without etching the first or third layers. The mask is removed and hemispherical grained silicon (HSG-Si) is grown over all of the exposed surfaces of the device.

Abstract: A method for manufacturing an array of stacked capacitors with increased capacitance on a dynamic random access memory (DRAM) device was achieved using chemical mechanical polishing (CMP). The invention utilizes CMP to planarize a polysilicon layer in which the capacitor bottom electrodes are formed using two masking steps and a self-aligning etch-back step to form a very high density array of capacitors for DRAM devices. The method involves depositing and then planarizing a thick first polysilicon layer by CMP over a partially completed DRAM cell. A patterned silicon oxide layer with portions aligned over the node contact openings of the pass transistors (FETs) is formed. Silicon nitride sidewall spacers are formed on the vertical sidewalls of the silicon oxide and a thermal oxide is grown on the first polysilicon layer. After selectively removing the nitride spacers, the polysilicon is etched to form deep trenches with inner sidewalls for the bottom electrodes.

Abstract: A method of manufacturing a capacitor for use in semiconductor memories is disclosed. The present invention includes forming a silicon nitride layer as an oxidation mask to oxidize a polysilicon layer. Then, a anisotropic etching is used to etch the oxidized polysilicon layer. Next, a second polysilicon layer is formed on the resulting structure. Then, an anisotropically etching is used to etch the second polysilicon layer for forming side wall spacers. Then, the oxidized polysilicon layer is removed to leave the bottom storage node of a capacitor is formed having increased area.

Abstract: Polysilicon or amorphous silicon electrodes are selectively texturized with respect to neighboring dielectric surfaces. Selectivity of texturizing is partially accomplished by exploiting differences in seed incubation time on silicon as compared to neighboring surfaces. The texturizing process is made substantially completely selective by a texturizing post-etch, which selectively removes parasitic deposits from surfaces adjacent to the silicon electrodes. Selectively texturized electrodes represent a significant improvement in DRAM process integration.

Abstract: The present invention provides two main embodiments of a method of manufacturing a high capacitance cylindrical capacitor for a DRAM. The capacitor of the invention has a high capacitance because of the addition area 48C under the upper cylinder 48A and the hemispherical grain (HSG) layer 49 72. The first embodiment of the invention forms a HSG layer 49 over the inside of the cylindrical electrode 48A. The second embodiment forms a HSG layer 72 over both the inside and outside of the cylindrical electrode 70A. The invention also features four preferred methods for forming the first and second openings 30 34 in the second insulating layer. The first and second preferred methods use two optical masks to define the openings 30 34. The third and fourth methods use one photoresist layer 100 with 3 different thickness areas and a three step etch to define the first and second openings 30 34.

Abstract: An improved method for forming a dynamic random access memory (DRAM) capacitor includes forming a first dielectric layer on a substrate. The first dielectric layer is patterned and anisotropically etched to form a trench that defines a storage node area. A doped polysilicon layer is formed on the first dielectric layer and filling the trench. Next, a nitride layer is formed on the doped polysilicon layer and a dielectric stack is then formed over the nitride layer. The dielectric stack includes alternating layers of a second dielectric material and a third dielectric material, each dielectric material having a different etch rate. The dielectric stack is patterned and anisotropically etched to form a laminated pillar. The pillar is then isotropically etched to form recessed cavities in a sidewall of the pillar. Portions of the nitride layer are then removed using the pillar as a mask, and a doped polysilicon layer is conformally formed over the pillar so as to fill the recessed cavities.

Abstract: A method is disclosed for a manufacturing process of forming a high capacitance capacitor in a DRAM cell. A semiconductor substrate having a switching MOS transistor comprising a word line and a bit line is provided. A first dielectric is deposited over the substrate and planarized. Contact hole is etched in the first dielectric until the substrate is exposed. A doped first polysilicon is blanket deposited over the substrate filling the holes. A trench is next formed partially in the first polysilicon layer over the contact hole but not reaching the hole. A second dielectric material is deposited over the substrate filling the trench. The dielectric layer is then plasma etched back so as to form a dielectric plug in the trench. Using now the dielectric plug as a mask, the first polysilicon layer is then removed to a predetermined thickness by means of reactive ion etch. A second polysilicon is next formed conformally over the first polysilicon layer covering the dielectric plug.

Abstract: Semiconductor memory device and method for fabricating the same for increasing the capacity of a capacitor by minimizing the capacitor area lost for a storage contact.

Abstract: The invention provides a method of manufacturing a cylindrical capacitor for a DRAM that has a pin shaped plug 42 that increases the photo alignment tolerances between a pin plug 42 and a cylindrical top crown 50A. The invention provides a capacitor structure with a pin shaped plug hole 40 (40A 40B) that has a wide upper hemispherical plug hole 40B and a narrower cylindrical lower plug hole 40A. There are two embodiments to forming the pin plug hole 40. In the first embodiment, (1) an isotropic etch forms the wide upper hemispherical plug hole 40B followed by, (2) an anisotropic etch forms the narrower cylindrical lower plug hole 40B. In the second embodiment, the first insulating layer 30 is composed of an upper layer 30B (with a fast wet etch rate) and a lower layer 30A (with a slow wet etch rate). Then the layer 30 is etched by a wet and a dry etch (in either order) to form the pin plug opening 30.

Abstract: Capacitors, in particular stacked capacitors for a dynamic memory cell configuration are manufactured by first forming a sequence of layers, which include layers made of a first conductive material alternating with layers made of a second material. The second material can be selectively etched with respect to the first material. Layered structures are formed from the sequence of layers, with the flanks of the layered structures each having a conductive support structure. The layered structures are formed with openings, such as gaps, in which the surface of the layers is exposed. The layers made of the second material are selectively removed with respect to the layers made of the first material. The exposed surface of the layers made of the first material and of the support structure are provided with a capacitor dielectric, onto which a counter-electrode is placed. The capacitor is made by etching p.sup.- -doped polysilicon that is selective to p.sup.+ -doped polysilicon.

Abstract: Fabricating a semiconductor memory device on a substrate having a transfer transistor formed thereon includes forming a first insulating layer over the transfer transistor, an etching protection layer over the first insulating layer, a second insulating layer over the etching protection layer, and a stacked layer over the second insulating layer, wherein the stacked layer has a recess therein disposed above a source/drain region of the transistor and exposing a portion of the second insulating layer. A third insulating layer is formed around the periphery of the recess and a fourth insulating layer is formed to fill the recess. Then the process includes removing the third insulating layer and the fourth insulating layer from the recess, and a portion of the second insulating layer directly below the third insulating layer to form a cavity which does not expose the etching protection layer. A first conductive layer is then formed to fill the recess and the cavity, followed by removing the stacked layer.

Abstract: The present invention provides a method of manufacturing a cylindrical capacitor which begins by forming an insulating layer and a passivation layer composed of silicon nitride is over a substrate. A plug contact opening is formed through the passivation layer and the insulating layer. The insulating layer in the plug contact opening is selectively wet etched. The wet etching forms an overhanging portion of the passivation layer. A bottom plug is formed in the contact opening. A first dielectric layer having a cylindrical electrode opening is formed over passivation layer and the plug is exposed. A second polysilicon layer is formed over the first dielectric layer and in the cylindrical openings. A second dielectric layer is formed over the second polysilicon layer and in the cylindrical electrode opening. The second dielectric layer and the second polysilicon layer are planarized.

Abstract: A stacked layer is formed over a sunstrate. The stacked layer consists of at least three, preferably four, layers with different etching rates under a certain etchant with one another. An etching is used to etch the stacked layer to define a storage node using a photoresist as a mask. Then, a selectively etching is performed to etch the stacked layer. A polysilicon layer is than conformily formed along the surface of the stacked layer. Then, an anisotropically etching is carried out to etch the polysilicon layer. The polysilicon layer on the top of the stacked layer is completely removed to expose the top layer of the stacked layer. Next, the stacked layer is removed to form two stair-like structures. A dielectric layer is deposited along the surface of stair-like structures. Finally, a conductive layer is deposited over the dielectric layer.

Abstract: A method for manufacturing a double walled cylindrical stacked capacitor for a DRAM using only one photo mask is provided. An insulating layer having a contact opening is formed over a transistor. A first conductive layer is then formed over the insulating layer. The first conductive layer is patterned forming a central spine over the contact opening and portions of the first conductive layer are left covering the insulation layer. Dielectric spacers are formed on the sidewall of the central spine. The remaining portions of the first conductive layer over the first insulating layer are removed and upper portions of the central spine are removed forming a conductive base. Inner and outer conductive walls are formed on the sidewalls of the dielectric spacers thereby forming a double walled bottom electrode. The dielectric spacers are removed. A capacitor dielectric layer and a top electrode are formed over the bottom electrode forming the capacitor.

Abstract: A fabricating method of a dynamic random access memory is provided. The characteristic of the method is the formation of a dielectric layer to protect a polysilicon layer of hemispheric grains, and thus, the slurry residue from chemical-mechanical polishing process is avoided. In addition, the dielectric layer and the oxide layer can be removed by the same step of wet etching without an additional process. The exposure limitation is not restricted by the shrinkage of the devices. Therefore, the polysilicon layer of hemispherical grains can be removed precisely as expected.

Abstract: A method is described using a single photoresist mask to make a double-crown-shaped DRAM capacitor self-aligned to the capacitor node contact. After forming the DRAM FETs and the bit lines, a planar BPSG layer, a first polysilicon layer, and a CVD oxide layer are deposited. A node contact photoresist mask is used to form first openings in the CVD oxide in which silicon nitride sidewall spacers are formed. A smaller second opening is etched in the first opening to form node contact openings to the DRAM FET source/drain areas. A conformal second polysilicon layer is deposited to form node contacts in the second openings and over the free-standing sidewall spacers. A planar spin-on glass layer is then used as a self-aligned mask to etch back to expose the second polysilicon layer, which is then removed from the top of the sidewall spacers. After removing the spin-on glass an anisotropic etch is used to form the double-crown-shaped capacitor bottom electrodes self-aligned to the node contacts.

Abstract: A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a lower, or storage node electrode, for the STC structure, consisting of a flat, polysilicon plug, contacting an underlying transistor region, and of an upper polysilicon shape, comprised of polysilicon columns, extending between about 2500 to 6000 Angstroms, above the top surface of the flat, polysilicon plug. The flat, polysilicon plug is formed via creation of a capacitor contact hole, in an insulator layer, followed by polysilicon deposition, and RIE etch back, creating the flat, polysilicon plug, recessed in a lower portion of the capacitor contact hole. Another polysilicon deposition, and anisotropic RIE procedure, results in the formation of polysilicon columns, on the sides of the upper portion of the capacitor contact hole.

Abstract: A process for fabricating a large surface area, storage node structure, for a DRAM device, has been developed. The storage node structure is comprised of a lower level polysilicon structure, exhibiting a "twin hammer tree" shape, and connected to an upper polysilicon level, exhibiting a "branch" type shape. The fabrication process used to create this storage node structure, features various deposition procedures, used for insulator and polysilicon layers, and various anisotropic and isotropic, dry etch procedures, as well as wet etch procedures, used for creation of the "twin hammer tree" shaped structure.

Abstract: A method for manufacturing an array of stacked capacitors with increased capacitance on a dynamic random access memory (DRAM) device was achieved. The invention uses a thermal oxidation and anisotropic plasma etch to form sidewall spacers in a recess or trench in a first polysilicon layer over the capacitor node contacts to the FETs. The recesses within the sidewall spacers are then filled with a second polysilicon layer and chem/mech polished back to form studs. The sidewall spacers are then selectively removed by a wet etch and a patterned second photoresist layer is used to pattern the first polysilicon layer into an array of capacitor bottom electrodes with vertical portions that increase the surface area. An interelectrode dielectric layer is formed on the bottom electrodes and a third polysilicon layer is deposited and patterned to form the top electrodes and to complete the array of stacked capacitors on the DRAM device.

Abstract: A process for fabricating stacked capacitor, DRAM devices, wherein the surface area of the capacitor is significantly increased as a result of sidewall processes, has been developed. The process is highlighted by deposition of polysilicon, to be used for the lower electrode of the stacked capacitor structure, on specific underlying insulator shapes. As a result of the severe underlying insulator topography, a significant portion of the polysilicon forms on the sides of the underlying insulator shapes, creating a significant increase in the lower electrode surface area, which relates to marked increases in capacitance and device signal.

Abstract: A method of the present invention forms a vertically oriented structure connected with a source/drain region through an open space. In one embodiment of the method wherein a capacitor storage node is formed, the open space is located between two word line gate stacks in a MOS DRAM memory circuit. A thin landing pad is formed of conducting material in the open space extending to the source/drain region and over the tops of the gate stacks. An insulating layer is formed over the gate stacks and the landing pad. A recess is etched down through the insulating layer to expose an annular portion of the landing pad. A volume of the insulating material is left upon the landing pad in the open space. A conductive layer is deposited in the recess making contact with the exposed annular portion of the landing pad.

Abstract: Methods of forming integrated circuit memory devices, such as DRAM memory cells, include the steps of performing a relatively low dose plug implantation step preferably prior to and after formation of a buried contact hole to expose a storage electrode contact region in a semiconductor substrate. By performing a plug implantation step at a low level prior to formation of a buried contact hole (and after), a memory cell having improved refresh characteristics can be achieved. In particular, the performance of the plug implantation step prior to and after formation of the buried contact hole compensates for substrate damage caused during formation of field oxide isolation regions adjacent the memory cell and during formation of the buried contact hole when the storage electrode contact region is exposed to an etchant.

Abstract: A method of forming a bit line of a dynamic random access memory. An insulating layer is used to cover the source/drain region in a substrate. A trench is formed in the insulating layer above the source/drain region. Then, a portion of the insulating layer inside the trench is removed to form an opening which exposes the source/drain region. A conductor is used to fill the trench and the opening so as to form a bit line and a metal plug, respectively.

Abstract: A method for forming a contact intermediate adjacent electrical components including, providing a node to which electrical connections are desired and which is located between two electrical components; providing oxidation conditions effective to grow an oxide cap on the outer portions of each of the adjacent electric components; exposing a given target area between the adjacent electrical components, the given target area being larger than what would otherwise exist if the oxide caps are not present; selectively removing material from within the target area while simultaneously protecting the adjacent electrical components from the selective removal conditions; selectively removing material from the target area thereby exposing the underlying node; and providing an electrically conductive material within the target area and which is disposed in electrical contact with the node.

Abstract: A semiconductor processing method of forming a capacitor construction includes, a) providing a pair of electrically conductive lines having respective electrically insulated outermost surfaces; b) providing a pair of sidewall spacers laterally outward of each of the pair of conductive lines; c) etching material over the pair of conductive lines between the respective pairs of sidewall spacers selectively relative to the sidewall spacers to form respective recesses over the pair of conductive lines relative to the sidewall spacers, the etching leaving the outermost conductive line surfaces electrically insulated; d) providing a node to which electrical connection to a capacitor is to be made between the pair of conductive lines, one sidewall spacer of each pair of sidewall spacers being closer to the node than the other sidewall spacer of each pair; e) providing an electrically conductive first capacitor plate layer over the node, the one sidewall spacer of each of sidewall spacers, and within the respective r

Abstract: A planarized capacitor array (182) and method of forming the same for high density applications. A storage node contact (116) is formed through an interlevel dielectric (110) on a semiconductor body (102). Then, an oxide layer (170) having a first thickness is deposited over the interlevel dielectric (110) and the storage node contact (116). A nitride layer (172) having a second thickness is deposited over the oxide layer (170) to protect the oxide layer (170) during later processing. The nitride layer (172) and oxide layer (170) are then patterned and etched to form a storage plate cavity (180). The capacitor array (182) is then formed in the storage plate cavity (180). The capacitor array (182) has a height approximately equal to the sum of said first and second thicknesses, so that the surface of the top node of the capacitor array (182) is co-planar with the upper surface of the surrounding oxide/nitride stack (170/172).

Abstract: A method of forming a capacitor on a semiconductor substrate includes forming a first oxide layer on the semiconductor substrate. A contact hole is then formed in the first oxide layer. A first conductive layer is formed on the first oxide layer and in the contact hole. Then the first conductive layer is etched to form a node structure. A non-conformal oxide is formed on the node structure so that the non-conformal oxide has an overhang portion and a lower portion on the sidewall of the node structure. The non-conformal oxide is isotropically etched to remove the lower portion of the non-conformal oxide and to expose the lower sidewall of the node structure. A second conductive layer is conformally deposited on the non-conformal oxide layer and the lower sidewall of the node structure. The second conductive layer is anisotropically etched, using the overhang portion of the non-conformal oxide as a mask. Then the non-conformal oxide is removed by using a highly selective etching process.

Abstract: A method for forming a ragged polysilicon crown-shaped capacitor of a dynamic random access memory cell is disclosed. The method includes forming a first dielectric layer (122) on a semiconductor substrate, and then forming a first silicon nitride layer (124) on the first dielectric layer. Next, a portion of the first silicon nitride layer is removed to form a first hole therein. A first polysilicon spacer (126) is then formed on sidewall of the first silicon nitride layer. Portions of the first dielectric layer are etched, therefore exposing a surface of the substrate, and forming a second hole in the first dielectric layer. Subsequently, a second doped polysilicon layer (128) is formed, thereby refilling the second hole. A second silicon nitride layer (130) is then formed, and the second silicon nitride layer and the second doped polysilicon layer are patterned to form a storage node.

Abstract: A method for making an array of DRAM cells having increased capacitance was achieved. The method forms a planar insulating layer in which are etched capacitor node contact openings to each FET in an array of cells. A first polysilicon layer is deposited to fill the node contact openings and provide a polysilicon planar surface on the insulating layer. A multilayer of alternate layers of a traditional LPCVD silicon oxide and O.sub.3 /TEOS silicon oxide is deposited and patterned having openings aligned over the capacitor node contacts where the capacitors are required. The multilayer is then etched in HF to partially etch and recess the faster etching O.sub.3 /TEOS oxide, forming grooves in the sidewalls of the multilayer structure.

Abstract: A method of fabricating a semiconductor memory device having a capacitor. First, a first insulating layer is formed on a substrate to cover the transistor. Next, a second insulating layer and a first conductive layer are formed in order. The first conductive layer only covers a portion of the second insulating layer to form a branch-like conductive layer. Then, a third insulating layer is formed. An opening is next formed. A second conductive layer is filled into the opening and therefore electrically connected to the source/drain region of the transistor to form a trunk-like conductive layer. Next, the second and the third insulating layers are removed. After a dielectric film is formed on the exposed surfaces of the first and second conductive layers, a third conductive layer is formed on the dielectric film to form an opposed electrode.

Abstract: A method of forming a capacitor on a semiconductor substrate includes forming a first oxide layer on the semiconductor substrate. A contact hole is then formed in the first oxide layer. A first conductive layer is formed on the first oxide layer and in the contact hole. Then the first conductive layer is etched back to the surface of said first oxide layer. A trench is formed in the first dielectric layer aligned with the first conductive layer, with the upper portion of the first conductive layer extending upwards from the bottom surface of the trench. A second conductive layer is conformally deposited on the first conductive layer and the first oxide layer. A second oxide layer is formed on the second conductive layer, filling the trench. A chemical mechanical polishing (CMP) process is then performed to remove the upper portions of the first and second oxide layers and the first and second conductive layers.

Abstract: The present invention relates to a semiconductor device whose through-holes are formed by self-alignment and a method for fabricating the same. The through-holes formed on the gate electrodes can be formed simultaneously with SACs without complicating the fabrication process. The semiconductor device comprises a semiconductor substrate, a device isolation film defining devices regions on the semiconductor substrate, a pair of diffused layers formed in the device regions, gate electrodes formed through a first insulation film on the semiconductor substrate between the pair of diffused layers, and an etching stopper film covering side walls of the gate electrodes and parts of top surfaces of the gate electrodes which are extended inward by a prescribed distance from peripheral edges thereof. Whereby through-holes of an SAC structure can be formed in a later step, and the through-holes can be formed to expose the gate electrodes without removing the etching stopper film.

Abstract: A method of fabricating a rugged-crown shaped capacitor on a semiconductor substrate is provided. Specifically, the method can be applied for fabricating a storage capacitor of a DRAM cell. A doped polysilicon layer is deposited on the substrate and patterned to retain the portion of the doped polysilicon layer within a planned region of the capacitor. Next, an undoped polysilicon layer is deposited on the doped polysilicon layer and the substrate and etched back as undoped polysilicon spacers. Then the doped layer and the undoped spacers are selectively etched by a hot H.sub.3 PO.sub.4 solution to form a crown-shaped node of the capacitor with a rugged surface. Then the undoped portion of the crown-shaped node of the capacitor is doped and the rugged-crown shaped node forms a conductive plate of the DRAM capacitor, providing a rugged-crown shaped capacitor having a larger area to increase its capacitance.

Abstract: The present invention provides a method of manufacturing a cylindrical capacitor which has plug spacers that reduce capacitor size and increase overlay tolerances. The method begins by forming an insulating layer and a passivation layer over a substrate. A plug opening is formed through the passivation layer and the insulating layer. A polysilicon plug is formed in the plug opening. Plug opening spacers are formed on the sidewalls of the insulating and passivation layers in the plug opening. A first dielectric layer having a bottom electrode opening is formed over passivation layer and the plug is exposed. A third polysilicon layer is formed over the first dielectric layer and on the sidewalls of the first dielectric layer. A second dielectric layer is formed over the third polysilicon layer and in the bottom electrode opening. The second dielectric layer and the third polysilicon layer are RIE etched down to the level on the top surface of the first dielectric layer.

Abstract: A method for fabricating a stacked capacitor is disclosed. The method includes forming successively a first dielectric layer, a first polysilicon layer and an insulation layer over a semiconductor substrate. The three layers are patterned to have a window in which a portion of the substrate is exposed. A second polysilicon layer is deposited over the insulation layer and filled in the window. The second polysilicon layer and the insulation layer are patterned to form an island. A dielectric spacer around the island is formed. Moreover, the second polysilicon layer over the insulation layer and the first polysilicon uncovered by the island are removed. The insulation layer in the island is then removed to leave a polysilicon rod surrounded by the dielectric spacer. Polysilicon spacers around the polysilicon rod and the dielectric spacer are formed and the dielectric spacer is removed, thereby forming a lower electrode.

Abstract: A semiconductor device wherein an effective surface area is secured within a contact hole and wherein a storage electrode with rectangular corners is exactly patterned. The effective surface area within a contact hole can be obtained by overlapping the storage electrode contact hole with a portion of the storage electrode, so as to ensure more capacitance. Rounding of the corner of the rectangular storage electrode, which directs the resulting storage electrode to diminish in effective surface area, can be prevented by the different position of the storage electrode mask at the contact hole from one row or column to next, so as to make no difference between the patterned storage electrode and the designed one.

Abstract: A storage capacitor structural configuration for memory cell units of DRAM devices and a process for constructing the capacitor. The capacitor includes a first electrode and a second electrode that are each electrically conducting layers, and a storage dielectric that is a dielectric layer sandwiched between the two electrodes. The silicon substrate of the device has formed thereon a field oxide layer and a transistor including a gate and a pair of source/drain regions. A first dielectric layer covers the transistor and includes a contact opening over one of the source/drain regions. The first electrode includes a first electrically conducting layer formed inside the contact opening and covering the revealed surface of the source/drain region and the first dielectric layer. A second electrically conducting layer having a rugged surface is formed on the surface of the first electrically conducting layer.

Abstract: Fabricating a DRAM memory cell with increased capacitance by increasing the surface area of a storage electrode of a storage capacitor includes forming transfer transistor having a gate electrode and source-drain electrode areas on a semiconductor substrate. First, second and third insulating layers are formed in sequence on the semiconductor substrate and the transfer transistor. The third, second and first insulating layers are selectively etched through to form a contact opening exposing one of the source-drain electrode areas as a contact area. An upper portion of the third insulating layer is etched to form a plurality of first trenches. A first conductive layer is formed over the insulating layer filling the contact opening and the first trenches. An upper portion of the first conductive layer is etched to form a plurality of second trenches, and selectively etched to define a pattern area of a storage electrode of a capacitor.

Abstract: A method of fabricating a semiconductor memory device having a transfer transistor and a storage capacitor. First, a first insulating layer is formed on the substrate to cover the transfer transistor. Next, a first conductive layer is formed, which penetrates the first insulating layer and is electrically connected to one of the source/drain regions of the transfer transistor. A pillar-shaped layer is formed on the first conductive layer. At least first and second films are successively formed on the first conductive layer and the pillar-shaped layer. Then, the second film, the first film, and the first conductive layer are patterned to form an opening, exposing the first insulating layer. A second conductive layer is then formed on sidewalls of the opening. The pillar-shaped layer and the first film are then removed. Finally, a dielectric layer is formed on the first and second conductive layers and the second film and a third conductive layer is formed on the dielectric layer.

Abstract: An improved process for fabricating cylindrical capacitors for use in DRAMs is described wherein the silicon nitride etch stop layer is eliminated. The etch stop layer is normally used to halt etching during the formation of the dielectric cylinder that is used as a substrate on which the cylindrical electrode gets built. If etching is allowed to proceed, the underlying dielectric layer on which the cylinder rests will also be removed. In place of the etch stop layer, the present invention calls for two dielectric layers that have generally similar properties in other respects but substantially different etch rates. For the fast etching dielectric, O.sub.3 TEOS is used while, for the slow etching dielectric, BPTEOS is used. When etched in 10:1 BOE a differential etch rate of about 10 times is obtained so that formation of a O.sub.3 TEOS cylindrical substrate can be completed without significantly eroding the underlying BPTEOS support layer.

Abstract: The present invention provides a method of manufacturing a cylindrical capacitor for a DRAM. A resist layer is first used to pattern a first conductive layer and an oxidation barrier layer into a cylindrical bottom electrode. In a critical step, the resist layer is laterally etched removing a lateral portion of the resist layer thereby exposing an outer cylindrical section of the barrier layer. Using the now narrower (laterally plasma etched) resist layer as a mask, the exposed portions of the oxidation barrier layer are etched away. A masking layer is formed over the sidewalls and the exposed portions of the bottom electrode by an oxidation process. The oxidation barrier layer then is removed. The bottom electrode is anisotropically etched using the masking layer as a mask forming a cylindrical storage electrode. A dielectric layer and top plate electrode are formed over the storage electrode to form the capacitor.