Abstract: The present invention is directed to fabrication of a capacitor formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor to hold a significant charge so as to assist in increased miniaturization efforts in the microelectronic field. The capacitor is fabricated in microelectronic fashion consistent with a dense DRAM array. Methods of fabrication include stack building with storage nodes that extend above a semiconductor substrate surface.

Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a first insulating film on a semiconductor substrate, forming a contact hole in the first insulating film, burying a first conductive film into the contact hole, forming a second conductive film on the first insulating film to connect the second conductive film with the first conductive film, and forming a second insulating film on the second conductive film. The method further comprises the steps of selectively etching the second insulating film, the second conductive film, and a part of the first insulating film to produce a patterned second insulating film, a patterned conductive film, and a patterned first insulating film respectively, and forming sidewalls on sides of the patterned first and second insulating films and the patterned second conductive film to connect the sidewalls with the patterned second conductive film.

Abstract: Fabricating a semiconductor memory device with a capacitor includes forming a first insulating layer on a substrate, covering a transfer transistor, and forming a first conducting layer that penetrates the first insulating layer and is electrically coupled to one of a drain or source region of the transfer transistor. Thereafter, a pillar layer is formed at the periphery of and above the first conducting layer, and a second conducting layer is also formed on sidewalls of the pillar layer. Next, alternately a first and a second film layer are formed at least once over the first conducting layer and the second conducting layer. Then, a second insulating layer is formed above the second film layer. After that, a third conducting layer is formed and then defined such that the first, the second, and the third conducting layers, in combination with the second film layer, form a storage electrode of a charge storage capacitor.

Abstract: A method for fabricating a capacitor of a memory cell in a dynamic random access memory, including forming a branch-like lower electrode, a dielectric film, and a upper electrode. The lower electrode consists of a cylindrical structure and horizontally extended outward conducting branches. This branch-like lower electrode efficiently increases the permittivity of the capacitor by increasing the surface of the electrode.

Abstract: An integrated circuit (IC) fabrication method is provided for the fabrication of an electrode structure having an increased surface area for a double-crown type of capacitor in a dynamic random-access memory (DRAM) device. In this method, damascene technology is used, which can help reduce the height difference between the memory cell region and the peripheral region, thus eliminating the required planarization process in the prior art. Moreover, this method can provide an electrode structure having a large surface area that allows the associated capacitor to be considerably increased in capacitance as compared to the prior art while requiring no increase in the layout area in the integrated circuit.

Abstract: A method for making cylinder-shaped stacked capacitors for DRAMs is described. A planar first insulating layer is formed over device areas. An etch-stop layer, a second insulating layer, and a polish-back endpoint detect layer are deposited in which cylinder-shaped capacitors with node contacts are formed. First openings for node contacts are etched in the polish-back and second insulating layers to the etch-stop layer aligned over the device areas. Wider second openings, aligned over the first openings, are etched through the polish-back layer, and also removes the etch-stop layer in the first openings. The second insulating layer in the second openings is etched to the etch-stop layer, while the first insulating layer is etched in the first openings for node contact openings. A doped first polysilicon layer is deposited and polished back to the polish-back detect layer to form concurrently the node contacts in the first openings and bottom electrodes in the second openings.

Abstract: In one aspect of the invention, an insulative nitride oxidation barrier layer is provided over a cell polysilicon layer to a thickness of at least about 150 Angstroms. An insulating layer is provided above the nitride oxidation barrier layer, and an contact/container is etched therethrough and through dielectric and cell polysilicon layers. Such exposes edges of the cell polysilicon within the contact/container. The wafer is then exposed to an oxidizing ambient to oxidize the cell polysilicon exposed edges, with the nitride oxidation barrier layer during such oxidation exposure inhibiting oxidation of the outer surface of the cell polysilicon layer. In another aspect, a multi-container stacked capacitor construction has its containers defined or otherwise electrically isolated in a single CMP step. In another aspect, a combination etch stop/oxidation barrier layer or region is provided to enable exposure of a precise quantity of the outside walls of a stacked capacitor container.

Abstract: A capacitive structure on an integrated circuit and a method of making the same are disclosed, which is particularly useful in random-access memory devices. Generally, the method of the present invention comprises the steps of forming a substantially vertical temporary support 54 (preferably by forming a cylindrical aperture in an insulating layer) on a semiconductor substrate 10 and forming a substantially vertical dielectric film 32 (preferably a high dielectric constant perovskite-phase dielectric film, and more preferably barium strontium titanate) on temporary support 54. The method further comprises depositing a first conductive (e.g. platinum) electrode 60 on substantially vertical dielectric film 32, and subsequently replacing temporary support 54 with a second conductive (e.g. platinum) electrode 64, such that a thin film capacitor 44 which is substantially vertical with respect to substrate 10 is formed.

Abstract: The present invention is a method for reducing particles during the manufacturing of fin or cylinder capacitors on a wafer. This invention utilizes a negative photoresist wafer edge exposure process to protect the edge of a wafer. This prevents polysilicon peeling from the edge of the wafer so as to reduce the defects and particles appearing on the wafer.

Abstract: Capacitor storage charge can be increased by increasing storage node area. A high aspect surface ratio stack capacitor is produced without increasing overall cell dimensions. The node is formed with layers of low doped and high doped concentration borophosphosilicate glass which is deposited by a single process step with precise nanometer dimensions, are selectively etched so that either doped or undoped layers will have a higher etch rate. This etching creates finger-like projections in the node, which provide for greater surface area using a very simplified process requiring fewer processing steps.

Abstract: A method of making a capacitor comprising providing a space extending between a pair of gate stacks on a semiconductor substrate, the space exposing a charge conducting region on the semiconductor substrate. A BPSG layer is formed over the pair of gate stacks. A hard mask layer comprising alternating layers of doped polysilicon and undoped polysilicon is formed over the BPSG layer during a single deposition cycle of depositing polysilicon. Portions of the hard mask layer and the BPSG layer are selectively removed to form topographical structures extending above the gate stacks and having a trench therebetween. A spacer etch and a contact etch are performed to expose the charge conducting region. A doped polysilicon spacer is formed on the lateral side of each topographical structure. A second group of alternating layers of doped polysilicon and undoped polysilicon is formed over the topographical structures and within the trench.

Abstract: A method for increasing the surface area, and thus the capacitance of a DRAM, stacked capacitor structure, has been developed. A storage node electrode, incorporating branches of polysilicon, is created via use of multiple polysilicon and insulator depositions, as well as via the use of dry anisotropic, and wet isotropic, etching procedures. The use of polysilicon spacers, created on the sides of silicon oxide mesas, adds a vertical component to the polysilicon branches. Removal of a portion of insulator layer from between polysilicon branches, results in exposure of the increased storage node electrode surface area. Unetched portions of the insulator layers, between polysilicon branches, supply structural support for the storage node electrode, comprised of polysilicon branches.

Abstract: A method for manufacturing a capacitor, applied to a memory unit having a substrate forming thereon a dielectric layer, includes the steps of a) forming a sacrificial layer over the dielectric layer, b) partially removing the sacrificial layer and the dielectric layer to form a contact window, c) forming a first conducting layer over the sacrificial layer and in the contact window, d) partially removing the first conducting layer and the sacrificial layer to expose a portion of the sacrificial layer and retain a portion of the first conducting layer, e) forming a second conducting layer alongside the portion of the first conducting layer and the portion of the sacrificial layer, f) removing the portion of the sacrificial layer to expose the dielectric layer, g) forming a third conducting layer over surfaces of the portion of the first conducting layer, the second conducting layer, and the dielectric layer, and h) partially removing the third conducting layer while retaining a portion of the third conducting l

Abstract: A method of fabricating a capacitor includes the steps of forming a layer of a conductive material on a substrate, and forming a patterned oxidation resisting layer on the conductive layer thereby defining exposed and unexposed portions of the conductive layer. The exposed portion of the conductive layer can be selectively oxidized thereby defining an oxide etch mask covering the exposed portions of the conductive layer. Portions of the conductive layer not covered by the oxide etch mask can be selectively etched thereby defining a vertical structure of the conductive material extending from the microelectronic substrate. This vertical structure can be coated with a dielectric layer, and a second conductive layer can be formed on the dielectric layer.

Abstract: A method is disclosed to manufacture a capacitor structure having a high capacitance and a flat topography on a semiconductor device. The method includes steps of: (a) forming a first insulating layer over a substrate having a transistor structure; (b) forming a first and a second contact holes on the first insulating layer; (c) forming a first conducting layer over the first insulating layer; (d) forming a bit line structure above the first contact hole; (e) forming an etching stop layer and a second insulating layer over the substrate, and removing a portion of the etching stop layer and the second insulating layer for forming a capacitor area wherein the second contact plug is exposed; (f) forming a second conducting layer over the substrate, and forming a sacrificial layer in the capacitor area for covering a portion of the second conducting layer; (g) forming the capacitor structure in the capacitor area.

Abstract: In a semiconductor device, such as a memory cell, including a capacitor, a corrugated electrode is used as a lower electrode of the capacitor and is covered with an insulation film to be opposed to an upper electrode. The corrugated electrode is specified in section by a series of folded portions which are alternately folded vertically and horizontally. Practically, the corrugated electrode is formed by a corrugated wall which surrounds a hollow space and which has a rectangular or a polygonal shape on a plane. Alternatively, the corrugated wall has an irregular surface formed by an aggregation of grains so as to effectively widen a surface of the lower electrode. Such a corrugated electrode may be manufactured by a mold which is formed by selectively etching a stack of first-kind spacer films and second-kind spacer films.

Abstract: A method is disclosed for increasing the capacitance of high-density DRAM devices by microlithographic patterning. A semiconductor substrate having a MOS transistor comprising a gate and source/drain regions, and a word line and a bit line is provided. A layer of inter-poly oxide is deposited over the substrate and planarized. Contact holes are etched in the oxide layer until the substrate is exposed. A layer of photoresist is next blanket deposited over the substrate. Using microlithographic methods, the photoresist is then patterned with in-line or staggered micron size features and the underlying inter-poly oxide layer is etched using the photoresist as a mask. The resulting inter-poly oxide surface, therefore, acquires the shape of a micro-folded topography having a roughened surface area of many folds larger than the original flat surface.

Abstract: A method to form capacitance node contacts with improved isolation in a DRAM process is described. An isolation layer is formed on a semiconductor substrate. A first contact hole is formed and filled with a polysilicon plug and the top surface of the isolation layer and of the polysilicon plug are polished to a planar surface. A first interpoly isolation layer is deposited. A stopping layer is deposited. A capping layer is deposited. A first polysilicon layer is deposited. The first polysilicon layer is etched to form features. A second interpoly isolation layer is deposited. The second interpoly isolation layer is planarized. The second contact hole is etched through the second interpoly isolation layer and the capping layer. The exposed first polysilicon material is etched back to the vertical sides of the second contact hole. The stopping layer and the first interpoly isolation layer are etched through to the top surface of the polysilicon plug.

Abstract: A multilayer decoupling capacitor structure is disclosed, having a first decoupling capacitor with one electrode formed in a conductively doped silicon substrate and a second electrode made of conductively doped polysliicon. A third bifurcated conductive layer disposed above the second electrode in conjunction with a fourth conductive layer above the third layer form a second and third decoupling capacitor. The first decoupling capacitor serves to decouple circuitry associated with dynamic random access memory cells, while the second and third decoupling capacitors provide decoupling for further circuitry.

Abstract: A new method for forming stacked capacitors for DRAMs having improved yields when the bottom electrode is misaligned to the node contact is achieved. A planar silicon oxide (SiO.sub.2) first insulating layer, a Si.sub.3 N.sub.4 etch-stop layer, and a disposable second insulating layer are deposited. First openings for node contacts are etched in the insulating layers. A polysilicon layer is deposited and etched back to form node contacts in the first openings. The node contacts are recessed in the second insulating layer, but above the etch-stop layer to form node contacts abutting the etch-stop layer. A disposable third SiO.sub.2 layer is deposited. Second openings for bottom electrodes are etched over and to the node contacts. A conformal second polysilicon layer is deposited and chem/mech polished back to form the bottom electrodes in the second openings. The third and second insulating layers are removed by wet etching to the etch-stop layer.

Abstract: The present invention discloses a method for forming a DRAM capacitor that has improved charge storage capacity by utilizing a deposition process wherein alternating layers of doped and undoped dielectric materials are first deposited, a deep UV type photoresist layer is then deposited on top of the oxide layers such that during a high density plasma etching process for the cell opening, acidic reaction product is generated by the photoresist layer when exposed to UV emission in an etch chamber such that the sidewall of the cell opening is etched laterally in an uneven manner, i.e., the doped dielectric layer being etched more severely than the undoped dielectric layer thus forming additional surface area and an improved charge storage capacity for the capacitor formed.

Abstract: A semiconductor processing method of forming a stacked container capacitor includes, a) providing a pair of spaced conductive runners relative to a substrate, the conductive runners respectively having electrically insulative sidewall spacers and an electrically insulative cap, the caps having respective outer surfaces; b) providing a node between the runners to which electrical connection to a capacitor is to be made; c) providing an electrically conductive pillar in electrical connection with the node, the pillar projecting outwardly relative to the node between the runners and having a first outer surface positioned outwardly of both runner caps, the pillar completely filling the space between the pair of runners at the location where the pillar is located; d) providing an insulating dielectric layer outwardly of the caps and the conductive pillar; e) etching a container opening through the insulating dielectric layer to outwardly expose the conductive pillar first outer surface; f) etching the exposed con

Abstract: The present invention provides a method of forming a opening in a semiconductor dielectric layer. In an advantageous embodiment, the method comprises the steps of forming a hardmask layer on the dielectric layer wherein the hardmask layer has an etch rate less than an etch rate of the dielectric layer, forming a guide opening through the hardmask layer, forming a spacer within the guide opening that reduces a diameter of the guide opening and forming the opening in the dielectric layer through the guide opening. The method may further include the steps of depositing a conductive material in the opening and guide opening and over at least a portion of the hardmask layer that extends beyond the guide opening, and removing the hardmask layer and the conductive material layer that extend beyond the guide opening. In certain embodiments, the contact opening may be formed to a width equal to or less than 0.25 .mu.m.

Abstract: A method of fabricating cylinder capacitors is provided comprising forming a first conductive layer and a dielectric layer on the semiconductor substrate. A via is formed in the dielectric layer. Then, a second conductive layer and a top oxide layer are formed on the dielectric layer. Part of the top oxide layer and the second conductive layer is removed by pattering the photoresist layer. A first spacer is formed at a side wall of the top oxide layer and the second conductive layer. The second conductive layer is etched by using the top oxide layer and the first spacer as a mask. Then, the top oxide layer is removed to form a second spacer. The second spacer is used as a mask in etching the second conductive layer to form a cup-shaped lower electrode. Further, a dielectric film layer and an upper electrode are formed to make a cylinder capacitor.

Abstract: In one aspect, the invention provides a method of forming an integrated circuitry memory device. In one preferred implementation, a conductive layer is formed over both memory array areas and peripheral circuitry areas. A refractory metal layer is formed over the conductive layer to provide conductive structure in both areas. According to a preferred aspect of this implementation, the conductive layer which is formed over the memory array provides an electrical contact for a capacitor container to be formed. According to another preferred aspect of this implementation, the conductive layer formed over the peripheral circuitry area constitutes a conductive line which includes at least some of the silicide. In another preferred implementation, the invention provides a method of forming a capacitor container over a substrate. According to a preferred aspect of this implementation, a conductive layer is elevationally interposed between an upper insulating layer and a lower conductive layer over the substrate.

Abstract: This invention is directed to a semiconductor memory device including a storage element comprising a ferroelectric material or a capacitor dielectric material between a top (plate) electrode and a bottom (stack) electrode. In particular, the invention pertains to the design and fabrication of the stack electrode, which is described as compound because it is comprised of two or more materials which are either patterned separately (with at least one material being deposited and patterned prior to the deposition of the others), or arranged so that each of the component materials significantly contributes to the area over which the ferroelectric or capacitor dielectric is initially deposited. These compound stack electrodes may offer ease in processing, more economical use of noble metal materials, and potentially increased mechanical stability (e.g., resistance to hillocking) relative to solid, single-material electrodes of the same dimensions.

Abstract: A method for forming a DRAM capacitor that uses a sacrificial layer to form a gear-teeth mold for producing a storage electrode having a highly increased surface area. The mold in a sacrificial layer is formed by first depositing alternating layers of two different insulating materials on a dielectric layer, and then patterning the sacrificial layer to form an opening using a conventional method. Next, a wet etching operation is performed using an etchant having a high etching selectivity between the two insulating layers. Hence, sunken slots are formed in the insulating layers that have a higher etching rate than its adjacent insulating layers, thus obtaining a gear teeth cross-sectional profile. Finally, the mold in the sacrificial layer is used for forming the storage electrode.

Abstract: A DRAM capacitor is formed by providing an opening to the surface of the drain of a memory cell's pass transistor. A first layer of polysilicon is deposited over the device and in contact with the drain of the pass transistor. Arsenic ions are implanted into the first layer of polysilicon and the first layer of polysilicon is annealed. A second layer of polysilicon is deposited over the first. Phosphorus ions are implanted into the surface of the second layer of polysilicon. A mask is formed over the two polysilicon layers, and the two layers are etched to define the lateral extent of the memory cell capacitor's lower electrode. An etch that preferentially etches doped polysilicon is used to laterally etch the (doped and annealed) first polysilicon layer, thereby undercutting the second polysilicon layer. The second polysilicon layer is then annealed.

Abstract: A DRAM capacitor structure and its manufacturing include covering a semiconductor substrate with a first conducting layer. A first insulating layer and a second insulating layer are alternately stacked at least once above the first conducting layer to form a multi-layered structure. A contact window opening is formed in the multi-layered structure to expose a source/drain region located above the semiconductor substrate. A pattern is etch-defined on the multi-layered structure, using the first insulating layer as an etching stop layer. Part of the second insulating layer is etched away to form a cross-sectional profile similar to twin towers, with each tower having the form of a vertical T-stack. A second conducting layer covers the multi-layered structure. The first insulating layer and the second insulating layer of the multi-layered structure, as well as the second conducting layer in a top part of the multi-layered structure, are etched away to form a lower electrode.

Abstract: A method of fabricating a stacked type capacitor. A semiconductor substrate having a transistor, a field oxide layer, and a conductive layer formed on top of the field oxide layer is provided. The transistor comprises a gate and a source/drain region. A first dielectric layer is formed over the substrate. An oxide layer is formed over the first dielectric layer. A second dielectric layer is formed on the oxide layer. An etching step is performed to the second dielectric layer to form an opening therein. A first poly-silicon layer is formed on the second dielectric layer and the opening. The first poly-silicon layer is etched back to remove a part of the first poly-silicon layer. A first spacer is formed on a wall of the opening. The oxide layer is etched for a first height by using the first spacer and the second dielectric layer as a first mask. A second poly-silicon layer is formed on the second dielectric layer and the opening.

Abstract: A method of forming a capacitor includes, a) providing a node to which electrical connection to a capacitor is to be made; b) providing an electrically conductive first layer over the node; c) providing an electrically insulative barrier second layer over the first conductive layer; d) providing a third layer over the electrically insulative barrier layer, the third layer comprising a material which is either electrically conductive and resistant to oxidation, or forms an electrically conductive material upon oxidation; e) providing an insulating inorganic metal oxide dielectric layer over the electrically conductive third layer; f) providing an electrically conductive fourth layer over the insulating inorganic metal oxide dielectric layer; and g) providing an electrically conductive interconnect to extend over the second insulative layer and electrically interconnect the first and third conductive layers.

Abstract: A method for fabricating DRAM capacitor which includes forming a transistor having a source/drain regions and a gate electrode above a silicon substrate; then, forming sequentially a stack of layers including a first insulating layer, a second insulating layer, a third insulating layer and a hard mask layer over the transistor; subsequently, patterning and etching the hard mask layer. Thereafter, an oxide layer is formed over the hard mask layer, and then portions of the layers are etched to form a capacitor region over the oxide layer and a contact opening exposing a portion of the source/drain region. In the subsequent step, a conducting layer is formed over the oxide layer, the hard mask layer, the sidewalls of the contact opening and the exposed portion of the source/drain region. Next, a polishing method is used to remove the conducting layer above the oxide layer, and then the oxide layer is removed to form a lower electrode.

Abstract: A method for forming gate segments in an integrated circuit. The method begins by forming a shallow trench isolation region outwardly from a layer of semiconductor material to isolate a plurality of active regions of the integrated circuit. After the isolation region is formed, at least one gate segment is formed in each active region by depositing, planarizing and selectively etching a conductive material. Source/drain regions are also formed in the active region. The active regions are selectively interconnected with edge-defined conductors that pass outwardly from the gate segments and the shallow trench isolation region to form the integrated circuit.

Abstract: A first interlayer insulating film having a second contact hole is formed on a main surface of a semiconductor substrate 1 in a peripheral circuitry. A second plug electrode of the same material as a first plug electrode in a memory cell array is formed in the second contact hole. A pad layer is formed over the second plug electrode and a top surface of the first interlayer insulating film. The pad layer and a capacitor lower electrode are made of the same material. The pad layer is covered with the second interlayer insulating film. A third contact hole is formed at a portion of the second interlayer insulating film located above the pad layer. A first aluminum interconnection layer is formed in the third contact hole. Thereby, a contact can be formed easily between the interconnection layer and the main surface of the semiconductor substrate in the peripheral circuitry of a DRAM, and a manufacturing process can be simplified.

Abstract: A method of forming a capacitor for DRAM according to the invention is disclosed. The method includes the follow steps: a dielectric layer, an etching stop layer, a first insulating layer, a first conductive layer and a second insulating layer are formed in order on a substrate. A contact hole is formed in the second insulating layer. the first conductive layer, the first insulating layer, the etching stop layer and the dielectric layer. Then, a second conductive layer is formed over the substrate and completely fills the contact hole. The second conductive layer is patterned. Next, a silicon nitride layer is formed adjacently to the patterned second conductive layer. Parts of the second insulating layer and the first conductive layer are removed by using the silicon nitride layer as a mask, thereby exposing parts of the first insulating layer. Afterwards, a third conductive layer is formed over the substrate.

Abstract: A semiconductor device and its method of fabrication are provided. The semiconductor device includes a substrate, a patterning stop region, an insulating overlayer, a container region within the insulating overlayer, a charge storage lamina or conductive layer over an interior surface of the container region; a contact region defined by the charge storage lamina or conductive layer; and an electrical contact in the contact region, wherein respective portions of the electrical contact and the charge storage lamina or conductive layer occupy collectively substantially all of the container region. A bit line terminal is coupled to the charge storage lamina through a switching structure.

Abstract: In one aspect, the invention includes: a) forming a first opening into a substrate surface; b) forming a polysilicon layer over the substrate surface and within the first opening to a thickness which less than completely fills the first opening to leave a second opening within the first opening; c) forming a coating layer over the polysilicon layer and within the second opening; d) etching the coating layer and the polysilicon layer to remove the coating layer and the polysilicon layer from over the substrate surface and leave the coating layer and the polysilicon layer within the opening; and e) after the etching, removing the coating layer from within the opening.

Abstract: A new structure of a capacitor for a DRAM is disclosed herein. The structure of the capacitor includes a mushroom shape first storage node, a dielectric layer and a second storage node. The mushroom shape first storage node includes a base portion that is formed of polysilicon. A plurality of mushroom neck portions located on the base portion. A plurality of roof portions are connected on the tops of the mushroom neck portions. The dielectric layer is conformally covered the surface of the mushroom shape storage node. The second storage node encloses the surface of the dielectric layer. The formation of the mushroom shape capacitor includes forming a first conductive layer over a wafer. Then, an undoped hemispherical grains silicon (HSG-silicon) is formed on the first conductive layer. The HSG-silicon is separated along the grain boundaries to expose a portion of the first conductive layer. Next, the exposed first conductive layer is etched by using the HSG-silicon layer as a mask.

Abstract: In the semiconductor device according to the invention, a tubular storage node is formed, then slanting rotation implantation of impurity phosphorus ions is executed for changing the phosphorus concentration and the etching rate at the thermal phosphoric acid treatment time is changed for roughening the surface under good control. Since the surface roughening does not extend to the center of the film of the storage node, the strength of the storage node can be held sufficient. Therefore, the capacitance can be increased.

Abstract: A method for forming a capacitor for an integrated circuit device includes the following steps. An interlayer dielectric layer is formed on a substrate, and a contact hole is formed in the interlayer dielectric layer. A first conductive layer is then formed on the interlayer dielectric layer, wherein the first conductive layer is electrically connected to the substrate through the contact hole. A hole having a depth less than the thickness of the first conductive layer is etched in the first conductive layer. An insulating layer is formed in the hole and the first conductive layer is then etched to a predetermined depth using the insulating layer as an etching mask to expose a side wall of an upper portion of the insulating layer. A spacer is formed on the side wall of the upper portion of the insulating layer. The first conductive layer is then etched using the insulating layer and the spacer as etching marks to form an electrode structure. The insulating layer and spacer are then removed.

Abstract: A DRAM is formed by providing a transfer FET, providing an elevated structure over and adjacent to the transfer FET and then forming a cavity above one of the source/drain regions of the transfer FET. The cavity is filled with a conductor to define in part a lower electrode of a charge storage capacitor. Portions of the cavity are then removed to expose additional charge storage surfaces for the lower electrode of the charge storage capacitor. The elevated structure includes a thick, planarized insulating layer provided over the transfer FET. A cavity is formed by providing an etching mask over the thick, planarized insulating layer with an opening positioned over the first source/drain. Etching is performed to remove a portion of the second insulating layer.

Abstract: A method of forming a stacked capacitor of a dynamic random access memory is disclose. The stacked capacitor is provided on a transistor and comprises first and second electrodes and a dielectric film sandwiched therebetween. The first electrode serving as a storage node. A first silicon oxide film is deposited on an interlayer dielectric film provided on the transistor. The first silicon oxide film is provided for preventing etching of the interlayer dielectric film. Subsequently, an amorphous silicon film is deposited on the first silicon oxide film. The silicon film is used to form the storage node and has density lower than density of the first silicon oxide film. Following this, a second silicon oxide is deposited on the silicon film. The second silicon oxide film is used to shape said silicon film. The second silicon oxide film is selectively removed after the silicon film is shaped using the second silicon oxide.

Abstract: A solid state memory fabrication method of DRAM chips with a self-alignment of field plate/BL isolation process includes using oxide-poly-oxide etch followed by oxidation or sidewall deposition (LPTEOS) to isolate the field plate and BL. This process uses a first etchant and a second etchant in etching the BL/N.sup.+ contact in the fabrication process. During the etch of BL/N.sup.+ contact (2C etch), a low selectivity etchant etches away Ploy-3 first. This first etchant is applied for approximately one hundred eighty seconds. And then a second etchant process is performed using a high Si selectivity etchant, which etches a way the residual oxide. The second etchant is applied for approximately ninety seconds. The exposed poly on the sidewall is isolated from the contact hole by oxidation or deposition (LPTEOS). The oxide formed on the substrate during oxidation is etched away by anisotropic etch. The self-alignment of BL/3P is thus achieved.

Abstract: The present invention discloses a method for forming DRAM stacked capacitors by utilizing a densified oxide layer as an etch-stop for the wet etching process of an upper oxide layer in forming a contact hole for the stacked capacitor and thus, eliminating the need of a silicon nitride etch-stop layer and the occurrence of numerous processing difficulties normally observed in such stacked capacitor forming process. The lower oxide layer can be formed by a BPTEOS chemistry while the upper oxide layer can be formed by an ozone-TEOS chemistry.

Abstract: In a method for forming a capacitor in a semiconductor device, an insulating film is formed on a semiconductor substrate, and an opening is formed through the insulating film. Then, a conductive film is formed to cover a side wall surface of the opening and an upper surface of the insulating film, and a whole surface is mechanically ground so as to selectively remove the conductive film on the upper surface of the insulating film so that the conductive film remains only in an inside of the opening. The remaining insulating film is removed so that a cylindrical electrode is formed of an upstanding remaining conductive film having the same height as the thickness of the removed insulating film.

Abstract: A method for forming DRAM capacitor that utilizes the formation of an oxide layer and the subsequent etch-removal of a portion of the oxide layer located in the gap between a first masking layer and a second masking layer in order to form the minimum separation required between the lower electrodes of adjacent capacitors. Furthermore, when the etching operation is carried on into the conductive layer that lies below the oxide layer, the lower electrode of the capacitor is also patterned out. The manufacturing process in this invention does not use the conventional photolithographic technique, and therefore will not be limited by the resolution of the light source. Consequently, distance between two neighboring capacitors can be reduced, and a higher capacitance for the capacitors can be obtained.

Abstract: A semiconductor structure for a DRAM cell having a high capacitance capacitor. The DRAM cell includes a silicon substrate on which a field oxide layer and a transistor having a gate layer and a source/drain region are formed. A contact surface is formed on a surface of the source/drain region. A silicon nitride layer is formed over the gate layer. A thick oxide layer is formed over one part of the silicon nitride layer, at a lateral side of the contact surface. Silicon nitride spacers are formed over opposite lateral sides of the gate layer, the silicon nitride layer, and the thick oxide layer. One of the silicon nitride spacers located adjacent to the contact surface, is shaped in the form of a pointed protrusion. A self-aligned contact insulating layer covers the thick oxide layer and the other silicon nitride spacer, that is located away from the contact surface. This structure defines a jagged surface over at least the contact surface, the pointed protrusion and the silicon nitride layer.

Abstract: A method of fabricating a capacitor of a semiconductor device is disclosed including the steps of forming a first polysilicon layer and an insulating layer on a semiconductor substrate, implanting ions into the insulating layer to form an ion-implanted layer, patterning the insulating layer including the ion-implanted layer, etching the insulating layer pattern, forming a second polysilicon layer on the insulating layer, removing the insulating layer and the ion-implanted layer, and forming a dielectric layer and a third polysilicon layer on the first and second polysilicon layers.

Abstract: A semiconductor device, such as a dynamic RAM, and method of making it. A number of stacked cell capacitors are placed at a prescribed spacing in an alignment direction on top of a p.sup.- -type silicon substrate (1). Each capacitor has a nearly perpendicular cylindrical lower electrode (cylindrical polysilicon layer (96)), a dielectric film (silicon nitride film (77)), and upper electrode (plate electrode (78) made of polysilicon). The spacing in the alignment direction is smaller than the inner diameter of the lower electrode.

Abstract: After formation of the storage poly in a stacked capacitor DRAM, the oxide 1 layer is partially etched to leave a thick oxide deposition in the area of the future bit line contact, upon which the cell poly is deposited, followed by oxide 2 and then a poly or nitride layer. A mask and etch process forms the bit line contact region through the cell poly, then a thin oxide is deposited and etched along with the oxide 1 to form cell poly spacers that don't close off the active area. The poly or nitride on top of the oxide 2 forms a hard mask that allows the spacers to travel down the side walls of the contact region creating a contact region that is wider at the top than bottom, facilitating metalization.