Abstract: A high capacitance stacked capacitor is defined using one optical mask for two masking steps where one masking step includes overexposing the resist layer. The method begins by forming a planarizing layer 28 over the substrate surface. A first photolithographic process using a first optical mask is used to form a first opening in the planarizing layer 28. A polysilicon stud 38 is formed in the first opening. A dielectric layer 40 is formed over the planarizing layer 28. A second opening 44 is formed in the dielectric layer 40 using a second photolithographic process using the same first optical mask. The second photoresist layer is exposed at a higher energy than the exposure of the first photoresist layer. The dielectric layer 40 is etched using the second photoresist pattern as an etch mask and forming the second opening 44 in the dielectric layer 40. Because of the overexposure, the second opening 44 has a larger open dimension than the first opening 36.

Abstract: A method for fabricating a capacitor having a fin-shaped electrode on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a metal-oxide-semiconductor field effect transistor (MOSFET), having one capacitor aligned over and contacting the source/drain of the MOSFET in the device region. The capacitor is increased in capacitance by forming a multilayer insulator structure over the storage capacitor area and recessing alternate layers, then using the form as a mold for forming a polysilicon fin-like bottom capacitor electrode. The remaining multilayer mold is removed and a high dielectric constant insulator is deposited on the bottom electrode as the inter-electrode dielectric.

Abstract: A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a lower, or storage node electrode, for the STC structure, consisting of a flat, lower polysilicon shape, contacting an underlying transistor region, and of an upper polysilicon shape, comprised of polysilicon spacers, on the sides of the lower polysilicon shape, protruding above the top surface of the flat, lower polysilicon shape. The polysilicon spacers are formed via LPCVD and anisotropic RIE procedures, in addition to the use of a lift off procedure, used to remove unwanted polysilicon spacers from an underlying silicon oxide surface. This storage node configuration results in an significant increase of surface area, when compared to storage nodes fabricated without the incorporation of polysilicon spacers.

Abstract: The present invention provides a method of manufacturing a tub structured stacked capacitor having a central column for a dynamic random access memory (DRAM). The method uses only two photo masks to form the capacitor and a chemical mechanical polishing process to eliminate capacitor dielectric integrity problems. A first insulating layer having a contact opening is formed on a substrate. A first polysilicon layer is formed over the first insulation layer and fills the contact hole with polysilicon. Next, the first polysilicon layer over the first insulation layer is chemically mechanically polished to a depth that at least exposes the first insulation layer thereby forming a central vertical extension. An annular trench is formed in the insulating layer surrounding the central vertical extension. A second polysilicon layer and an oxide layer are formed over the trench, the central vertical extension, and the insulation layer.

Abstract: A method for manufacturing an array of dynamic random access memory (DRAM) cells having a single crown-shaped or a double crown-shaped stacked capacitors is accomplished. The method involves forming an array of device areas on a silicon substrate in which FETs for the DRAM cells are formed. After forming bit line contacts and bit line metallurgy contacting one of the two source/drain areas of each FET, a thick low melting temperature glass (BPSG) is deposited and planarized by annealing. Node capacitor contact openings are formed in the BPSG using a polysilicon sidewall method that reduces the contact size, and a thick polysilicon layer is deposited to contact the node source/drain areas of the FETs, and also provides a planar polysilicon surface. A specially designed edge phase-shift mask is then used with a positive photoresist to pattern the thick polysilicon layer and form crown-shaped bottom electrodes.

Abstract: A method is disclosed to form memory cell structures for DRAMs in which the capacitor nodes are formed in the shape of posts that fit in an area no larger than that which is over the active regions of the semiconductor substrate. Hence, the posts are suitable to accommodate the area that is appropriate for any one of the very high density DRAMs up to and including 1 G-bit. Furthermore, one less mask is used to form the node electrode in comparison with prior art. The interior of said post structure constitutes one electrode and the exterior wall the other, while a thin dielectric separates the two polysilicon plates of the capacitor. It is shown that said post structures perform the multi-function of providing a good support during the planarization process. Optional pillars may be formed at judiciously chosen locations in the cell to provide additional storage nodes and/or more uniform support structures to more readily facilitate chemical-mechanical polishing (CMP) of the substrate surface.

Abstract: A process for forming an upper-layer fin and a lower-layer fin of a storage electrode, and a semiconductor integrated circuit device fabricated by the process. When two-layered polycrystalline silicon films are to be sequentially etched to form the upper-layer fin and the lower-layer fin by the dry-etching method using a first mask, the upper polycrystalline silicon film is patterned at first so far as to form the clearance of the upper-layer fins with the minimum working size of the memory cells of a DRAM, to form the upper-layer fin. Next, the lower-layer fin is formed by the dry-etching method using a second mask which has a pattern enlarged in self-alignment from the pattern of the first mask, so that it is given a larger horizontal size than that of the upper-layer fin.

Abstract: A method for fabricating a dynamic random access memory comprises the steps of forming a diffusion region in a semiconductor substrate, providing an insulation layer on the semiconductor substrate, forming a contact hole in the insulation layer to expose the diffusion region at the contact hole, depositing a semiconductor layer on the insulation layer in the amorphous state such that the semiconductor layer establishes an intimate contact with the exposed diffusion region via the contact hole, patterning the semiconductor layer to form a capacitor electrode, depositing a dielectric film on the capacitor electrode such that said dielectric film covers the capacitor electrode; and depositing a semiconductor material to form an opposing electrode such that the opposing electrode buries the capacitor electrode underneath while establishing an intimate contact with the dielectric film that covers the capacitor electrode.

Abstract: A method for fabricating a semiconductor memory element which has an excellent insulation property suitable for high density integration, including the steps of forming self-aligning plate electrodes by etching a dielectric film covering an upperside protective layer by an amount sufficient to expose each of the dielectric films, forming a third insulation film the entire surface thereof, exposing the upperside protection layer by etching the third insulation film with photosensitive films used as masks, forming a bit line contact by etching the upperside protection layer and the underside protection layer until the impurity region through the bit line contact.