Abstract: The present invention is directed toward methods of fabricating components for microelectronic devices, microelectronic devices including memory cells or other components, and computers including memory devices. For example, one embodiment is directed toward a method of fabricating a memory cell on a workpiece having a substrate, a plurality of active areas in the substrate, and a dielectric layer over the active areas. One embodiment of the method includes constructing bit line contact openings in the dielectric layer over first portions of the active areas and cell plug openings over second portions of the active areas. The method also includes depositing a first conductive material into the bit line contact openings to form bit line contacts and into the cell plug openings to form cell plugs. This embodiment continues by forming a trench through an upper portion of a plurality of the bit line contacts and portions of the dielectric layer between bit line contacts.

Abstract: A MIM capacitor includes a bottom plate, a capacitor dielectric disposed over the bottom plate, and a top plate disposed over the capacitor dielectric. An etch stop material is disposed over the top plate, and the top plate has a width that is less than the width of the etch stop material width. The top plate edges may be pulled back during the removal of the resist used to pattern the top plate, by the addition of chemistries in the resist etch that are adapted to pull-back or undercut the top plate edges beneath the etch stop material.

Abstract: A method of forming a capacitor. The method includes forming a substrate assembly having an interconnect recessed therein, and forming a first electrode on the interconnect. The first electrode includes a material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof. The method further includes forming a second electrode, and forming a dielectric between the first and second electrodes.

Abstract: A capacitor electrode is produced with an underlying barrier structure. A barrier incorporation layer is used and a CMP (chemical mechanical polishing) process is employed in order to produce the barrier structure. The capacitor electrode with an underlying barrier structure is produced by depositing a barrier layer on a semiconductor substrate; forming a barrier structure from the barrier layer with a lithographic mask and an etching step; depositing a barrier incorporation layer covering the barrier structure and surrounding regions; and removing the barrier incorporation layer with chemical mechanical polishing until the barrier structure is uncovered, to thereby form the capacitor electrode above the barrier structure.

Abstract: A semiconductor memory device and fabricating method thereof, wherein the semiconductor memory device includes first and second conductive regions formed in parallel at predetermined regions of a semiconductor substrate, a storage node and a multiple tunnel junction layer pattern sequentially stacked on a channel region between the first and second conductive regions, a data line stacked on the multiple tunnel junction layer pattern, and a wordline covering both sidewalls of the storage node and of the multiple tunnel junction layer pattern, wherein both sidewalls of the storage node have undercut regions for increasing the overlapping area of the storage node and a wordline. The storage node is formed by alternately and repeatedly stacking first and second conductive layers having different etch rates, successively patterning the conductive layers to form a storage node pattern, and selectively and isotropically etching the first or second conductive layer of the storage node pattern.

Abstract: A storage electrode has a truncated-conical “pipe-shaped” top section having a small inner diameter, mounted on a cylindrical base section having a large inner diameter. To fabricate the storage electrode, a buried contact plug is formed on a first insulating layer on a wafer, and an etching stop layer and a second insulating layer are formed on the first insulating layer. A third insulating layer is formed on the second insulating layer after implanting impurities into the second insulating layer. An opening is formed by anisotropically etching the third insulating layer and the second insulating layer using a photoresist pattern as an etching mask. A cleaning process is carried out such that the second insulating layer exposed through the opening is isotropically etched. After depositing polysilicon along a profile of the second and third insulating layers to a uniform thickness, the remaining third and second insulating layers are removed.

Abstract: The present invention is directed to fabrication of a capacitor formed with a substantially concave shape and having optional folded or convoluted surfaces. The concave shape optimizes surface area within a small volume and thereby enables the capacitor to hold a significant charge so as to assist in increased miniaturization efforts in the microelectronic field. The capacitor is fabricated in microelectronic fashion consistent with a dense DRAM array. Methods of fabrication include stack building with storage nodes that extend above a semiconductor substrate surface.

Abstract: A semiconductor integrated circuit device including a dynamic random access memory (DRAM) unit having improved signal-to-noise ratio, reduced bit line capacitance, and reduced area is provided. The DRAM unit includes a plurality of bit line pairs, each bit line pair including a first metal conductor and a second metal conductor. Each bit line pair includes a reference bit line and a sense bit line. Each bit line pair may be configured such that the reference bit line and the sense bit line are longitudinally oriented with respect to each other. Alternatively, each bit line pair is configured such that the first metal conductor and the second metal conductor are symmetrically twisted about each other in at least one location. The lateral spacing between a cell plate and a transistor gate is minimized, resulting in reduced overall area.

Abstract: There is described a semiconductor device having a storage node capacitor structure suitable for rendering memory cells compact, and storage nodes are prevented from tilting. The device includes a storage node which has a vertical surface extending in the direction perpendicular to the surface of a semiconductor substrate, and a dielectric film for tilt prevention purposes which is brought into close contact with the side surface of the vertical surface and which prevents the vertical surface from tilting.

Abstract: An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line contact is completed by extending a via from the bit line, formed above the interlevel dielectric, down to the level of the intermediate plug, and the via is filled with metal. The height of the via to be filled is thus reduced by the height of the intermediate plug. In one embodiment, the intermediate plug is slightly shorter than an adjacent container-shaped capacitor. In another embodiment, the intermediate plug is about as high as an adjacent stud capacitor.

Abstract: A method of fabricating a semiconductor device includes steps of forming an interlayer dielectric film to cover upper sides of a bit line pad and a storage node pad defining a first conductive layer, simultaneously forming a plurality of contact holes reaching upper surface of the first conductive layer through the interlayer dielectric film, expanding in width upper portion of part of the aforementioned plurality of contact holes, thereby forming a trench for a second conductive layer, and arranging conductors in the aforementioned plurality of contact holes and the aforementioned trench for a second conductive layer. Thus, a bit line contact, a storage node contact and a bit line serving as the second conductive layer are obtained.

Abstract: The present invention discloses a method for fabricating a semiconductor device. In a process for forming metal interconnection contact holes on both a gate electrode including an Si-rich SiON film as a mask insulating film in a peripheral circuit region and on a semiconductor substrate, the metal interconnection contact hole is formed according to a three-step etching process using a photoresist film pattern exposing the intended locations of a metal interconnection contacts as an etching mask. Accordingly, contact properties are improved by preventing damage to the semiconductor substrate, thereby reducing leakage current and improving yield.

Abstract: A container capacitor and method of forming the container capacitor are provided. The container capacitor comprises a lower electrode fabricated by forming a layer of doped polysilicon within a container in an insulative layer disposed on a substrate; forming a barrier layer over the polysilicon layer within the container; removing the insulative layer to expose the polysilicon layer outside the container; nitridizing the exposed polysilicon layer at a low temperature, preferably by remote plasma nitridation; removing the barrier layer to expose the inner surface of the polysilicon layer within the container; and forming HSG polysilicon over the inner surface of the polysilicon layer. The capacitor can be completed by forming a dielectric layer over the lower electrode, and an upper electrode over the dielectric layer. The cup-shaped bottom electrode formed within the container defines an interior surface comprising HSG polysilicon, and an exterior surface comprising smooth polysilicon.

Abstract: In order to provide a particularly space-saving capacitor configuration in a memory device, a plurality of second electrode regions which are not in direct electrical contact with one another are formed on areas of a first electrode region covered by a dielectric material. During operation of the capacitor configuration, portions of the first electrode region form bottom electrodes which are connected by a connecting region, so that an additional connecting device for the bottom electrodes is not necessary.

Abstract: Provided is a method for fabricating a capacitor using an electrochemical deposition method and Ce(NH4)2(NO3)6 solution. The method includes the steps of: a) forming a contact hole in an insulation layer on a substrate; b) forming a plug including nitride in the contact hole; c) forming a Ru seed layer in the contact hole and on the insulation layer; d) forming a sacrificial layer including an open area overlapped with the contact hole on the Ru seed layer; e) forming a Ru layer for an electrode of the capacitor in the open area by performing electrochemical deposition; f) removing the sacrificial layer, whereby the Ru seed layer not covered with the Ru layer is exposed; and g) etching the exposed Ru seed layer by using an aqueous solution including Ce(NH4)2(NO3)6.

Abstract: A method of fabricating a high-density capacitor. At least one first trench is formed in a dielectric layer positioned on a semiconductor substrate. A first liner layer and a first conductive layer are formed on the semiconductor substrate followed by a first planarization process. At least one second trench having a joint side wall with the first trench is formed in the dielectric layer. A capacitor dielectric layer, a second liner layer, and a second conductive layer are formed on the semiconductor substrate followed by a second planarization process. The surfaces of the first conductive layer and the second conductive layer are then exposed to form a high-density capacitor having a three-dimensional structure.

Abstract: A method for forming gate segments in an integrated circuit. The method begins by forming a shallow trench isolation region outwardly from a layer of semiconductor material to isolate a plurality of active regions of the integrated circuit. After the isolation region is formed, at least one gate segment is formed in each active region by depositing, planarizing and selectively etching a conductive material. Source/drain regions are also formed in the active region. The active regions are selectively interconnected with edge-defined conductors that pass outwardly from the gate segments and the shallow trench isolation region to form the integrated circuit.

Abstract: Method for forming at least a portion of a top electrode of a container capacitor and at least a portion of a contact plug in one deposition are described. In one embodiment, the top electrode is formed interior to a bottom electrode of the container capacitor. In another embodiment, the top electrode is formed interior to, and exterior and below a portion of the bottom electrode of the container capacitor. The method of forming a top electrode of a container capacitor and a contact plug with a same deposition is particularly well-suited for high-density memory array formation.

Abstract: Methods are presented for reducing the thermal budget in a semiconductor manufacturing process that include for instance, depositing high dielectric constant films to form MIS capacitors, where processes including plasma nitridation and oxidation and deposition processes including ALD and PVD are selectively employed to lower the overall thermal budget thereby allowing smaller structures to be reliably manufactured.

Abstract: Integrated circuitry fabricated using methods for forming contact structures and container structures, as described herein, are provided. The integrated circuitry formed by the methods of the present invention, for example DRAM structures, provide capacitors in containers having sufficiently high storage capacitance for advanced integrated circuit devices. In addition the methods for forming such container capacitors facilitate the formation of contacts structures and provided for the formation of local interconnect structures and electrical contact to each of the structures formed.

Abstract: The integrated ferroelectric semiconductor memory is fabricated according to the stack cell principle. A ferroelectric capacitor module is formed on an intermediate oxide above a selection transistor located in or on a semiconductor wafer. The capacitor module is brought into conductive contact by its bottom capacitor electrode with an electrode of the selection transistor by means of an electrically conductive plug leading through the intermediate oxide. A layer system of a conductive oxygen diffusion barrier and a conductive adhesion layer is deposited directly below the bottom capacitor electrode, and the adhesion layer and the overlying oxygen diffusion barrier are deposited directly into the contact hole and form the plug at least in the region lying directly below the bottom capacitor electrode.

Abstract: A method of forming silicon storage nodes on silicon substrates, wherein the silicon storage nodes have a roughened surface, which does not result in deposition of silicon atoms over the entire surface of the silicon substrate and which does not require the silicon storage nodes to be comprised of amorphous silicon prior to being subjected to the surface-roughening treatment.

Abstract: Methods of forming electrical connections with an integrated circuitry substrate node location are described. According to one aspect of the invention, a substrate node location is laterally surrounded with insulating material and left outwardly exposed. Conductive material is deposited over the exposed node location. Subsequently, a photomaskless etch of the conductive material is conducted to a degree sufficient to leave a plug of conductive material over the node location. In a preferred implementation, the insulating material with which such node location is surrounded constitutes insulating material portions which are provided relative to conductive lines which are formed over the substrate. In another preferred implementation, such conductive lines form a grid of insulating material which, in turn, defines the node location. According to a preferred aspect of the invention, a plurality of insulated conductive lines are formed over a substrate.

Abstract: Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material.

Abstract: A method of forming a structure having a contact hole includes the steps of (a) forming an insulating layer on a first conductive layer, (b) forming a second conductive layer on the insulating layer, (c) forming an opening in the second conductive layer, (d) forming a conductive sidewall around an inner wall of the first conductive layer defining the opening, (e) selectively etching the insulating layer in a state where the second conductive layer and the conductive sidewall function as etching masks, so that the contact hole having a width smaller than that of the opening and defined by the conductive sidewall is formed, and the first conductive layer is exposed through the contact hole, and (f) removing the second conductive layer and the conductive sidewall.

Abstract: Disclosed are a semiconductor device and a method for fabricating the same and, more particularly, a method for decreasing the size of semiconductor devices by stacking two substrates, one of which has only memory cells and the other of which has only logic circuits is disclosed. The disclosed method includes forming memory cells on a first semiconductor substrate; forming logic circuits on a second semiconductor substrate; and stacking the second semiconductor substrate on the first semiconductor substrate in order that the memory cells are electrically operable to the logic circuits on the second semiconductor substrate. In the disclosed stacked semiconductor substrate, the logic circuit area is placed on the memory cell area and these two areas are electrically connected by a metal interconnection, thereby decreasing the size of the semiconductor devices.

Abstract: A process of manufacturing a flash memory device having a tunnel oxide layer with high reliability, low defect and interface trap by using semi-atmospheric pressure chemical vapor deposition (SPACVD) and tetra-ethyl-ortho-silicate (TEOS) reactant. SAPCVD is performed accompanied with a reaction temperature between about 600° C. and about 750° C. and a reaction pressure between about 340 Torr and about 500 Torr to react TEOS and oxygen.

Abstract: A unique electrochemical process fills oxygen vacancies in dielectrics while reducing oxidation of nearby electrodes and conductors. Preferably, an electromagnetic field or bias is applied to a dielectric. The bias causes oxygen vacancies in the dielectric to migrate to the surface of the dielectric. As the oxygen vacancies migrate toward the surface, oxygen ions fill the oxygen vacancies. In one embodiment, a unique plasma treatment provides the oxygen ions that react with the oxygen vacancies. In another embodiment, a unique electrolysis treatment provides the oxygen ions that react with the oxygen vacancies.

Abstract: Methods for fabricating semiconductor devices having capacitors are provided. A plurality of storage node electrodes are formed on a semiconductor substrate. Then, a capacitor dielectric layer is formed over the storage node electrodes. A plate electrode layer is subsequently formed on the capacitor dielectric layer. A hard mask layer is then formed on the resultant structure where the plate electrode layer is formed so as to fill a gap between the adjacent storage node electrodes. The hard mask layer and the plate electrode layer are successively patterned to form a plate electrode.

Abstract: A capacitor for a semiconductor memory device is fabricated by forming a mold layer on a semiconductor substrate that includes a peripheral circuit area and a cell array area which includes a plug in a buried contact hole. A hard mask layer pattern is formed on the mold layer. The mold layer is etched, using the hard mask layer pattern as an etch mask, to form a mold layer pattern. The hard mask layer pattern is then removed from the mold layer pattern or only partially etched back on the mold layer pattern. A capacitor lower electrode is formed along the walls of the buried contact hole and on a surface of the mold layer pattern. A capacitor dielectric layer is formed on the capacitor lower electrode and a capacitor upper electrode is formed on the capacitor dielectric layer.

Abstract: Within metal interconnect layers above a substrate of an integrated circuit, a vertical metal-insulator-metal (VMIM) capacitor is formed by the same damascene metallization types of processes that formed the metal interconnect layers. The metal interconnect layers have horizontal metal conductor lines, are vertically separated from other metal interconnect layers by an interlayer dielectric (ILD) layer, and electrically connect to the other metal interconnect layers through via connections extending through the ILD layer. One vertical capacitor plate of the VMIM capacitor is defined by a metal conductor line and a via connection. The other vertical capacitor plate is defined by a metal region adjacent to the metal conductor line and the via connection. The metal conductor line, the via connection and the metal region are formed by the damascene metallization processes.

Abstract: A method for fabricating a semiconductor device that forms a capacitor and metal interconnection in the same level, simultaneously using a damascene process for forming a metal interconnection. A capacitor structure having the high capacitance needed for logic elements is obtained without increasing the number of layers for fabricating the capacitor by forming a three-dimensional capacitor in the damascene pattern while maintaining the conventional processes in a damascene interconnection process.

Abstract: A method for fabricating a memory array includes fabricating a first portion (110, 310, 510) of a memory array on a first side (14, 214, 414) of a substrate (12, 212, 412). A second portion (150, 350, 550) of the memory array is fabricated on a second, opposite side (16, 216, 416) of the substrate (12, 212, 412). The first portion (110, 310, 510) and the second portion (150, 350, 550) of the memory array are coupled to each other through the substrate (12, 212, 412).

Abstract: There is disclosed a method of manufacturing a capacitor in a semiconductor device. The present invention forms a Ru film as a lower electrode of the capacitor in which a Ta2O5 film is used as a dielectric film by introducing Ru of a raw material, oxygen and NH3 in order to reduce oxygen or a NH3 plasma process as a subsequent process is performed in order to remove oxygen existing on the surface of the Ru film. Therefore, the present invention can prevent oxidization of a diffusion prevention film due to oxygen existing in a Ru film during annealing process performed after deposition of a Ta2O5 film and thus improve reliability of the device.

Abstract: In order to improve the performance of a semiconductor integrated circuit device wherein a capacitor provided between storage nodes of an SRAM and a device having an analog capacitor are formed on a single substrate, a plug is formed in a silicon oxide film on a pair of n channel type MISFETs in a memory cell forming area, and a local wiring LIc for connecting respective gate electrodes and drains of the pair of n channel type MISFETs is formed over the silicon oxide film and the plug. Thereafter, a capacitive insulating film and an upper electrode are further formed over the local wiring LIc. According to the same process step as the local wiring, capacitive insulating film and upper electrode formed in the memory cell forming area, a local wiring LIc, a capacitive insulating film and an upper electrode are formed over a silicon oxide film in an analog capacitor forming area and a plug in the silicon oxide film.

Abstract: A non-volatile semiconductor memory device with a small variation in capacitance-coupling to the stacked gate for memory miniaturization. The device has a memory cell array in which memory cells are arranged in array. Each cell has a first gate and a second gate on a semiconductor substrate. The first gate is formed, via a first gate insulating film, on each of device forming regions isolated by device-isolating insulating films. The second gate is formed on the first gate via a second gate insulating film. The first gate is patterned so that its portion is overlapped on the isolation insulating film from the device forming region. A protective insulating film is provided on the isolation film between the device forming regions and in the vicinity of the first gate. A charge-storage layer of each memory cell has at least two stacked conductive layers with a small isolation width at a low aspect ratio for burying isolation insulating films for high density, to easily fabricate in low cost.

Abstract: In this process, a capacitor core is formed on a semiconductor device with a first conductive sublayer in contact with a plug. First form a stack of alternately doped and undoped oxide layers on the sublayer with the stack comprising a bottom layer formed on top of the sublayer and each additional layer in the stack formed on a previous one of the layers in the stack. Then form a mask over the stack and etch through the mask to pattern the oxide layers to form cavities in the stack of oxide layers reaching down through the stack to the sublayer. Then perform differential etching of the oxide layers in the cavities. Form undercut edges in the doped oxide layers with the undoped oxide layers having cantilevered ribs projecting from the stacks into the cavities to complete the cavities. Deposit a bulk/thick film monolithic conductive layer into the cavities to form a monolithic capacitor core with counterpart cantilevered ribs.

Abstract: A stacked capacitor on a contact plug of a semiconductor substrate and the method for fabricating the same. A cylindrical conductive layer is formed upon a contact plug of a semiconductor substrate as a lower electrode of a stacked capacitor and there is an opening in the cylindrical conductive layer. A barrier layer is deposited inside the opening of the cylindrical conductive layer and fills a portion of the opening. A capacitor dielectric layer is deposited on the cylindrical conductive layer and on the barrier layer and an upper electrode layer is formed on the capacitor dielectric layer to complete the stacked capacitor.

Abstract: Methods of forming electrical connections with an integrated circuitry substrate node location are described. According to one aspect of the invention, a substrate node location is laterally surrounded with insulating material and left outwardly exposed. Conductive material is deposited over the exposed node location. Subsequently, a photomaskless etch of the conductive material is conducted to a degree sufficient to leave a plug of conductive material over the node location. In a preferred implementation, the insulating material with which such node location is surrounded constitutes insulating material portions which are provided relative to conductive lines which are formed over the substrate. In another preferred implementation, such conductive lines form a grid of insulating material which, in turn, defines the node location. According to a preferred aspect of the invention, a plurality of insulated conductive lines are formed over a substrate.

Abstract: A method for fabricating a cylinder-type capacitor for a semiconductor device includes the steps of forming in sequence a first insulating layer, a first etch stop layer, a second insulating layer, and a second etch stop layer on a semiconductor substrate including a conductive region, forming a second etch stop layer pattern, a second insulating layer pattern, and a first etch stop layer pattern by etching a part of the second etch stop layer, the second insulating layer, and the first etch stop layer so that a storage node hole for exposing the surface of a part of the first insulating layer may be formed, forming a spacer on an inner wall of the storage node hole, forming a first insulating layer pattern by etching the first insulating layer exposed using the second etch stop layer pattern and the spacer as a mask so that a node contact hole for exposing the conductive region is formed, removing the second etch stop layer pattern and the spacer, forming a lower electrode on the surfaces of the storage node

Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode formed over the semiconductor substrate and a first interlevel insulating layer which is formed over the semiconductor substrate and has first and second contact holes defined by the first interlevel insulating layer. The semiconductor device also includes a first wiring pattern formed in the first contact hole and on the first interlevel insulating layer, a protection layer covering the first wiring pattern and a second interlevel insulating layer which is formed over the first interlevel insulating layer and has a third contact hole defined by the second interlevel insulating layer. The semiconductor device further includes the third contact hole being located on the second contact hole and a second wiring pattern formed in the second and third contact holes and on the second interlevel insulating layer.

Abstract: A capacitor having an electrode with a general cup shape, including a generally horizontal bottom and vertical walls, and in electric contact by its bottom with a conductive pad, the pad extending beyond the upper surface of an insulating layer and the bottom including a complementary recess of the protruding pad portion.

Abstract: A DRAM capacitor contact comprised of a silicon oxide layer with a trench having sidewalls and a form in the silicon oxide layer. A dielectric liner is coated on the sidewalls of the trench. A metal layer is then deposited between the sidewalls and polished to form a bit-line. One or more dielectric layers are deposited above the bit-lines and VIAs are formed in these layers. A sidewall is formed in the VIA above the bit-line and the VIAs are extended down to the silicon substrate and filled with a conductive material and planarized, forming the capacitor contact.

Abstract: A process for forming a capacitive structure and a fuse structure in an integrated circuit device includes forming a first capacitor plate and first and second fuse electrodes in a first dielectric layer of the device. In a second dielectric layer overlying the first dielectric layer, a capacitor dielectric section overlying the first capacitor plate, and a fuse barrier section overlying and between the first and second fuse electrodes are formed simultaneously. In a conductive layer overlying the second dielectric layer, a second capacitor plate overlying the capacitor dielectric section, and a fuse overlying the fuse barrier section and contacting the first and second fuse electrodes are formed simultaneously. The capacitor dielectric section and the fuse barrier section may be defined simultaneously by selectively removing portions of the first dielectric layer during a single etching step.

Abstract: The semiconductor memory device includes an interlevel dielectric pattern and an adhesive pattern, wherein both the interlevel dielectric and adhesive patterns include a contact hole to expose a semiconductor substrate. The adhesive pattern sufficiently adheres a lower electrode of a capacitor to the interlevel dielectric pattern, and thus prevents damage to the interlevel dielectric pattern during the formation of the capacitor. A conductive plug is disposed within the contact hole and may project higher than the top surface of the adhesive pattern. A leakage current preventive pattern is formed on top of the adhesive pattern and prevents a capacitor dielectric layer from directly contacting the plug to prevent occurrences of leakage current. A lower electrode of a capacitor electrically connected to the plug is formed on the plug.

Abstract: A method of fabricating a vertical transistor of a memory cell is disclosed. Accordinng to this method, a semiconductor substrate is first provided. A pad layer is formed on the surface of the substrate. A deep trench is formed in the substrate. In the deep trench, a trench capacitor is formed, a collar oxide layer is then formed on the sidewalls above the trench capacitor. A first conductive layer is formed above the trench capacitor. A second conductive layer is deposited to form a buried strap and an opening. A first insulating layer and a second masking layer are formed and fill the opening. The pad layer, the substrate, the second masking layer, the first insulating layer, the collar oxide layer and the first conductive layer are patterned. A second insulating layer is deposited and forms a Shallow Trench Isolation. A portion of the second masking layer is removed. The pad layer is removed to expose the substrate. A well is formed in the exposed substrate after forming a third insulating layer.

Abstract: Providing a capacitance element which prevents short-circuit between adjacent storage node layers caused by an adhering conductive foreign matter. A method of manufacturing a capacitance element in which a plurality of aperture portions are formed in an insulation layer on a semiconductor substrate and a storage node layer is formed at inner surfaces of the aperture portions, comprising the steps of forming a plurality of aperture portions in an insulation layer from a surface of a silicon oxide film, forming a conductive layer so as to cover the insulation layer and the silicon oxide film, removing the conductive layer on the silicon oxide film so that the conductive layer remaining inside the aperture portions becomes storage node layers, and removing silicon oxide film.

Abstract: A method for manufacturing a semiconductor device incorporating therein an insulating layer prevents a bridge between metal patterns. The method begins with the preparation a semiconductor substrate divided into a peripheral region and a cell region provided with a first metal pattern formed thereon, wherein the regions are adjacent to each other. Thereafter, a first insulating layer is covered on top of the first metal pattern. And then, a second insulating layer is formed on top of the first insulating layer, wherein an etching rate of the first insulating layer is slower than that of the second insulating layer. In the next step, the second insulating layer is planarized to a predetermined thickness for smoothing a step contour between the cell region and the peripheral region. Finally, a second metal pattern is formed on top of the planarized second insulating layer, thereby preventing a bridge between the first and the second metal patterns.

Abstract: A method for fabricating a CUB DRAM device having an enlarged process window for bit line contact patterning is deacribed. A plurality of capacitor node contact junctions and a bit line junction are provided in a semiconductor substrate. A node contact plug is formed through a first insulating layer to each of the capacitor node contact junctions. A bit line contact plug is formed to the bit line junction. Openings are etched through a second insulating layer to each of the node contact plugs. A polysilicon layer is conformally deposited within the openings and then recessed below the top of the openings wherein each of the polysilicon layers forms a bottom plate electrode of a capacitor. A capacitor dielectric layer is formed overlying the bottom plate electrodes and the second insulating layer. A polysilicon layer is deposited overlying the capacitor dialectic layer and patterned to form top capacitor plates overlying each of the bottom plate electrodes to complete the capacitors.

Abstract: A ferroelectric memory transistor includes a substrate having active regions therein; a gate stack, including: a high-k insulator element, including a high-k cup and a high-k cap; a ferroelectric element, wherein said ferroelectric element is encapsulated within said high-k insulator element; and a top electrode located on a top portion of said high-k insulator; a passivation oxide layer located over the substrate and gate stack; and metalizations to form contacts to the active regions and the gate stack.