Abstract: An integrated DRAM cell comprises a DRAM capacitor and a transistor. The capacitor of the cell is formed in a first well in a dielectric layer overlying the cell transistor. The top electrode of the capacitor also serves as a barrier layer between an underlying plug in a second well in the dielectric layer. A method of forming the cell comprises the step of using a single mask for formation of the layer which acts as both the top electrode of the capacitor and the barrier layer of the second well.

Abstract: Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material. In another embodiment, a capacitor storage node is formed having an uppermost surface and a side surface joined therewith. A protective cap is formed over the uppermost surface and a capacitor dielectric layer is formed over the side surface and protective cap. A cell electrode layer is formed over the side surface of the capacitor storage node.

Abstract: A method of planarizing the peripheral circuit region of a DRAM. A first oxide layer and a silicon nitride layer are sequentially formed over a substrate. A plurality of polysilicon plugs are formed within the crown-shaped capacitor region of the DRAM. A patterned second oxide layer is formed over the silicon nitride layer. A conformal doped amorphous silicon layer is formed over the exposed surface of the crown-shaped capacitor region and the peripheral circuit region of the DRAM. A photoresist layer is formed over the crown-shaped region and then a nitrogen implant is carried out to form a silicon oxy-nitride barrier layer. A chemical-mechanical polishing is carried out to separate the various lower electrodes. The photoresist layer and the second oxide layer within the crown-shaped capacitor region are removed. Hemispherical silicon grains are grown on the exposed surface of the doped amorphous silicon layer.

Abstract: An intermediate metal plug is used to raise the platform to which contact is to be made. In the illustrated process, a partial bit line plug is formed adjacent a stacked capacitor, and an interlevel dielectric formed over the capacitor. The bit line contact is completed by extending a via from the bit line, formed above the interlevel dielectric, down to the level of the intermediate plug, and the via is filled with metal. The height of the via to be filled is thus reduced by the height of the intermediate plug. In one embodiment, the intermediate plug is slightly shorter than an adjacent container-shaped capacitor. In another embodiment, the intermediate plug is about as high as an adjacent stud capacitor.

Abstract: An integrated circuit comprising stacked capacitor memory cells having sub-lithographic, edge-defined word lines and a method for forming such an integrated circuit. The method forms conductors adjacent to sub-lithographic word lines in order to couple a stacked capacitor to the access transistor of the memory cell. The conductors are bounded by the word lines. The bit line and capacitor are formed with a single mask image in such a manner as to self-align the bit line and the capacitor and to maximize the capacitance of the memory device. The method may be used to couple any suitable circuit element to a semiconductor device in an integrated circuit having edge-defined, sub-lithographic word lines.

Abstract: The invention relates to a method for fabricating a capacitor of a semiconductor device including the steps of: forming storage nodes for being connected with predetermined portions of a semiconductor substrate; forming a surface nitride layer by performing a surface nitrification process for preventing formation of an oxide layer on the surface of the storage nodes that deteriorates dielectric characteristic of the layer; forming an alumina (Al2O3) layer as a dielectric layer on the surface nitride layer in a perovskite structure with superior electrical and mechanical strength; and forming a plate electrode on the dielectric layer, thereby forming a capacitor with capacitance high enough to achieve high integration of the semiconductor device.

Abstract: The present invention discloses a method of manufacturing a capacitor in a semiconductor device which is directed to solve the problem of reduction of capacitance occurring when manufacturing a capacitor of a MIS structure using poly-silicon as an underlying electrode and metal as an upper electrode in a capacitor using Ta2O5 as a dielectric film. In order to solve the problem, the present invention forms an underlying electrode using metal having a good oxide-resistant such as TiSiN. Thus, the present invention could not only lower the thickness of the effective oxide film of Ta2O5 when depositing Ta2O5 or performing a thermal process for crystallization but also prevent increase of a leak current due to oxidization of the underlying electrode and the diffusion prevention film, thus securing the capacitance of the capacitor and improving the electric characteristic of the capacitor.

Abstract: A method of forming silicon storage nodes on silicon substrates, wherein the silicon storage nodes have a roughened surface, which does not result in deposition of silicon atoms over the entire surface of the silicon substrate and which does not require the silicon storage nodes to be comprised of amorphous silicon prior to being subjected to the surface-roughening treatment.

Abstract: In one embodiment, the present invention provides a method of forming a dynamic random access memory device which utilizes self-aligned contact pads 40a and 40b for the bit line and storage node contacts. A transfer gate 14 is formed at the fact of a semiconductor region 30. The semiconductor 30 includes a bit line contact region 44 and storage node contact region adjacent opposite edges of the transfer gate 14. Transfer gate 14 is surrounded with an insulating material 34/38. A conductive layer 40 is formed over the transfer gate 14, over the bit line contact region 44 and over the storage node contact region. This conductive layer 40 is then etched so that a first portion 40a of the conductive layer 40 provides an electrical contact to the bit line contact region 44 and a second portion 40b of the conductive layer 40 provides an electrical contact to the storage node contact region.

Abstract: The semiconductor device comprises a MOSFET including a pair of impurity diffused regions formed on both sides of a gate formed on a semiconductor substrate; an insulation film covering a top of the MOSFET and having a through-hole opened on one of the impurity diffused regions formed in; and a capacitor formed at at least a part of an inside of the through-hole, the through-hole having a larger diameter inside than at a surface thereof or having a larger diameter at an intermediate part between the surface thereof and a bottom thereof than the surface and the bottom thereof.

Abstract: A plurality of charge storage electrodes are formed on an interlayer insulating film which is formed on a silicon substrate. A plurality of insulating members which surround periphery of the charge storage electrodes and which are separated from each other are formed. A capacitance insulating film is so formed as to cover the plurality of charge storage electrodes and the plurality of insulating members. A plate electrode is formed on the capacitance insulating film. The insulating members are formed of a silicon nitride film which has a function as an etching stopper for protecting the interlayer insulating film.

Abstract: A capacitor core is formed on a semiconductor device with a first conductive layer in contact with a plug. A mold is formed from a stack of alternately doped and undoped silicon dioxide layers on the sublayer with the stack comprising a bottom layer formed on top of the sublayer and each additional layer in the stack formed on a previous one of the layers in the stack. Pattern the silicon dioxide layers in the mold which are alternatingly doped and undoped to form an intercore, capacitor-core-shaping cavity in the stack of silicon dioxide layers reaching down through the stack to be bottom of the stack. Then perform differential etching of the silicon dioxide layers in the mold. Form undercut edges in the doped silicon dioxide layers with the undoped silicon dioxide layers having cantilevered ribs projecting from the stacks into the cavity to complete the mold.

Abstract: A DRAM capacitor and a method for fabricating the same are disclosed. The method sequentially formed word lines, landing pads, first interpoly dielectric (IPD1)layer, bit line, and IPD2 layer, and then in terms of line masks, nitride cap nitride spacer and landing pad to serve as etching mask or stopping layer, and avoid the usage of a mask layer of storage node contact. Furthermore, the invention fully utilizes the etching selectively between IPD2 (BPSG) layer and IPD1 layer (densified TEOS) by an anhydrous HF to expand the space in an etched IPD2 layer to increase the capacitor area.

Abstract: An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell (100)). The cell can comprise a bitline contact (38), storage node contacts (32) hexagonally surrounding the bitline contact (38), storage nodes (36) also surrounding the bitline contact (38), a wordline (30) portions of which form field effect transistor gates. Large distances between bitline contacts (38) and storage node contact (32) cause large problems during photolithography because dark areas are difficult to achieve when using Levenson Phaseshift. Because Levenson Phaseshift depends on wave cancellations between nearby features, commonly known as destructive interferences, the resultant printability of the pattern is largely a function of the symmetry and separation distances. When non-symmetries in the pattern occur, the result is weaker cancellations of fields (i.e. between features) and a large loss of image contrast and depth of focus during the printing step.

Abstract: A capacitor includes a substrate, an insulating layer on the substrate, the insulating layer having a contact hole, a first storage node in the contact hole and on the insulating layer, a second storage node on a peripheral portion of the first storage node, the second storage node having a planar top surface, a dielectric layer on the surface of the first and second storage nodes, and a plate node on the dielectric layer.

Abstract: A method of forming a DRAM cell is disclosed. A heavily-doped region is formed in a semiconductor substrate. A first dielectric layer and a second dielectric layer are formed on the semiconductor substrate in sequence. A trench is next formed in the semiconductor substrate and also forming source/drain regions. First spacers with dopant source material are formed on sidewalls of the trench. After forming a gate dielectric layer within the trench, a first plug is formed on the gate dielectric layer. After forming an isolation film on the first plug and forming source/drain extensions, a second plug is formed on the isolation film. After removing the second dielectric layer, second spacers and third spacers are formed on sidewalls of the first spacers. After removing the second spacers and upper portions of the first spacers, a capacitor is formed on the transistor.

Abstract: In a process for forming a storage electrode having a number of hemi-spherical grains formed on a surface thereof, after a number of hemi-spherical grains are formed on a surface of the storage electrode, phosphorus or arsenic is ion-implanted to the hemi-spherical grains under an ion implantation energy of 20 keV to 50 keV.

Abstract: A method for fabricating a semiconductor device, wherein a dual damascene metal line is formed utilising a material layer pattern. The material layer pattern has openings to define contact holes both for metal interconnection in the peripheral region and for storage nodes in the cell array region. The material layer pattern is formed on an insulating layer. A second insulating layer is deposited on the material layer pattern. A groove mask pattern is formed and used as an etch stop while etching through the etching is performed at the another insulating layer and stopped at the material layer to form a first opening. Using the material layer pattern, exposed portions of the insulating layer are etched to form a second opening aligned to the first opening and thereby to form a dual damascene opening for a metal line. Metal is deposited in the first and second opening to form dual damascene metal lines.

Abstract: Disclosed herein is a method of forming a capacitor for a semiconductor memory device. The method comprises a step of:forming a lower electrode on the semiconductor substrate; forming an O3-oxide film on the lower electrode; forming Si—O—N bonds on the surface of the O3-oxide film; forming a TaON film on the Si—O—N bonds by a chemical vapor deposition of a Ta chemical vapor, an O2 gas and an NH3 gas; and forming an upper electrode on the TaON film.

Abstract: A capacitor having high capacitance using a silicon-containing conductive layer as a storage node, and a method for forming the same, are provided. The capacitor includes a storage node, an amorphous Al2O3 dielectric layer, and a plate node. The amorphous Al2O3 layer is formed by a method in which reactive vapor phase materials are supplied on the storage node, for example, an atomic layered deposition method. Also, the storage node is processed by rapid thermal nitridation before forming the amorphous Al2O3 layer. The amorphous Al2O3 layer is densified by annealing at approximately 850° C. after forming a plate node, to thereby realize the equivalent thickness of an oxide layer which approximates a theoretical value of 30 Å.

Abstract: Disclosed herein is a semiconductor memory device. In the semiconductor memory device, a transfer transistor having a drain region and a source region is formed on an Si semiconductor substrate. A lower end of a storage node is electrically connected to the drain region through a drain contact hole defined in an interlayer insulator. The storage node has an on-film extending portion which extends on an upper surface of the interlayer insulator, and a fin-shaped electrode portion which protrudes from the on-film extending portion. Structurally, the fin-shaped electrode portion is provided within a capacitor region so as to extend within a region smaller than the capacitor region and is spaced away from the on-film extending portion on the side of a bit line contact hole defined in the interlayer insulator.

Abstract: An electrically conductive structure, such as a capacitor is disclosed. A capacitor can be made by providing a space extending between a pair of gate stacks on a semiconductor substrate, the space exposing a charge conducting region on the semiconductor substrate. A BPSG layer is formed over the pair of gate stacks. A hard mask layer comprising alternating layers of doped polysilicon and undoped polysilicon is formed over the BPSG layer during a single deposition cycle of depositing polysilicon. Portions of the hard mask layer and the BPSG layer are selectively removed to form topographical structures extending above the gate stacks and having a trench therebetween. A spacer etch and a contact etch are performed to expose the charge conducting region. A doped polysilicon spacer is formed on the lateral side of each topographical structure. A second group of alternating layers of doped polysilicon and undoped polysilicon is formed over the topographical strictures and within the trenches.

Abstract: A method for producing capacitor-node contact plugs of a dynamic random access memory, comprising: providing a semiconductor substrate; forming at least one gate structure separated by a first isolation layer as a word line, and forming a source region and a drain region next to the word line; forming a second isolation layer to cover the first isolation layer, word line, source region, and drain region; forming a first landing pad, which passes through the second isolation layer and couples to the source region, wherein the first landing pad is offset a given distance along the word line; forming a third isolation layer to cover the second isolation layer and the first landing pad; forming a second landing pad coupled to the drain region through the second isolation layer and the third isolation layer; forming at least one bit line separated by a fourth isolation layer along the vertical direction to the word line, wherein the at least one bit line is coupled to the second landing pad; forming a fifth isolat

Abstract: A non-volatile memory (NVM) cell is fabricated by slightly modifying a conventional logic process. The NVM cell is fabricated by forming the gate electrode of an access transistor from a first conductive layer, and then forming a capacitor structure that contacts the gate electrode. In one embodiment, the capacitor structure is fabricated by forming a crown electrode of a capacitor structure from a second conductive layer, forming a dielectric layer over the crown electrode, and then forming an plate electrode over the dielectric layer from a third conductive layer. The crown electrode contacts the gate electrode, thereby providing an electrical connection between these electrodes. A first set of thermal cycles are performed during the formation of the capacitor structure. After the capacitor structure has been formed, P+ and/or N+ ion implantations are performed, thereby forming shallow junctions on the chip (e.g., a drain region of the access transistor).

Abstract: The invention advantageously provides a novel method for making self-aligned contacts on a semiconductor substrate. A gate electrode having a vertical sidewall and a protecting layer thereon is formed over the semiconductor substrate. A doped region is formed in the substrate adjacent to the gate electrode. An insulating sidewall spacer is formed on the sidewall of the gate electrode. A second doped region is formed in the substrate adjacent to the sidewall spacer. A second protecting layer is formed to cover or blanket the first protecting layer, the sidewall spacer, and the substrate. An interlayer insulting layer is provided on the second protecting layer in order to form a planer surface. The interlayer insulating layer and the second protecting layer are etched to expose the doped regions to form the self-aligned contacts.

Abstract: In a semiconductor memory device such as a DRAM, a conductive film is arranged on the rim portion of a isolation insulating film in opposition to a semiconductor substrate with a thin insulating film in between. This conductive film is electrically connected to a lower electrode of a storage capacitor. This novel arrangement can control the location of electrical pn junction independently of the location of metallurgical pn junction, thereby realizing a semiconductor memory device having a long data retention time with the increase in leakage current suppressed.

Abstract: In the preferred embodiment for forming a ragged polysilicon crown-shaped capacitor of a memory cell, a first dielectric layer is formed on a semiconductor substrate. A portion of the first dielectric layer is removed to define a contact hole within the first dielectric layer, wherein the contact hole is extended down to a source region in the substrate. Next, a conductive plug is formed and is communicated to the source region within the contact hole. A second dielectric layer is formed on the first dielectric layer and the conductive plug, and a third dielectric layer is formed on the second dielectric layer. Next, portions of the third dielectric layer and the second dielectric layer are removed to define a storage node opening, wherein the storage node opening is located over the conductive plug. A first conductive layer is then formed to conformably cover the inside surface of the storage node opening and on the third dielectric layer.

Abstract: In this DRAM, an SiO2 film for assuring the step coverage of cell-capacitor of cylinder type is left remained only in the peripheral circuit region. The capacitor upper electrode is formed extending from the memory cell array region to the peripheral circuit region. Since the capacitor upper electrode in the peripheral circuit region is disposed higher than the upper surface of the capacitor upper electrode which constitutes the cell-capacitor, this capacitor upper electrode in the peripheral circuit region is employed as a stopper for subsequently flattening the interlayer insulating film. Subsequently, the interlayer insulating film is employed as a mask for etching the capacitor upper electrode in the peripheral circuit region.

Abstract: A semiconductor device capacitor has a storage electrode wherein the impurity concentration decreases from the bottom to the top thereof. The semiconductor device capacitor is formed on a lower structure of a semiconductor substrate burying a contact hole formed on the semiconductor substrate. The impurity concentration linearly or non-linearly decreases going upward from the bottom of the contact hole to the top of the storage electrode. A method of manufacturing the semiconductor device capacitor also provides that the storage electrode is formed such that the concentration of impurities decreases linearly or non-linearly going upward from the bottom toward the top.

Abstract: A method for forming a lower electrode structure of a capacitor of a semiconductor device, includes the steps of: forming an active region in a semiconductor substrate; forming an insulation layer atop the semiconductor substrate having the active region formed therein; forming a contact hole in the insulation layer, the contact hole exposing the active region; forming a conductive plug connected to the active region through the contact hole, the conductive plug having an upper contact surface; forming a silicide contact on the upper contact surface of the conductive plug; forming a lower electrode layer in electrical contact with the silicide contact, by depositing titanium aluminum nitride on the insulation layer; and patterning the lower electrode layer to form a lower electrode having an upper surface. A natural oxide film is prevented from generating between the interface of the plug and the lower electrode.

Abstract: A method for making a semiconductor device is provided. In the method, an insulating layer is formed over a semiconductor substrate, and a groove is formed in the insulating layer. Then, a first conductive layer, a first mask layer, a second conductive layer, and a second mask layer are sequentially and conformably formed on an upper surface of the insulating layer and an inner surface of the groove to form a laminated layer. Afterwards, the laminated layer is anisotropically etched to form a multiple cylindrical structure in the groove, and a multiple cylindrical electrode is formed based on the multiple cylindrical structure. Subsequently, a dielectric layer and a plate electrode are sequentially formed on the multiple cylindrical electrode to create a capacitor.

Abstract: A semiconductor memory device comprises a memory cell region having an array of plurality of memory cells, and a peripheral circuit region to which a bit line connected to a predetermined number of the memory cells in the memory cell region is extended and connected, the bit line in the memory cell region and the bit line in the peripheral circuit region having substantially the same upper surface height.

Abstract: Semiconductor capacitor constructions, DRAM cell constructions, methods of forming semiconductor capacitor constructions, methods of forming DRAM cell constructions, and integrated circuits incorporating capacitor structures and DRAM cell structures are encompassed by the invention. The invention includes a method comprising: a) forming an opening within an insulative layer and over a node location; b) forming a spacer within the opening to narrow the opening, the spacer having inner and outer surfaces, the inner surface forming a periphery of the narrowed opening; c) removing a portion of the insulative layer from proximate the outer surface to expose at least a portion of the outer surface; d) forming a storage node layer in electrical connection with the node location, extending along the spacer inner surface, and extending along the exposed spacer outer surface; and e) forming a dielectric layer and a cell plate layer operatively proximate the storage node layer.

Abstract: In a process for forming a lower electrode of a cylindrical capacitor in a semiconductor memory, a polysilicon film is formed on an insulator film to cover an inner surface of a hole formed in the insulator film. An exposed surface of the polysilicon film is treated with a reaction accelerator which reacts with a positive photoresist to lower dissolubility of the positive photoresist to a developer liquid. The positive photoresist is deposited on the whole surface to fill up the hole. As a result, the positive photoresist filled up within the hole reacts with the reaction accelerator within the hole and becomes difficult to dissolve to the developer liquid even after the positive photoresist is exposed to light. The whole of the positive photoresist is exposed to light and then developed with the developer so that the positive photoresist remains only within the hole.

Abstract: A method of fabricating a bottom electrode is described. A first dielectric layer having a first opening is formed over a substrate. The first opening exposes a portion of a conductive layer in the substrate. A first liner layer is formed on a sidewall of the first opening. A conductive plug is formed in the opening. A plurality of bit lines are formed next to the first opening. A second liner layer is formed over the substrate to cover the bit lines, the first liner layer, and the conductive plug. A node contact opening is formed in the second liner layer to expose a portion of the conductive plug. A second dielectric layer is formed over the substrate. A second opening is formed in the second dielectric layer to expose the node contact opening and a portion of the second liner layer. A conformal conductive layer is formed in the opening.

Abstract: Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material. In another embodiment, a capacitor storage node is formed having an uppermost surface and a side surface joined therewith. A protective cap is formed over the uppe-most surface and a capacitor dielectric layer is formed over the side surface and protective cap. A cell electrode layer is formed over the side surface of the capacitor storage node.

Abstract: A container capacitor and method having an internal concentric fin. In one embodiment, the finned capacitor is a stacked container capacitor in a dynamic random access memory circuit. The finned container capacitor provides a high storage capacitance without increasing the size of the cell. The capacitor fabrication requires only two depositions, a spacer etch and a wet etch step in addition to conventional container capacitor fabrication steps.

Abstract: A new method is provided for the creation of a salicided polysilicon capacitor. A salicided layer of polysilicon is created as the lower plate of a salicided polysilicon capacitor over the surface of a field isolation region. A layer of silicon nitride is deposited over the field oxide isolation region including the surface of the salicided polysilicon layer. A layer of TEOS is deposited over the surface of the layer of silicon nitride, a layer if titanium nitride is deposited over the surface of the layer of TEOS. The layer of TiN is etched after which the layer of TEOS is etched. The etch of the layer of TEOS is an overetch whereby TEOS is symmetrically removed from underneath the etched layer of TiN, leaving remnants of TEOS in place underneath the etched layer of TiN while at the same time creating air gaps underneath the etched layer of TiN.

Abstract: A capacitor core is formed on a semiconductor device with a first conductive layer in contact with a plug. A mold is formed from a stack of alternately doped and undoped silicon dioxide layers on the sublayer with the stack comprising a bottom layer formed on top of the sublayer and each additional layer in the stack formed on a previous one of the layers in the stack. Pattern the silicon dioxide layers in the mold which are alternatingly doped and undoped to form an intercore, capacitor-core-shaping cavity in the stack of silicon dioxide layers reaching down through the stack to be bottom of the stack. Then perform differential etching of the silicon dioxide layers in the mold. Form undercut edges in the doped silicon dioxide layers with the undoped silicon dioxide layers having cantilevered ribs projecting from the stacks into the cavity to complete the mold.

Abstract: The present invention relates to a method of manufacturing a capacitor in a semiconductor device. It is designed to solve the problem due to oxidization of the surface of the underlying tungsten electrode during thermal process performed after depositing Ta2O5 to form a dielectric film in a Ta2O5 capacitor of a MIM (Metal Insulator Metal) structure using tungsten (W) as an underlying electrode. Thus, the present invention includes forming a good thin WO3 film by processing the surface of the underlying tungsten electrode by low oxidization process before forming a Ta2O5 dielectric film and then performing deposition and thermal process of Ta2O5 to form a Ta2O5 dielectric film. As a good WO3 film is formed on the surface of the underlying tungsten electrode before forming a Ta2O5 dielectric film, the grain boundary of the tungsten film is filled with oxygen atoms, thus preventing diffusion of oxygen atoms from the Ta2O5 dielectric film during a subsequent thermal process.

Abstract: A method of fabricating a contact node. A first dielectric layer is formed on the substrate. A second dielectric layer and a third dielectric layer are formed in sequence over the substrate. A portion of the first dielectric layer, the second dielectric layer, and the third dielectric layer are etched to form a contact opening which exposes a portion of the substrate. A conductive layer is formed in the contact opening. The third dielectric layer is removed to exposes a portion of the conductive layer.

Abstract: A method of manufacturing DRAM capacitor includes forming a tungsten plug to connect with the source/drain region of a silicon substrate and using tungsten to form the upper and lower electrodes of the capacitor. The tungsten lower electrode of this invention is formed by depositing tungsten over the substrate using a physical vapor deposition method, and then depositing tungsten again using a chemical vapor deposition method so that a roughened surface is produced. Consequently, the tungsten lower electrode has a greater surface area, thereby increasing the capacitance of the capacitor. In addition, tantalum pentoxide is used to form the dielectric layer. Since tantalum pentoxide has a high dielectric constant, the effective capacitance of the capacitor is further increased.

Abstract: A method of making a capacitor comprising providing a space extending between a pair of gate stacks on a semiconductor substrate, the space exposing a charge conducting region on the semiconductor substrate. A BPSG layer is formed over the pair of gate stacks. A hard mask layer comprising alternating layers of doped polysilicon and undoped polysilicon is formed over the BPSG layer during a single deposition cycle of depositing polysilicon. Portions of the hard mask layer and the BPSG layer are selectively removed to form topographical structures extending above the gate stacks and having a trench therebetween. A spacer etch and a contact etch are performed to expose the charge conducting region. A doped polysilicon spacer is formed on the lateral side of each topographical structure. A second group of alternating layers of doped polysilicon and undoped polysilicon is formed over the topographical structures and within the trench.

Abstract: A method for fabricating a semiconductor device includes the steps of depositing an amorphous silicon layer on a substrate, and forming an oxidation film on a surface of the amorphous silicon layer by treating the surface of the amorphous silicon layer with an oxidation gas. The forming step occurs before crystallization of the amorphous silicon layer.

Abstract: There is provided a method of manufacturing a semiconductor device having a MOS transistor formed on a silicon substrate, and a stacked capacitor constituted by an information storage electrode provided above the MOS transistor through an insulating interlayer and a counter-electrode separated from the information storage electrode due to the presence of a capacitor insulating film. In this method, the capacitor is formed by adding an impurity in a silicon oxide film which is formed on the insulating interlayer and used to shape the information storage electrode, and performing etching by using a chemical solution containing phosphoric acid, sulfuric acid, nitric acid, or a solution mixture thereof, or a chemical solution containing a solution mixture of an aqueous ammonia solution and a hydrogen peroxide solution to selectively remove the silicon oxide film added with the impurity.

Abstract: A capacitor for a semiconductor device including a lower electrode having a silicon layer with portions initially doped at different doping densities, a plurality of protrusions formed selectively on the lower electrode according to the different doping densities, a dielectric layer over the lower electrode and the protrusions, and an upper electrode over the dielectric layer. After the protrusions are formed, a step of additionally doping the lower electrode to increase the doping density thereof is not required. The silicon layer with portions initially doped at different doping densities allows the protrusions to form more easily, so that the entire surface area of the lower electrode is increased to thus minimize variations in capacitance.

Abstract: A process for fabricating a capacitor under bit line (CUM), DRAM device, featuring increased capacitance, without increasing the aspect ratio for a dry etched, narrow diameter bit line contact hole, has been developed. The process features increasing the vertical space in a capacitor opening, needed to accommodate a capacitor structure with increased vertical dimensions, via selective removal of the top portions of the polysilicon plug structures exposed in the capacitor openings. The depth of a subsequent bit line contact hole, opened to a non-truncated polysilicon plug structure, is therefore not increased as a result of the increase capacitor depth, thus not resulting in an increased aspect ratio for the dry etched, narrow diameter bit line contact hole.

Abstract: A method of manufacturing a crown-shaped DRAM capacitor. A silicon oxide layer and a silicon nitride layer are sequentially formed over a substrate. A conductive plug passing through the silicon oxide layer and the silicon nitride layer is formed. A first and a second dielectric layer are sequentially formed over the silicon nitride layer and the conductive plug. A first opening that exposes the conductive plug and a portion of the silicon nitride layer surrounding the plug is formed in the second and the first dielectric layer. A doped amorphous silicon layer conformal to the substrate profile is formed. The doped amorphous silicon layer above the second dielectric layer is removed. The second dielectric layer is next removed, and then hemispherical silicon grains (HSGs) are grown over the exposed surface of the doped amorphous silicon layer. The first dielectric layer is removed, and finally a third dielectric layer and a conductive layer are sequentially formed over the substrate.

Abstract: A semiconductor processing method of forming a capacitor construction includes, a) providing a pair of electrically conductive lines having respective electrically insulated outermost surfaces; b) providing a pair of sidewall spacers laterally outward of each of the pair of conductive lines; c) etching material over the pair of conductive lines between the respective pairs of sidewall spacers selectively relative to the sidewall spacers to form respective recesses over the pair of conductive lines relative to the sidewall spacers, the etching leaving the outermost conductive line surfaces electrically insulated; d) providing a node to which electrical connection to a capacitor is to be made between the pair of conductive lines, one sidewall spacer of each pair of sidewall spacers being closer to the node than the other sidewall spacer of each pair; e) providing an electrically conductive first capacitor plate layer over the node, the one sidewall spacers, and within the respective recesses; and f) providing a

Abstract: A method of forming a contact hole in a semiconductor device is provided wherein an oxide spacer is formed over a contact hole. The oxide contact hole spacer prevents an already-formed gate protecting spacer comprised of silicon nitride from being etched during a subsequent step of removing the already-formed silicon nitride etching stopper. After forming a gate stack having the protecting spacer, the silicon nitride etching stopper is formed. An interlayer insulating layer is formed thereon and a selected portion of the interlayer insulating layer is etched to form a contact hole. The oxide spacer is formed on both sidewalls of the contact hole and then the etching stopper silicon nitride layer is removed.