Abstract: Aspects of the disclosure include a method for making a semiconductor, including patterning a first transistor having one or more gate stacks on a first source-drain area and second transistor comprising one or more gate stacks on a second source-drain area, forming dielectric spacers on gate stack side walls, depositing a first nitride liner on the first and second transistors. The method also includes masking the second transistor and etching to remove the first nitride material and the spacer from the first source-drain area and growing a first epitaxial layer on the first source-drain area by an epitaxial growth process. The method also includes depositing a second nitride liner on the first and second transistors. The method also includes masking the first transistor. The method also includes etching to remove the second nitride material from the second source-drain area and growing a second epitaxial layer on the second source-drain area by an epitaxial growth process.

Abstract: A method of forming fins in a complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor (nFET) device and a CMOS device are described. The method includes forming a strained silicon-on-insulator (SSOI) layer in both a pFET region and an nFET region, etching the strained silicon layer, the insulator, and a portion of the bulk substrate in only the pFET region to expose the bulk substrate, epitaxially growing silicon (Si) from the bulk substrate in only the pFET region, and epitaxially growing additional semiconductor material on the Si in only the pFET region. The method also includes forming fins from the additional semiconductor material and a portion of the Si grown on the bulk substrate in the pFET region, and forming fins from the strained silicon layer and the insulator in the nFET region.

Abstract: A storage transistor for non-volatile memory can be fabricated to create controlled sharp polycrystalline silicon (polysilicon) edges. The edges concentrate the electric field in the storage transistor and are used to enhance tunneling between layers of polysilicon for both program and erase operations. The storage transistor includes first and second polysilicon layers and a tunneling dielectric layer between the first and second polysilicon layers, and the second polysilicon layer includes at least a first edge extending towards the first polysilicon layer.

Abstract: A method for fabricating a semiconductor device comprises forming a fin in a layer of III-V compound semiconductor material on a silicon-on-insulator substrate; forming a semiconductor extension on the fin, the semiconductor extension comprising a III-V compound semiconductor material that is different from a material forming the fin in the III-V compound semiconductor layer; forming a dummy gate structure and a spacer across and perpendicular to the fin; forming a source/drain layer on a top surface of the substrate adjacent to the dummy gate structure; planarizing the source/drain layer; removing the dummy gate structure to expose a portion of the semiconductor extension on the fin; removing the exposed portion of the semiconductor extension; etching the semiconductor extension to undercut the spacer; and forming a replacement gate structure in place of the removed dummy gate structure and removed exposed portion of the semiconductor extension.

Abstract: A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage is provided. For this, a first deposition film (2) of low concentration silicon carbide of a first conductivity type is formed on the surface of a high concentration silicon carbide substrate (1) of a first conductivity type. Formed on the first deposition film (2) is a second deposition film (31) that comprises a high concentration gate region of a second conductivity type, with a first region removed selectively. A third deposition film (32) formed on the second deposition film, which comprises a second region that is wider than the selectively removed first region, a high concentration source region (5) of a first conductivity type and a low concentration gate region (11) of a second conductivity type. A low concentration base region (4) of a first conductivity type is formed in contact with the first deposition film (2) in the first and second regions.

Abstract: In one embodiment, an apparatus includes a three dimensional structure comprising a semiconductor material, and at least one thin film in contact with at least one exterior surface of the three dimensional structure for inducing a strain in the structure, the thin film being characterized as providing at least one of: an induced strain of at least 0.05%, and an induced strain in at least 5% of a volume of the three dimensional structure. In another embodiment, a method includes forming a three dimensional structure comprising a semiconductor material, and depositing at least one thin film on at least one surface of the three dimensional structure for inducing a strain in the structure, the thin film being characterized as providing at least one of: an induced strain of at least 0.05%, and an induced strain in at least 5% of a volume of the structure.

Abstract: A method includes providing a substrate that underlies a layer of SiGe; forming a plurality of fins in the layer of SiGe. Each formed fin has a fin shape and fin location preserving hard mask layer on a top surface. The method also includes depositing Si on a first subset of the set of fins in what will be an nFET area; performing a Si—Ge inter-mixing process on the first subset of fins to reduce a concentration of Ge in the first subset while producing a Si—Ge intermix layer; removing the Si—Ge intermix layer leaving the first subset of fins having the reduced concentration of Ge, and forming a second subset of fins in what will be a pFET area. The second subset is also formed from the layer of SiGe and has a greater percentage of Ge than a percentage of Ge in the first subset of fins.

Abstract: Three-dimensional (3D) semiconductor devices are provided. The 3D semiconductor device includes a plurality of dummy pillars penetrating each cell pad of an electrode structure and the electrode structure disposed under each cell pad. Insulating patterns of a mold stack structure for formation of the electrode structure may be supported by the plurality of dummy pillars, so transformation and contact of the insulating patterns may be minimized or prevented.

Abstract: A super-junction trench MOSFET with closed cell layout having shielded gate is disclosed, wherein closed gate trenches surrounding a deep trench in each unit cell and the shielded gate disposed in the deep trench. Trenched source-body contacts are at least formed between the closed gate trenches and the deep trench. The deep trench has square, rectangular, circle or hexagon shape.

Abstract: A method for manufacturing a memory device, which can be configured as a 3D NAND flash memory, and includes a plurality of stacks of conductive strips, including even stacks and odd stacks having sidewalls. Some of the conductive strips in the stacks are configured as word lines. Data storage structures are disposed on the sidewalls of the even and odd stacks. Active pillars between corresponding even and odd stacks of conductive strips include even and odd semiconductor films connected at the bottom of the trench between the stacks, and have outside surfaces and inside surfaces. The outside surfaces contact the data storage structures on the sidewalls of the corresponding even and odd stacks forming a 3D array of memory cells; the inside surfaces are separated by an insulating structure that can include a gap. The semiconductor films can be thin-films having a U-shaped current path.

Abstract: A method of forming fins in a dual isolation complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor (nFET) device and a CMOS device with dual isolation are described. The CMOS device includes an n-type field effect transistor (nFET) region, the nFET region including one or more fins comprised of strained silicon, the one or fins in the nFET region being formed on an insulator. The CMOS device also includes a p-type field effect transistor (pFET) region, the pFET region including one or more fins comprised of silicon (Si) or silicon germanium (SiGe) on epitaxially grown silicon and including a shallow trench isolation (STI) fill to isolate the one or more fins of the pFET region from each other.

Abstract: Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend primarily along a first direction. The walls are spaced from one another by trenches that extend primarily along the first direction. Steps are formed along bottoms of the trenches. Gatelines are formed on the steps and along lower regions of the walls. After the gatelines are formed, the walls are patterned into spaced-apart pillars that have bottom regions below the gatelines. In some embodiments the gated devices may be transistors or thyristors.

Abstract: In a semiconductor device and a method of forming such a device, the semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers is provided on the substrate. A plurality of gate patterns is provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel, the vertical channel being in contact with the substrate at a contact region that comprises a semiconducting region.

Abstract: A method of making a circuit structure includes growing a bulk layer over a substrate, and growing a donor-supply layer over the bulk layer. The method further includes depositing a doped layer over the donor-supply layer, and patterning the doped layer to form a plurality of islands. The method further includes forming a gate structure over the donor-supply layer, wherein the gate structure is partially over a largest island of the plurality of islands. The method further includes forming a drain over the donor-supply layer, wherein at least one island of the plurality of islands is between the gate structure and the drain.

Abstract: Disclosed herein is a semiconductor device that comprises a plug including an upper portion, a lower portion and a side surface and comprising tungsten, a barrier metal comprising tungsten nitride and covering the side surface and the lower portion of the contact plug, a conductive layer, and a barrier layer comprising titanium and intervening between the barrier metal and the first conductive layer.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type made of silicon carbide; and a second semiconductor layer of a second conductivity type made of silicon carbide, placed in junction with the first semiconductor layer, and containing an electrically inactive element.

Abstract: A method, and the resulting structure, of forming two fins with different types of strain and material on the same substrate.

Abstract: A memory array and a method for electrically coupling memory cell access devices to a word line. The memory array includes a source line electrically coupled to each source terminal of the memory cell access devices. The memory array also includes a first set of at least two vertical pillars positioned above and electrically coupled to the source line. A second set of vertical pillars electrically isolated from the source line and positioned such that the source line does not extend below the second set of vertical pillars is also included. Furthermore, gate terminals of the memory cell access devices laterally surround the first set of vertical pillars and the second set of vertical pillars. Finally, a first word line contact is positioned between two of the second set of vertical pillars. The first word line contact is electrically coupled to the gate terminals.

Abstract: A semiconductor device includes at least one field effect transistor structure, which is formed on a semiconductor substrate. The field effect transistor structure includes a drift region, a body region, a source region and a gate. The source region and the drift region include at least mainly a first conductivity type, wherein the body region includes at least mainly a second conductivity type. The body region includes at least one low doping dose portion extending from the drift region to at least one of the source region or an electrical contact interface of the body region at a main surface of the semiconductor substrate, wherein a doping dose within the low doping dose portion of the body region is less than 3 times a breakdown charge.

Abstract: A super-junction trench MOSFET with closed cell layout is disclosed, wherein closed gate trenches surrounding a deep trench in each unit cell. Trenched source-body contacts are disposed between the closed gate trenches and the deep trench. The deep trench has square, rectangular, circle or hexagon shape.

Abstract: A gated diode may include source zones and a drain zone which are both of a first conductivity type. The source zones directly adjoin a first surface of a semiconductor die and the drain zone directly adjoins an opposite second surface of the semiconductor die. The drain zone includes a drift zone formed in an epitaxial layer of the semiconductor die. Base zones of a second conductivity type, which is the opposite of the first conductivity type, are provided between the drain zones and the source zones. The drift zone further includes adjustment zones directly adjoining a base zone and arranged between the respective base zone and the second surface, respectively. A net dopant concentration in the adjustment zone is at least twice a net dopant concentration in the second sub-zone. The adjustment zones precisely define the reverse breakdown voltage.

Abstract: An IGBT includes a trench gate electrode that is bent when a semiconductor substrate is seen in a plan view, and an inner semiconductor region of the same conductivity type as an emitter region is formed at a position inside a bent portion of the trench gate electrode and exposed on a front surface of the semiconductor substrate. The trench gate electrode is bent, and therefore, a hole density during operation increases, whereby conductivity modulation phenomenon is accelerated, and an on-state voltage is reduced. When the IGBT is turned off, the inner semiconductor region influences a movement path of the holes so that a moving distance thereof through a body region becomes short. The holes escape easily to a body contact region when the IGBT is turned off. Increase of current density during the operation and prevention of a latchup are both achieved.

Abstract: According to an exemplary embodiment, a method of forming a vertical structure with at least two barrier layers is provided. The method includes the following operations: providing a substrate; providing a vertical structure over the substrate; providing a first barrier layer over a source, a channel, and a drain of the vertical structure; and providing a second barrier layer over a gate and the drain of the vertical structure.

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.

Abstract: A memory array and a method for electrically coupling memory cell access devices to a word line. The memory array includes a source line electrically coupled to each source terminal of the memory cell access devices. The memory array also includes a first set of at least two vertical pillars positioned above and electrically coupled to the source line. A second set of vertical pillars electrically isolated from the source line and positioned such that the source line does not extend below the second set of vertical pillars is also included. Furthermore, gate terminals of the memory cell access devices laterally surround the first set of vertical pillars and the second set of vertical pillars. Finally, a first word line contact is positioned between two of the second set of vertical pillars. The first word line contact is electrically coupled to the gate terminals.

Abstract: A super-junction trench MOSFET is disclosed by applying a first doped column region of first conductivity type between a pair of second doped column regions of second conductivity type adjacent to sidewalls of a pair of deep trenches with buried voids in each unit cell for super-junction. A buffer poly-silicon layer is deposited above the buried void for stress release to prevent wafer crack and silicon defects.

Abstract: A method for making a semiconductor device may include forming, on a substrate, at least one stack of alternating first and second semiconductor layers. The first semiconductor layer may comprise a first semiconductor material and the second semiconductor layer may comprise a second semiconductor material. The first semiconductor material may be selectively etchable with respect to the second semiconductor material. The method may further include removing portions of the at least one stack and substrate to define exposed sidewalls thereof, forming respective spacers on the exposed sidewalls, etching recesses through the at least one stack and substrate to define a plurality of spaced apart pillars, selectively etching the first semiconductor material from the plurality of pillars leaving second semiconductor material structures supported at opposing ends by respective spacers, and forming at least one gate adjacent the second semiconductor material structures.

Abstract: A silicon carbide device includes a silicon carbide substrate, an inorganic passivation layer structure and a molding material layer. The inorganic passivation layer structure laterally covers at least partly a main surface of the silicon carbide substrate and the molding material layer is arranged adjacent to the inorganic passivation layer structure.

Abstract: There is provided a solid-state image device, including a semiconductor substrate, a circuit formed on a first face of the semiconductor substrate, a grid pattern provided on a second face of the semiconductor substrate, and a semiconductor layer formed within the grid pattern and having a shape whose cross-sectional surface area in a plane parallel to a surface of the semiconductor substrate decreases with increasing distance from the semiconductor substrate.

Abstract: A 3D semiconductor integrated circuit having a gate pick-up line and a method of manufacturing the same, wherein the semiconductor integrated circuit includes a plurality of active pillars formed in a gate pick-up region, buffer layers formed on the respective active pillars in the gate pick-up region, gates each surrounding an outer circumference of the corresponding active pillar and the corresponding buffer layer, and a gate pick-up line electrically coupled to the gates.

Abstract: A semiconductor device includes a fin-shaped silicon layer and a pillar-shaped silicon layer on the fin-shaped silicon layer, where a width of the pillar-shaped silicon layer is equal to a width of the fin-shaped silicon layer. Diffusion layers reside in upper portions of the pillar-shaped silicon layer and fin-shaped silicon layer and in a lower portion of the pillar-shaped silicon layer to form. A gate insulating film and a metal gate electrode are around the pillar-shaped silicon layer and a metal gate line extends in a direction perpendicular to the fin-shaped silicon layer and is connected to the metal gate electrode. A contact resides on the metal gate line and a nitride film is on an entire top surface of the metal gate electrode and the metal gate line, except for the bottom of the contact.

Abstract: In one embodiment, a method of making a VDMOS transistor can include: (i) etching an oxide layer formed on a surface of an epitaxial structure to define an active region of the VDMOS; (ii) injecting and diffusing a first dopant into the active region to form a doping region; (iii) forming a gate oxide layer on the active region; (iv) depositing polysilicon on the gate oxide layer, and etching the polysilicon to form a gate; (v) injecting a second dopant at an end of the gate to form a source, where the first and second dopants have opposite types; (vi) forming a contact hole adjacent to the gate, and injecting a third dopant into the contact hole, where the first and third dopants have a same type; (vii) depositing and etching aluminum on a chip surface; and (viii) coating the aluminum and chip surface with a passivation layer.

Abstract: A 3D semiconductor integrated circuit having a gate pick-up line and a method of manufacturing the same, wherein the semiconductor integrated circuit includes a plurality of active pillars formed in a gate pick-up region, buffer layers formed on the respective active pillars in the gate pick-up region, gates each surrounding an outer circumference of the corresponding active pillar and the corresponding buffer layer, and a gate pick-up line electrically coupled to the gates.

Abstract: One method disclosed includes, among other things, forming a raised isolation post structure between first and second fins, wherein the raised isolation post structure partially defines first and second spaces between the first and second fins, respectively, and forming a gate structure around the first and second fins and the raised isolation post structure, wherein at least portions of the gate structure are positioned in the first and second spaces. One illustrative device includes, among other things, first and second fins, a raised isolation post structure positioned between the first and second fins, first and second spaces defined by the fins and the raised isolation post structure, and a gate structure positioned around a portion of the fins and the isolation post structure.

Abstract: A semiconductor device includes: a first conductivity type semiconductor substrate; and a plurality of second conductivity type semiconductor regions, the respective second conductivity type semiconductor regions being embedded in a plurality of stripe shaped trenches formed in the semiconductor substrate so that the respective second conductivity type semiconductor regions are extended in the row direction or the column direction in parallel with a first principal surface of the semiconductor substrate and are spaced in a fixed gap mutually. The semiconductor substrate and the plurality of the semiconductor regions are depleted by a depletion layer extended in the direction in parallel to the first principal surface from a plurality of pn junction interfaces, and the respective pn junction interfaces are formed between the semiconductor substrate and the plurality of the semiconductor regions.

Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.

Abstract: Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material.

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

Abstract: A semiconductor device includes semiconductor mesas of a first conductivity type extending between a first surface and a bottom plane of a semiconductor portion, and a semiconductor structure of a second, complementary conductivity type extending along sidewalls of the semiconductor mesas and outwardly from the semiconductor mesas. A thickness of the semiconductor structure has a local maximum value at a first distance to both the first surface and the bottom plane.

Abstract: A semiconductor device includes a buried layer in a substrate, the buried layer having a first dopant type. The semiconductor device further includes a first layer over the buried layer, the first layer having the first dopant type. The semiconductor device further includes at least one first well in the first layer, the at least one first well having a second dopant type. The semiconductor device further includes an implantation region in a sidewall of the first layer, the implantation region having the second dopant type, wherein the implantation region is below the at least one first well. The semiconductor device further includes a metal electrode extending from the buried layer to a drain contact, wherein the metal electrode is insulated from the first layer and the at least one first well by an insulation layer.

Abstract: A semiconductor device includes a fin-shaped silicon layer and a pillar-shaped silicon layer on the fin-shaped silicon layer, where a width of a bottom part of the pillar-shaped silicon layer is equal to a width of a top part of the fin-shaped silicon layer. A gate insulating film and a metal gate electrode are around the pillar-shaped silicon layer and a metal gate line extends in a direction perpendicular to the fin-shaped silicon layer and is connected to the metal gate electrode. A nitride film is on an entire top surface of the metal gate electrode and the metal gate line, except for the bottom of a contact.

Abstract: A dual-gate transistor having a negative differential resistance (NDR) region is disclosed. The dual-gate transistor includes a back-gate, a zero-bandgap graphene layer disposed on the back-gate, a top-gate disposed on a portion of the zero-bandgap graphene layer adjacent to the top-gate, and a drain disposed on a portion of the zero-bandgap graphene layer adjacent to the top-gate and displaced from the source. Also included is a dynamic bias controller configured to simultaneously sweep a source-drain voltage and a top-gate voltage across a Dirac point to provide operation within the NDR region. Operation within the NDR region is employed to realize non-Boolean logic functions. Graphene-based non-Boolean logic circuits are constructed from pluralities of the disclosed dual-gate transistor. Pattern recognition circuitry for operation between 100 GHz and 500 GHz is also disclosed via the graphene-based non-Boolean logic circuits.

Abstract: Some embodiments include a semiconductor construction having a stack containing alternating levels of control gate material and intervening dielectric material. A channel material panel extends through the stack and along a first direction. The panel divides the stack into a first section on a first side of the panel and a second section on a second side of the panel. Memory cell stacks are between the channel material panel and the control gate material. The memory cell stacks include cell dielectric material shaped as containers having open ends pointing toward the channel material panel, and include charge-storage material within the containers. Some embodiments include methods of forming semiconductor constructions.

Abstract: A method for forming a semiconductor device includes providing a semiconductor body which has a main surface and a first n-type semiconductor region, forming a trench which extends from the main surface into the first n-type semiconductor region, and forming a dielectric layer having fixed negative charges on a surface of the trench, by performing at least one atomic layer deposition using an organometallic precursor.

Abstract: A semiconductor component is produced by forming a trench in a semiconductor region. The trench has an upper trench region and a lower trench region. The upper trench region is wider than the lower trench region such that a step is formed in the semiconductor region. A dopant is introduced into the step to form a locally delimited dopant region in the semiconductor region.

Abstract: In a 3D nonvolatile memory with memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes from a bottom plane to a top plane stacked in the z-direction over a semiconductor substrate; a plurality of local bit lines elongated in the z-direction through the plurality of layers and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; the 3D nonvolatile memory further having a plurality of staircase word lines spaced apart in the y-direction and between and separated from the plurality of bit line pillars at a plurality of crossings, individual staircase word lines each having a series of alternating steps and risers elongated respectively in the x-direction and z-direction traversing across the plurality of planes in the z-direction with a segment in each plane.

Abstract: A superjunction semiconductor device is disclosed in which the tradeoff relationship between on-resistance and breakdown voltage is improved greatly so that reverse recovery capability is improved. A drain drift portion substantially corresponds to a portion just under p-base regions serving as an active region and forms a first parallel pn structure in which a first n-type region and a first p-type region are joined to each other alternately and repeatedly. A drain drift portion is surrounded by edge termination region including a second parallel pn structure. Edge termination region is formed such that second n-type and p-type regions oriented consecutively to the first parallel pn structure of the drain drift portion are joined to each other alternately and repeatedly. N-buffer layer is provided between first and second parallel pn structures and n+ drain layer. P-buffer layer is provided selectively inside n-buffer layer in edge termination region.

Abstract: A method to fabricate a three dimensional memory structure includes forming an array stack, creating a layer of sacrificial material above the array stack, etching a hole through the layer of sacrificial material and the array stack, creating a pillar of semiconductor material in the hole to form at least two vertically stacked flash memory cells that use the pillar as a common body, removing at least some of the layer of sacrificial material around the pillar to expose a portion of the pillar, and forming a field effect transistor (FET) using the portion of the pillar as the body of the FET.

Abstract: A semiconductor device includes a first fin-shaped semiconductor layer on a semiconductor substrate, a first insulating film around the first fin-shaped semiconductor layer, a first pillar-shaped semiconductor layer on the first fin-shaped semiconductor layer, a first gate insulating film around the first pillar-shaped semiconductor layer, a first gate line formed around the first gate insulating film and extending in a direction perpendicular to the first fin-shaped semiconductor layer, a second diffusion layer disposed in a lower portion of the first pillar-shaped semiconductor layer, a third gate insulating film surrounding an upper portion of the first pillar-shaped semiconductor layer, a first contact electrode surrounding the third gate insulating film, a second contact electrode that connects an upper portion of the first contact electrode to an upper portion of the first pillar-shaped semiconductor layer, and a first magnetic tunnel junction memory element on the second contact electrode.

Abstract: Methods of forming an array of memory cells and memory cells that have pillars. Individual pillars can have a semiconductor post formed of a bulk semiconductor material and a sacrificial cap on the semiconductor post. Source regions can be between columns of the pillars, and gate lines extend along a column of pillars and are spaced apart from corresponding source regions. Each gate line surrounds a portion of the semiconductor posts along a column of pillars. The sacrificial cap structure can be selectively removed to thereby form self-aligned openings that expose a top portion of corresponding semiconductor posts. Individual drain contacts formed in the self-aligned openings are electrically connected to corresponding semiconductor posts.