Abstract: NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a method for forming an NMOS transistor may include providing a substrate having a p-type silicon region and a gate stack disposed thereon, the gate stack partially defining a source and a drain region; depositing an undoped first silicon layer having a lattice adjusting element atop the p-type silicon region and within the source and the drain regions; and depositing a second silicon layer having a lattice adjusting element and an n-type dopant atop the undoped first silicon layer.

Abstract: A method of forming ultra-shallow p-type lightly doped drain (LDD) regions of a PMOS transistor in a surface of a substrate includes the steps of providing a gaseous mixture of an inert gas, a boron-containing source, and an optional carbon-containing source, wherein the concentration of the gaseous mixture is at least 99.5% dilute with the inert gas and the optional carbon-containing source, if present, forming the gaseous mixture into a plasma, and forming the LDD regions, wherein the forming step includes plasma-doping the boron into the substrate using the plasma. N-type pocket regions are formed in the substrate underneath and adjacent to the LDD regions, wherein for a PMOS transistor having a threshold voltage of 100 mV, the n-type pocket regions include phosphorous impurities at a dopant concentration of less than 6.0×1018 atoms/cm3 or a proportionately lower/higher dopant concentration for a lower/higher threshold voltage.

Abstract: A method produces a semiconductor by conducting superimposed doping of a plurality of dopants in a semiconductor substrate, which includes evaporating a (2×n) structure by a first dopant and forming its thin line structure on the substrate, then bringing the semiconductor substrate to a temperature capable of epitaxial growth, vapor depositing a second or third or subsequent dopants above the semiconductor substrate where the first dopant has been deposited, then epitaxially growing a semiconductor crystal layer over the semiconductor substrate, subsequently forming a superimposed doping layer composed of the first, second, or the third or subsequent dopants in the semiconductor substrate, and applying an annealing treatment to the superimposed doping layer at a high temperature, thereby activating the plurality of dopants electrically or optically. Superimposed doping of a plurality kinds of elements as dopants is performed to a predetermined depth in the case of an elemental semiconductor.

Abstract: A method of growing polygonal carbon from photoresist and resulting structures are disclosed. Embodiments of the invention provide a way to produce polygonal carbon, such as graphene, by energizing semiconductor photoresist. The polygonal carbon can then be used for conductive paths in a finished semiconductor device, to replace the channel layers in MOSFET devices on a silicon carbide base, or any other purpose for which graphene or graphene-like carbon material formed on a substrate is suited. In some embodiments, the photoresist layer forms both the polygonal carbon layer and an amorphous carbon layer over the polygonal carbon layer, and the amorphous carbon layer is removed to leave the polygonal carbon on the substrate.

Abstract: When forming sophisticated high-k metal gate electrode structures, the removal of a dielectric cap material may be accomplished with superior process uniformity by using a silicon dioxide material. In other illustrative embodiments, an enhanced spacer regime may be applied, thereby also providing superior implantation conditions for forming drain and source extension regions and drain and source regions.

Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a first ion implantation process to implant a first molecular cluster having carbon, boron, and hydrogen into the semiconductor substrate at two sides of the gate structure for forming a doped region, wherein the molecular weight of the first molecular cluster is greater than 100.

Abstract: A semiconductor device includes a first pocket region and a second pocket region. The source region includes a first extension region having a concentration peak located at a first depth from a surface of the semiconductor substrate, and the first pocket region has a concentration peak located deeper than the first depth, and the drain region includes a second extension region having a concentration peak located at a second depth from the surface of the semiconductor substrate, and the second pocket region has a concentration peak located shallower than the second depth.

Abstract: Methods of forming transistors and transistors are disclosed, such as a transistor having a gate dielectric over a semiconductor having a first conductivity type, a control gate over the gate dielectric, source and drain regions having a second conductivity type in the semiconductor having the first conductivity type, and strips having the second conductivity type within the semiconductor having the first conductivity type and interposed between the control gate and at least one of the source and drain regions.

Abstract: A method for forming a lightly doped drain (LDD) region in a semiconductor substrate. The method includes generating an ion beam of a selected species, and accelerating the ion beam, wherein the accelerated ion beam includes a first accelerated portion and a second accelerated portion. The method further includes deflecting the accelerating ion beam, wherein the first and second accelerated portions are concurrently deflected into a first path trajectory having a first deflected angle and second path trajectory having a second deflected angle. In an embodiment, the first and second path trajectories travel in the same direction, which is perpendicular to the surface region of the semiconductor wafer, and the first deflected angle is greater than the second deflected angle. In an embodiment, the selected species may include an n-type ion comprising phosphorous (P), arsenic (As), or antimony (Sb).

Abstract: An integrated circuit (IC) includes at least one NMOS transistor, wherein the NMOS transistor includes a substrate having a semiconductor surface, and a gate stack formed in or on the surface including a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region are on opposing sides of the gate stack. An In region having a retrograde profile is under at least a portion of the channel region. The retrograde profile includes (i) a surface In concentration at a semiconductor surface interface with the gate dielectric of less than 5×1016 cm?3, (ii) a peak In concentration at least 20 nm from the semiconductor surface below the gate dielectric, and wherein (iii) the peak In concentration is at least two (2) orders of magnitude higher than the In concentration at the semiconductor surface interface.

Abstract: Dielectric cap layers of sophisticated high-k metal gate electrode structures may be efficiently removed on the basis of a sacrificial fill material, thereby reliably preserving integrity of a protective sidewall spacer structure, which in turn may result in superior uniformity of the threshold voltage of the transistors. The sacrificial fill material may be provided in the form of an organic material that may be reduced in thickness on the basis of a wet developing process, thereby enabling a high degree of process controllability.

Abstract: In one aspect provides a method of manufacturing a semiconductor device having improved transistor performance. In one aspect, this improvement is achieved by conducting a pre-deposition spacer deposition process wherein a temperature of a bottom region of a furnace is higher than a temperature of in the top region and is maintained for a predetermined period. The pre-deposition temperature is changed to a deposition temperature, wherein a temperature of the bottom region is lower than a temperature of the top region.

Abstract: Methods of manufacturing a semiconductor device include forming a gate electrode on a semiconductor substrate, forming spacers on side walls of the gate electrode, and doping impurities into the semiconductor substrate on both sides of the spacers to form highly doped impurity regions. The spacers are selectively etched to expose portions of the semiconductor substrate, and more lightly doped impurity regions are formed in the semiconductor substrate between the highly doped impurity regions and the gate electrode.

Abstract: A semiconductor device including a control terminal sidewall spacer structure made of a high-K dielectric material. The semiconductor device includes a control terminal where the spacer structure is a sidewall spacer structure for the control terminal. The semiconductor device includes current terminal regions located in a substrate. In some examples, the spacer structure has a height that is less than the height of the control terminal. In some examples, the spacer structure includes portions located over the regions of the substrate between the first current terminal region and the second current terminal region.

Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

Abstract: A method of forming ultra-shallow p-type lightly doped drain (LDD) regions of a PMOS transistor in a surface of a substrate includes the steps of providing a gaseous mixture of an inert gas, a boron-containing source, and an optional carbon-containing source, wherein the concentration of the gaseous mixture is at least 99.5% dilute with the inert gas and the optional carbon-containing source, if present, forming the gaseous mixture into a plasma, and forming the LDD regions, wherein the forming step includes plasma-doping the boron into the substrate using the plasma. N-type pocket regions are formed in the substrate underneath and adjacent to the LDD regions, wherein for a PMOS transistor having a threshold voltage of 100 mV, the n-type pocket regions include phosphorous impurities at a dopant concentration of less than 6.0×1018 atoms/cm3 or a proportionately lower/higher dopant concentration for a lower/higher threshold voltage.

Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed.

Abstract: When forming a sophisticated high-k metal gate stack in an early manufacturing stage, the dielectric cap layer may be efficiently removed without unduly affecting the drain and source extension regions. To this end, a specifically designed sidewall spacer structure may be used, such as a silicon dioxide spacer element in combination with a silicon nitride etch stop liner. The spacer structure may thus enable the removal of the dielectric cap layer while still maintaining the functions of an implantation mask and a silicidation mask during the further processing.

Abstract: Provided is that the method of manufacturing the semiconductor device including a first process of implanting a first impurity of a first conductivity type in a source and drain region having an elevated structure, with a concentration equal to or less than 1E14 atoms/cm2, on the conditions that the concentration peak thereof is located more deeply than the interface between silicide and a semiconductor substrate, a second process of implanting a second impurity of a first conductivity type having a smaller mass than that of the first impurity in the source and drain region on the conditions that the peak thereof is located more shallowly than the concentration peak of the first impurity, and a third process of applying high-temperature millisecond annealing to the semiconductor substrate after the first and second processes.

Abstract: A method of forming a small geometry feature. The method includes forming a source layer on a top surface of a substrate; forming a mandrel on a top surface of the source layer, the mandrel having a sidewall; sputtering material from the source layer onto the sidewall of the mandrel to form a sidewall layer on the sidewall of the mandrel; and removing the mandrel. Also methods to forming wires and field effect transistors of integrated circuits.

Abstract: An electrostatic discharge protection device is disclosed. The electrostatic discharge protection device preferably includes a first transistor, a second transistor, and an electrostatic discharge clamping circuit. The first transistor includes a first drain electrically connected to an input/output pin of a chip, a first source electrically connected to a first voltage input pin of the chip, and a first gate. The first drain is preferably an internally shrunk drain. The second transistor includes a second drain electrically connected to the input/output pin of the chip, a second source electrically connected to a second voltage input pin and a second gate. The electrostatic discharge clamping circuit is electrically connected to the first voltage input pin and the second voltage input pin.

Abstract: A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing process is performed to activate the dopants within the source/drain region. An etching process is performed to form a recess around the gate structure and a selective epitaxial growth process is performed to form an epitaxial layer in the recess. A second rapid thermal annealing process is performed to redefine the distribution of the dopants within the source/drain region and repair the damaged bonds of the dopants.

Abstract: A transistor structure is formed by providing a semiconductor substrate and providing a gate above the semiconductor substrate. The gate is separated from the semiconductor substrate by a gate insulating layer. A source and a drain are provided adjacent the gate to define a transistor channel underlying the gate and separated from the gate by the gate insulating layer. A barrier layer is formed by applying nitrogen or carbon on opposing outer vertical sides of the transistor channel between the transistor channel and each of the source and the drain. In each of the nitrogen and the carbon embodiments, the vertical channel barrier retards diffusion of the source/drain dopant species into the transistor channel. There are methods for forming the transistor structure.

Abstract: By forming a single spacer element and reducing the size thereof by a well-controllable etch process, a complex lateral dopant profile may be obtained at reduced process complexity compared to conventional triple spacer approaches in forming drain and source regions of advanced MOS transistors.

Abstract: The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.

Abstract: A semiconductor device and a method for manufacturing the same substantially prevent the degradation of the reliability and characteristics due to hot carriers by using a high-k dielectric material as a gate sidewall spacer material of a gate structure.

Abstract: Ni silicide is formed through simple steps. After forming a semiconductor film over a substrate, a Ni film is deposited over the semiconductor film while heating the substrate, thereby forming Ni silicide on the semiconductor film. Alternatively, after forming a semiconductor film over a substrate, a Ni film is deposited over the semiconductor film while heating the substrate up to 450° C. or higher, thereby forming Ni silicide on the semiconductor film. Alternatively, after forming a semiconductor film over a substrate, a Ni film is deposited with a thickness of 10 nm or more over the semiconductor film while heating the substrate to 450° C. or higher, thereby forming Ni silicide on the semiconductor film. Alternatively, after forming a semiconductor film over a substrate, and removing an oxide film on the semiconductor film, a Ni film is deposited over the semiconductor film while heating the substrate up to 450° C. or higher, thereby forming Ni silicide on the semiconductor film.

Abstract: A method of manufacturing a semiconductor device includes forming a first mask pattern exposing a first region for forming a first transistor and a second region for forming a second transistor, performing a first ion implantation for forming well regions using the first mask pattern, performing a second ion implantation for threshold voltage (Vth) adjustment of the first transistor using the first mask pattern, removing the first mask pattern and forming a second mask pattern in which the first region is covered and the second region is opened, performing a third ion implantation for Vth adjustment of the second transistor using the second mask pattern, forming first and second gate insulating films in the first and second regions respectively, and forming first and second gate electrodes in the first and second regions respectively.

Abstract: A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.

Abstract: An integrated circuit (IC) includes a plurality of compressively strained PMOS transistors. The IC includes a substrate having a semiconductor surface. A gate stack is formed in or on the semiconductor surface and includes a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region is opposing sides of the gate stack. At least one compressive strain inducing region including at least one specie selected from Ge, Sn and Pb is located in at least a portion of the source and drain regions of the PMOS transistors, wherein the strain inducing region provides ?1010 dislocation lines/cm2 and an active concentration of the compressive strain inducing specie that is above a solid solubility limit for the compressive strain inducing specie in the compressive strain inducing region.

Abstract: A semiconductor device includes a first conductivity-type deep well formed in a substrate, a plurality of device isolation layers formed in the substrate in which the first conductivity-type deep well is formed, a second conductivity-type well formed on a portion of the first conductivity-type deep well between two of the device isolation layers, a first gate pattern formed over a portion of the second conductivity-type well, a second gate pattern formed over one of the device isolation layers, a source region formed in an upper surface of the second conductivity-type well to adjoin a first side of the first gate pattern, a first drain region formed to include the interface between an upper surface of the second conductivity-type well adjoining a second side of the first gate pattern and an upper surface of the first conductivity-type deep well adjoining the second side of the first gate pattern, and a second drain region formed in an upper surface of the first conductivity-type deep well to be spaced from th

Abstract: By selectively applying a stress memorization technique to N-channel transistors, a significant improvement of transistor performance may be achieved. High selectivity in applying the stress memorization approach may be accomplished by substantially maintaining the crystalline state of the P-channel transistors while annealing the N-channel transistors in the presence of an appropriate material layer which may not to be patterned prior to the anneal process, thereby avoiding additional lithography and masking steps.

Abstract: A semiconductor device includes: a semiconductor substrate in which a SiGe layer having a first width in a channel direction is embedded in a channel forming region; gate insulating film formed on the channel forming region; a gate electrode formed on the gate insulating film and having a region protruding from a forming region of the SiGe layer with a second width wider than the first width; and source/drain regions having extension regions formed on the semiconductor substrate which sandwiches the channel forming region, thereby forming a field effect transistor, wherein the extension region is apart from the SiGe layer so that a depletion layer extending from a junction surface between the extension region and the semiconductor substrate does not reach the SiGe layer.

Abstract: A first transistor includes a first gate insulating film, a first gate electrode, and a first sidewall. A second transistor includes a second gate insulating film, a second gate electrode, and a second sidewall. A capacitive element is connected to one side of source and drain regions of the second transistor. The first gate insulating film has the same thickness as that of the second gate insulating film, and the first gate electrode has the same thickness of that of the second gate electrode. The width of the second sidewall is larger than the width of the first sidewall.

Abstract: A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer.

Abstract: A semiconductor device improves a Schottky-barrier field-effect transistor. In a semiconductor device including a gate electrode formed with interposition of a gate insulating film on a channel formed on a semiconductor substrate, and a Schottky source/drain formed within a top surface of the substrate to be positioned on both sides of the gate insulating film so that end portions of the Schottky source and the Schottky drain do not cover a lower end portion of the gate insulating film and so as to form Schottky junctions with the semiconductor substrate, a Schottky barrier height at an interface between the end portion of the Schottky source and the semiconductor substrate and a Schottky barrier height at an interface between the end portion of the Schottky drain and the semiconductor substrate are different from Schottky barrier heights at interfaces between portions except the end portions of the Schottky source/drain and the substrate.

Abstract: A method of forming an integrated circuit includes providing a semiconductor wafer, and forming a metal-oxide-semiconductor (MOS) device. The step of forming the MOS device includes forming a gate stack on the semiconductor wafer, and performing a cryo-implantation to form an implantation region adjacent the gate stack at a wafer temperature lower than 0° C.

Abstract: An improved source/drain junction configuration in a metal-oxide semiconductor transistor is provided, as well as a novel method for fabricating this junction. This configuration employs gate double sidewall spacers in the peripheral region and gate single sidewall spacers in the cell array region. The double sidewall spacers are advantageously formed to suppress the short channel effect, to prevent current leakage, and to reduce sheet resistance. The insulating layer used to form the second spacers in the peripheral region remains in the cell array region and serves as an etching stopper during the etching step of interlayer insulating layer for contact opening formation and also serves as a barrier layer during the step of silicidation formation. As a result the fabrication process of the resulting device is simplified.

Abstract: A method for forming a shallow junction region in a crystalline semiconductor substrate and method for fabricating a semiconductor device having the shallow junction region includes a defect engineering step in which first ions are introduced into a first region of the substrate and vacancies are generated in the first region. During the generation of substrate vacancies, the first region remains substantially crystalline. Interstitial species are generated in a second region and second ions are introduced into the second region to capture the interstitial species. Laser annealing is used to activate dopant species in the first region and repair implantation damage in the second region. The defect engineering process creates a vacancy-rich surface region in which source and drain extension regions having high dopant activation and low sheet resistance are created in an MOS device.

Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed.

Abstract: In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrode in a gate length direction, and upper and lower drain regions are formed on the other side thereof. By thus forming the lower source and drain regions in the source and drain regions, current concentration occurring in an upper portion of a channel region, which is generated as the gate length becomes shorter, may be suppressed and a current may be allowed to flow uniformly in the entire channel region, and hence an effective gate width is made wider owing to the irregular structure formed in the well region. Accordingly, an on-resistance of a semiconductor device is reduced to enhance driving performance.

Abstract: A method of monolithically fabricating an LDMOS transistor with a fabrication process that is compatible with a sub-micron CMOS fabrication process. The specification further describes an LDMOS transistor. The LDMOS transistor is implemented in a first impurity region on a substrate. The LDMOS transistor has a source that includes a second impurity region. The second impurity region is implanted into the surface of the substrate within the first impurity region. Additionally, the LDMOS transistor has a drain that includes a third impurity region. The third impurity region is implanted into the surface of the substrate within the first impurity region. The third impurity region is spaced a predetermined distance away from a gate of the LDMOS transistor. The drain of the LDMOS transistor further includes a fourth impurity region within the third impurity region. The fourth impurity region provides an ohmic contact for the drain.

Abstract: A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region.

Abstract: A doping method includes: a first step of depositing a material solution containing an antimony compound containing elements selected from the group consisting essentially of hydrogen, nitrogen, oxygen, and carbon together with antimony to a surface of a substrate; a second step of drying the material solution to form an antimony compound layer on the substrate; and a third step of performing heat treatment so that antimony in the antimony compound layer is diffused into the substrate.

Abstract: A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.

Abstract: A gate electrode structure is provided, which includes, from bottom to top, an optional, yet preferred metallic layer, a Ge rich-containing layer and a Si rich-containing layer. The sidewalls of the Ge rich-containing layer include a surface passivation layer. The inventive gate electrode structure serves as a low-temperature electrically activated gate electrode of a MOSFET in which the materials thereof as well as the method of fabricating the same are compatible with existing MOSFET fabrication techniques. The inventive gate electrode structure is electrically activated at low processing temperatures (on the order of less than 750° C.). Additionally, the inventive gate electrode structure also minimizes gate-depletion effects, does not contaminate a standard MOS fabrication facility and has sufficiently low reactivity of the exposed surfaces that renders such a gate electrode structure compatible with conventional MOSFET processing steps.

Abstract: A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.

Abstract: A strained channel transistor is provided. The strained channel transistor comprises a substrate formed of a first material. A source region comprised of a second material is formed in a first recess in the substrate, and a drain region comprised of the second material is formed in a second recess in the substrate. A strained channel region formed of the first material is intermediate the source and drain region. A gate stack formed over the channel region includes a gate electrode overlying a gate dielectric. A gate spacer formed along a sidewall of the gate electrode overlies a portion of at least one of said source region and said drain region. A cap layer may be formed over the second material, and the source and drain regions may be silicided.

Abstract: A stress memorization technique (SMT) film is deposited over a semiconductor device. The SMT film is annealed with a low thermal budget anneal that is sufficient to create and transfer the stress of the SMT film to the semiconductor device. The SMT film is then removed. After the SMT film is removed, a second anneal is applied to the semiconductor device sufficiently long and at a sufficiently high temperature to activate dopants implanted for forming device source/drains. The result of this approach is that there is minimal gate dielectric growth in the channel along the border of the channel.

Abstract: A semiconductor device includes a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration.