Abstract: The present invention provides a method for fabricating a semiconductor device capable of preventing a contact resistance from increasing in a region contacted to an N-type conductive region during forming a conductive pattern directly contacted to the N-type conductive region including a conductive pattern and silicon, and preventing an increase in a parasitic capacity of the conductive pattern according to an increase in a thickness of a barrier layer.

Abstract: A high voltage semiconductor device. The high voltage device has a substrate (e.g., silicon wafer) having a surface region. The substrate has a well region within the substrate and a double diffused drain region within the well region. A gate dielectric layer is overlying the surface region. A gate polysilicon layer is overlying the gate dielectric layer. A mask layer is overlying the gate polysilicon layer. The device also has a gate electrode formed within the gate polysilicon layer. The gate electrode has a first predetermined width and a first predetermined thickness. Preferably, the gate electrode has a first side and a second side formed between the first predetermined width. The gate electrode is coupled to the double diffused drain region within the well region.

Abstract: An apparatus and method for manufacturing rotated field effect transistors. The method comprises providing a substrate including a first gate structure and a second gate structure, which are not parallel to each other. The method further includes performing a first ion implant substantially orthogonal to an edge of the first gate structure to form a first impurity region and performing a second ion implant at a direction different than that of the first ion implant and substantially orthogonal to an edge of the second gate structure to form a second impurity region under the edge of the second gate structure.

Abstract: A metal oxide semiconductor device having a substrate layer of a semiconductor material and a gate, a source and, a drain formed over the substrate layer is provided. The substrate is doped with a deep n-type lightly doped drain implant that simmultaneously lowers the threshold voltage and increases the drain junction breakdown voltage of the device. A method of fabricating a metal oxide semiconductor device is also divided.

Abstract: This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region.

Abstract: A method of making an integrated circuit chip is provided, which combines a smart grading implant with a diffusion retarding implant, e.g., to improve short channel effect controllability and improve dopant grading in the source/drain regions. Using a smart grading implant, a relatively low-energy high-dose implant is performed before a relatively low-energy high-dose implant. Hence, a relatively high-energy low-dose implant of ions is performed into a source/drain region of a substrate. A diffusion retarding implant is performed into the source/drain region of the substrate. Then after performing the high-energy low-dose implant and the diffusion retarding implant (together, overlapping, or separately), a relatively low-energy high-dose implant of ions is performed into the source/drain region of the substrate.

Abstract: An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region.

Abstract: In a method for producing a semiconductor structure a semiconductor a substrate with a top surface is provided. A gate dielectric layer is provided on the top surface and on the gate dielectric layer is provided a memory cell array region with a first plurality of gate stacks and a peripheral element region with a second plurality of gate stacks. A dielectric layer is provided over the memory cell array region and the peripheral element region. A first source/drain implantation over the memory cell array region and the peripheral element region is carried out, a blocking mask over the memory cell array region is formed, the dielectric layer is removed using the blocking mask, and a second source/drain implantation over the memory cell array region and the peripheral element region is carried out, wherein the memory cell array region is protected by a mask.

Abstract: A semiconductor device includes: a semiconductor substrate having a source region and a drain region; and an offset region that is provided in the semiconductor substrate and extends from an edge of a gate electrode toward the drain region. The offset region includes multiple regions having different impurity concentrations formed by an ion implantation with a mask having an opening ratio that changes from the gate electrode to the drain region and by subsequent thermal treatment. The multiple regions include a concentration gradient region that is interposed between adjacent ones of the multiple regions and has the impurity concentration that gradually changes.

Abstract: A semiconductor structure and method for forming the same. The semiconductor structure comprises a field effect transistor (FET) having a channel region disposed between first and second source/drain (S/D) extension regions which are in turn in direct physical contact with first and second S/D regions, respective. First and second silicide regions are formed such that the first silicide region is in direct physical contact with the first S/D region and the first S/D extension region, whereas the second silicide region is in direct physical contact with the second S/D region and the second S/D extension region. The first silicide region is thinner for regions in contact with first S/D extension region than for regions in contact with the first S/D region. Similarly, the second silicide region is thinner for regions in contact with second S/D extension region than for regions in contact with the second S/D region.

Abstract: First and second impurity doped regions are formed in a semiconductor substrate. A first gate electrode is formed on the first impurity doped region with a first gate insulation film interposed therebetween. A second gate electrode is formed on the second impurity doped region with a second gate insulation film interposed therebetween. A first sidewall insulation film is formed on either side of the first gate electrode. A second sidewall insulation film has a thickness different from that of the first sidewall insulation film and are formed on either side of the second gate electrode. A third sidewall insulation film is formed on the first sidewall insulation film on the side of the first gate electrode. A fourth sidewall insulation films have a thickness different from that of the third sidewall, insulation film and are formed on the second sidewall insulation film on the side of the second gate electrode.

Abstract: A transistor, transistor arrangement and method thereof are provided. The example method may include determining whether a gate width of the transistor has been adjusted; and adjusting a distance between a higher-concentration impurity-doped region of the transistor and a device isolation layer of the transistor based on the adjusted gate width if the determining step determines the gate width of the transistor is adjusted. The example transistor may include a first device isolation layer defining a first active region, a first gate line having a first gate width and crossing over the first active region, a first lower-concentration impurity-doped region formed in the first active region at first and second sides of the first gate line and a first higher-concentration impurity-doped region formed in the lower-concentration impurity-doped region and not in contact with the gate line and the device-isolation layer.

Abstract: A method of fabricating polysilicon lines and polysilicon gates, the method of including: providing a substrate; forming a dielectric layer on a top surface of the substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species about contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.

Abstract: A semiconductor device having a recess gate is formed by first forming a recess below the upper surface of the substrate. A spacer is formed at each sidewall of the recess. An impurity doping area is formed in a source area. A first LDD area is formed in a drain area. A gate comprising a gate insulating layer and a gate conductive layer is then formed in the recess. A second LDD area is formed on the upper surface of the semiconductor substrate. A gate spacer is formed at each sidewall of the gate. Then a source/drain area having an asymmetrical structure is formed on each side of the gate.

Abstract: The method of manufacturing a recess type MOS transistor improves a refresh characteristic. In the method, a channel impurity region is formed by ion implanting a first conductive impurity in an active region of a semiconductor substrate. Thereon, a second conductive impurity and the first conductive impurity are ion-implanted each alternately into the active region, to thus sequentially form first to third impurity regions having a dual diode structure on the channel impurity region, the second conductive impurity having conductivity opposite to the first conductive impurity. A trench is formed, and a gate insulation layer is formed in a gate region to produce a gate stack. The first conductive impurity is selectively ion-implanted in a source region, to thus form a fourth impurity region. A spacer is then formed in a sidewall of the gate stack, and the second conductive impurity is ion-implanted in the source/drain regions, to form a fifth impurity region.

Abstract: An MOS device includes a semiconductor layer of a first conductivity type, a source region of a second conductivity type formed in the semiconductor layer, and a drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the source region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the source and drain regions. The MOS device further includes a buried LDD region of the second conductivity type formed in the semiconductor layer between the gate and the drain region, the buried LDD region being spaced laterally from the drain region, and a second LDD region of the first conductivity type formed in the buried LDD region and proximate the upper surface of the semiconductor layer. The second LDD region is self-aligned with the gate and spaced laterally from the gate such that the gate is non-overlapping relative to the second LDD region.

Abstract: A gate electrode made of semiconductor is formed on the partial surface area of a semiconductor substrate. A mask member is formed on the surface of the semiconductor substrate in an area adjacent to the gate electrode. Impurities are implanted into the gate electrode. After impurities are implanted, the mask member is removed. Source and drain regions are formed by implanting impurities into the surface layer of the semiconductor substrate on both sides of the gate electrode. It is possible to reduce variations of cross sectional shape of gate electrodes and set an impurity concentration of the gate electrode independently from an impurity concentration of the source and drain regions.

Abstract: A semiconductor device may include first, second, and third semiconductor layers. The first and third layers may have a first dopant type, and the second layer may have a second dopant type. A first region within the third semiconductor layer may have the second dopant type. A second region between the first region and the second semiconductor layer may have the first dopant type. A third region above the second region may have the first dopant type. A fourth semiconductor region adjacent to the third region may have a first concentration of the second dopant type. A source contact region may have a second concentration of the second dopant type adjacent to the third semiconductor region and adjacent to the fourth semiconductor region. The second concentration may be higher than the first concentration.

Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

Abstract: A method of selecting plasma doping process parameters includes determining a recipe parameter database for achieving at least one plasma doping condition. The initial recipe parameters are determined from the recipe parameter database. In-situ measurements of at least one plasma doping condition are performed. The in-situ measurements of the at least one plasma doping condition are correlated to at least one plasma doping result. At least one recipe parameter is changed in response to the correlation so as to improve at least one plasma doping process performance metric.

Abstract: The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric. The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.

Abstract: A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor substrate, ion-implanting a first conductive impurity into source/drain regions to form first impurity regions, and ion-implanting the first conductive impurity to form second impurity regions that are overlapped by the first impurity regions. The method includes forming a pad polysilicon layer on the source/drain regions, sequentially removing the pad polysilicon layer and the dummy gate electrode from a gate region of the semiconductor substrate, annealing the semiconductor substrate, and ion-implanting a second conductive impurity to form a third impurity region in the gate region. The method includes removing the dummy gate oxide layer, forming a gate insulation layer, and forming a gate electrode on the gate region.

Abstract: A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.

Abstract: An inverse-T transistor is formed by a method that decouples the halo implant, the deep S/D implant and the extension implant, so that the threshold voltage can be set by adjusting the halo implant without being affected by changes to the extension implant that are intended to alter the series resistance of the device. Formation of the inverse-T structure can be made by a damascene method in which a temporary layer deposited over the layer that will form the cross bar of the T has an aperture formed in it to hold the gate electrode, the aperture being lined with vertical sidewalls that provide space for the ledges that form the T. Another method of gate electrode formation starts with a layer of poly, forms a block for the gate electrode, covers the horizontal surfaces outside the gate with an etch-resistant material and etches horizontally to remove material above the cross bars on the T, the cross bars being protected by the etch resistant material.

Abstract: A method of manufacturing a semiconductor device having a semiconductor substrate that includes an active region for forming transistor elements, which includes a gate, and an element isolation region for isolating the transistor elements separately each other, which has a STI structure, the method comprises; first—ion implanting fist ions onto the surface of the semiconductor substrate in a region other than a stress region in the active region, which is located at the interface with the element isolation region, in the stress region, a potential stress is generated by forming the element isolation region and/or the difference between a material of the element isolation region and a material of the semiconductor substrate, so that a first impurity region for a source and/or a drain is formed in the active region in which the gate is not formed; and second ion implanting second ions each of which mass is smaller than that of each of the first ions so that a second ion impurity region is formed in the stress r

Abstract: Disclosed is a metal capacitor including a lower electrode having hemispherical metal grains thereon. The metal capacitor includes a lower metal electrode containing Ti, hemispherical metal grains containing Pd and formed on the lower metal electrode containing Ti, a dielectric layer formed on the lower metal electrode containing Ti and the hemispherical metal grains containing Pd, and an upper metal electrode formed on the dielectric layer.

Abstract: A method for forming a thin-film transistor on an insulating substrate includes the steps of: forming a non-single-crystal semiconductor thin film on the insulating substrate; forming a gate insulating film on the non-single-crystal semiconductor thin film; forming a gate electrode including a lower gate electrode and an upper gate electrode on the gate insulating film, the lower gate electrode having a portion that is not covered by the upper gate electrode; forming a source-drain region and an LDD (lightly doped drain) region in the non-single-crystal thin film semiconductor film at a time by introducing an impurity into the non-single-crystal semiconductor thin film through the gate electrode and the gate insulating film; and etching away an exposed portion of the lower gate electrode by using the upper gate electrode as a mask.

Abstract: Semiconductor devices and manufacturing methods therefor are disclosed, in which a drain-extended MOS transistor comprises a self-aligned floating region proximate one end of the transistor gate and doped with a first type dopant to reduce channel hot carrier degradation, as well as an oppositely doped first source/drain laterally spaced from the first end of the gate structure in a semiconductor body. The device may further comprise a resurf region doped to a lower concentration than the floating region to facilitate improved breakdown voltage performance. A method of fabricating a drain-extended MOS transistor in a semiconductor device is disclosed, comprising providing first dopants to a floating region in a semiconductor body, which is self-aligned with the first end of a gate structure, and providing second dopants to source/drains of the semiconductor body, wherein the first and second dopants are different.

Abstract: Methods for stabilizing a threshold voltage in an NMOS transistor are disclosed. A disclosed method comprises: forming a gate electrode on an active region in a substrate of a first conductive type; implanting ions of a second conductive type into the active region to form LDD regions; forming spacers on the sidewalls of the gate electrode; implanting ions of the second conductive type into the active region to form second source/drain regions; implanting halo ions into the active region; activating ions in the source/drain regions by conducting a first thermal process; and moving the halo ions toward the surface of the channel under the gate electrode by conducting a second thermal process.

Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having L-shaped sidewall spacers (430) on opposing sidewalls thereof and placing source/drain implants (310 or 510) into the substrate (110) proximate the gate structure (130). The method for manufacturing the semiconductor device further includes removing at least a portion of a horizontal segment of the L-shaped sidewall spacers (430).

Abstract: A method including forming a transistor device having a channel region; implanting a first halo into the channel region; and implanting a second different halo into the channel region. An apparatus including a gate electrode formed on a substrate; a channel region formed in the substrate below the gate electrode and between contact points; a first halo implant comprising a first species in the channel region; and a second halo implant including a different second species in the channel region.

Abstract: MOS transistors having a low junction capacitance between their halo regions and their source/drain extension regions and methods for manufacturing the same are disclosed. A disclosed MOS transistor includes: a semiconductor substrate of a first conductivity type; a gate insulating layer pattern and a gate on an active region of the substrate; spacers on side walls of the gate; source/drain extension regions of a second conductivity type within the substrate on opposite sides of the gate, the source/drain extension regions having a graded junction structure; halo impurity regions of the first conductivity type within the substrate under opposite edges of the gate adjacent respective ones of the source/drain extension regions; and source/drain regions of the second conductivity type within the substrate on opposite sides of the spacer.

Abstract: Disclosed is a method of manufacturing a semiconductor device. A plurality of device separation regions are formed in an SOI layer of an SOI substrate, a desired impurity is implanted into a body portion of an Si active layer region, and thereafter a gate electrode is formed with a gate insulation film therebetween. Thereafter, an impurity is implanted into the Si active layer region to form extension portions of source/drain portions, and then an impurity different in polarity from the impurity in the source/drain portions is halo-implanted to form a reverse-characteristic layer. In the halo implantation, the range of projection is set to reach the inside of a buried oxide film. With this configuration, in a fully depleted SOI-MOSFET or the like provided with a thin film SOI layer, it is made possible to simultaneously achieve an improvement of roll-off characteristic and a reduction in parasitic resistance and to secure a sufficient driving capability.

Abstract: Methods of forming semiconductor devices with a layered structure of thin and well defined layer of activated dopants, are disclosed. In a preferred method, a region in a semiconductor substrate is amorphized, after which the region is implanted with a first dopant at a first doping concentration. Then a solid phase epitaxy regrowth step is performed on a thin layer of desired thickness of the amorphized region, in order to activate the first dopant only in this thin layer. Subsequently, a second dopant is implanted in the remaining amorphous region at a second doping concentration. Subsequent annealing of the substrate activates the second dopant only in said remaining region, so a very abrupt transition between dopant characteristics of the thin layer with first dopant and the region with the second dopant is obtained.

Abstract: A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the substrate and a plurality of pass gates formed over the field regions of the substrate, first self-aligned contact regions formed between adjacent pass gates and access gates, and second self-aligned contact regions formed between adjacent access gates, wherein a width of each of the first self-aligned contact regions is larger than a width of each of the second self-aligned contact regions.

Abstract: A structure for making a LDMOS transistor (100) includes an interdigitated source finger (26) and a drain finger (21) on a substrate (15). Termination regions (35, 37) are formed at the tips of the source finger and drain finger. A drain (45) of a second conductivity type is formed in the substrate of a first conductivity type. A field reduction region (7) of a second conductivity type is formed in the drain and is wrapped around the termination regions for controlling the depletion at the tip and providing higher voltage breakdown of the transistor.

Abstract: An insulated gate field effect transistor having reduced gate-drain overlap and a method for manufacturing the insulated gate field effect transistor. A gate structure is formed on a major surface of a semiconductor substrate. A source extension region and a drain extension region are formed in a semiconductor material using an angled implant. The source extension region extends under the gate structure, whereas the drain extension region is laterally spaced apart from the gate structure. A source region is formed in the semiconductor substrate and a drain region is formed in the semiconductor substrate, where the source and drain regions are laterally spaced apart from the gate structure. A source-side halo region is formed in the semiconductor substrate adjacent the source extension region.

Abstract: Fluorine containing regions (70) are formed in the source and drain regions (60) of the MOS transistor. A metal layer (90) is formed over the fluorine containing regions (70) and the source and drain regions (60). The metal layer is reacted with the underlying fluorine containing regions to form a metal silicide.

Abstract: A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as a mask, to form a doped depletion region beneath and separated from the source/drain regions. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. The doped depletion region and substrate form depletion regions between the source/drain regions and the doped depletion region. We perform a S/D implant by implanting ions having a second conductivity type into the substrate to form S/D regions. The doped depletion region and depletion regions reduce the capacitance between the source/drain regions and the substrate.

Abstract: Example methods of manufacturing MOSFET devices are disclosed. One example method may include an oxidation, an etching, an ion implanting for a threshold voltage control to form an elevated source/drain region and thereby implements an ultra shallow junction.

Abstract: A method and system for providing a halo implant to a semiconductor device is disclosed. The method and system includes providing a thin photoresist layer that covers a substantial amount of an active area including a source region and a drain region of the semiconductor device. The method and system further includes providing the halo implant to the semiconductor device, using the thin photoresist layer as a mask. Utilizing this thin photoresist layer, taking into account other height variables, the source and drain regions can be opened only as needed. At a 45° angle, the implant can be delivered to all transistors in the circuit in the targeted area as well as getting only a large amount of the dose (up to ¾ of the dose) to the transistor edge which sits on the trench edge.

Abstract: A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another method, a gate and a gate oxide layer are formed in overlapping relation, with the gate having opposing edges and a center therebetween. At least one of chlorine or fluorine is concentrated in the gate oxide layer within the overlap more proximate at least one of the gate edges than the center. Preferably, the central region is substantially undoped with fluorine and chlorine. The chlorine and/or fluorine can be provided by forming sidewall spacers proximate the opposing lateral edges of the gate, with the sidewall spacers comprising at least one of chlorine or fluorine. The spacers are annealed at a temperature and for a time effective to diffuse the fluorine or chlorine into the gate oxide layer to beneath the gate.

Abstract: A method and arrangement for reducing the series resistance of the source and drain in a MOSFET device provides for epitaxially grown regions on top of the source and drain extensions to cover portions of the top surfaces of the silicide regions formed on the substrate. The epitaxial material provides an extra flow path for current to flow through to the silicide from the extension, as well as increasing the surface area between the source/drain and the silicide to reduce the contact resistance between the source/drain and the silicide.

Abstract: A semiconductor device is provided with a FET having a sufficiently small short channel effect and sufficiently small junction capacitance and junction leakage current. The FET includes a channel region formed in a silicon substrate, a gate electrode formed on the channel region through the intermediary of a gate insulting film, heavily doped regions, and pocket regions. The pocket regions are formed to extend from inside the heavily doped regions, respectively, over inside the channel region. Because a pocket sub-region inside the respective heavily doped regions is formed to be located in regions shallower than the respective lower end faces of the heavily doped regions, junction capacitance and junction leakage current are reduced. Further, because respective pocket sub-regions inside the channel region are formed in regions deeper than the respective pocket sub-regions inside the heavily doped regions, a short channel effect can be reduced.

Abstract: Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer (130) is formed prior to formation of epitaxial silicon (106) over a substrate (104), and a drain-extended MOS transistor (T1, T2) is formed in the epitaxial silicon layer (106). The p-buried layer (130) may be formed above an n-buried layer (120) in the substrate (104) for high-side driver transistor (T2) applications, wherein the p-buried layer (130) extends between the drain-extended MOS transistor (T2) and the n-buried layer (120) to inhibit off-state breakdown between the source (154) and drain (156).

Abstract: Methods of fabricating halo regions are provided. In one aspect, a method is provided of fabricating a first halo region and a second halo region for a circuit device of a first conductivity type and having a gate structure with first and second sidewalls. The first halo region of a second conductivity type is formed by implanting the substrate with impurities in a first direction toward the first sidewall of the gate structure. The second halo region of the second conductivity type is formed by implanting the substrate with impurities in a second direction toward the second sidewall of the gate structure. The first and second halo regions are formed without implanting impurities in a direction substantially perpendicular to the first and second directions.

Abstract: A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portions reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.

Abstract: Disadvantages of the floating body of a SOI MOSFET are addressed by providing a pocket halo implant of indium beneath the gate and in the channel region of the semiconductor SOI layer of the MOSFET. Also provided is the method for fabricating the device.

Abstract: A metal oxide semiconductor (MOS) transistor and a method of manufacturing the same are disclosed. An example MOS transistor includes a semiconductor substrate of a first conductivity type where an active region is defined, a gate insulating layer pattern and a gate formed on the active region of the substrate, a spacer formed on side walls of the gate, and source/drain extension regions of a second conductivity type formed within the substrate at both sides of the gate. The example MOS transistor further includes source/drain regions of the second conductivity type formed within the substrate at both side of the spacer and punch-through suppression regions of the first conductivity type formed within the active of the substrate. The punch-through suppression regions surround the source/drain extension regions and the source/drain regions under the gate.

Abstract: A process for fabricating input/output, N channel, (I/O NMOS) devices, featuring an ion implanted nitrogen region, used to reduce hot carrier electron, (HEC), injection, has been developed. The process features implanting a nitorgen region, at the interface of an overlying silicon oxide layer, and an underlying lightly doped source/drain, (LDD), region. The implantation procedure can either be performed prior to, or after, the deposition of a silicon oxide liner layer, in both cases resulting in a desired nitrogen pile-up at the oxide-LDD interface, as well as resulting, in a more graded LDD profile. An increase in the time to fail, in regards to HCE injection, for these I/O NMOS devices, is realized, when compared to counterparts fabricated without the nitrogen implantation procedure.