Abstract: On a surface of a silicon substrate having conductivity type of p-type, a field oxide layer and a gate oxide layer to be an isolation region are formed. A gate electrode is formed via the gate oxide layer. A surface silicon oxide layer is formed on a surface of the gate electrode. An etch stop layer is formed at a region outside of the surface silicon oxide layer, which etch stop layer is formed of a material different from a material of the gate oxide layer. Also, on the upper surface of the etch stop layer, an interlayer insulation layer is formed. Then, on the surface of the silicon substrate in the vicinity of the end of the gate electrode, an n.sup.- -diffusion layer is formed. In a region outside of the n.sup.- -diffusion layer, an n.sup.+ -diffusion layer is formed. On the other hand, between the upper surface of the n.sup.- -diffusion layer and the n.sup.

Abstract: A method for manufacturing a deep-submicron P-type metal-oxide semiconductor shallow junction utilizes an electron terminal structure with a base covered by a layer containing boron, germanium, and silicon. This layer containing boron, germanium, and silicon ("B--Ge--Si") is used as a shield during ion implanting and as an impurity ion source to form a high diffusion ion concentration at a shallow junction of the semiconductor base or substrate. The B--Ge--Si layer can be thoroughly removed using selective corrosive erosion. Due to the simplicity of this invention's manufacturing process, it can be used for deep-submicron PMOS component production, and thus, it has great practical value.

Abstract: A method of making an asymmetrical IGFET and isolating active regions is disclosed.

Abstract: A gate oxide and a first conducting layer are formed on a substrate, and then the first conducting layer is patterned and a gate in a NMOS region is formed. A LDD, a sidewall spacer, and a drain/source in the NMOS region are then formed in series. A layer of hard mask is formed. The layer of hard mask and the first conducting layer are patterned and a gate in a PMOS region is formed. A LDD, a sidewall spacer, and a drain/source in the NMOS region are then formed in series.

Abstract: An integrated circuit transistor and a method for making the same are provided. The transistor is resistant to junction shorts due to the overetch of local interconnect trenches. The transistor includes a source/drain region with a first junction and a second junction that is located deeper than the first junction in the portion of the active area susceptible to the overetch junction short phenomena. The second junction is established by ion implantation through a mask that is patterned to create an opening corresponding to the intersection of the layouts of the active area and the local interconnect trench. Using this method, the second junction is only established where needed to prevent shorting and does not impede transistor performance.

Abstract: A high voltage NMOS device includes an extended drain region formed by implantation of arsenic and phosphorus and a drivein of both the species. The dosage of arsenic is substantially higher than the dosage of phosphorus, so that upon drivein, the slower diffusing arsenic is highly concentrated near the surface of the extended drain region, while the more rapidly diffusing phosphorus provides a gradual gradient of concentration of dopant into the extended drain region.

Abstract: A method of reducing the fringe capacitance between a gate and a substrate in a semiconductor device. A silicon nitride is formed over a substrate with a buffer oxide layer thereon and patterned to form an opening. The buffer oxide layer within the opening is removed and another oxide layer is formed at the same place as a gate oxide layer. A poly-gate is formed at the opening with a wider width than the opening. Thus, a part of the poly-gate at both ends covers a part of the silicon nitride layer. The silicon nitride layer is then removed and leaves the poly-gate as a T-shape with two ends suspended over the substrate. With a large angle, a light dopant is implanted into the substrate under the suspended part of the poly-gate to form a lightly doped region. With another smaller angle, a heavy dopant is implanted into the substrate beside the poly-gate. Therefore, a source/drain is formed.

Abstract: Short channel MOS semiconductor devices are produced by implanting impurity ions through gate electrode and gate oxide layers, before patterning the gate electrode, using a composite mask of silicon oxide and silicon nitride, to form a shallow channel region in the substrate for adjusting the threshold voltage and a deeper well region for preventing punch through. In another embodiment, impurity ions are implanted to form lightly doped and heavily doped source/drain regions in a single ion implantation step using a thermally grown oxide region having bird's beaks as a mask. Self-aligned lightly doped regions are formed under the bird's beaks.

Abstract: To provide a lateral MISFET that has a uniform and reliable gate insulation film, and exhibits low on-resistance and excellent balance between the breakdown voltage and on-resistance. The device of the invention has an n-type semiconductor substrate, in a part of the surface layer thereof is formed a trench. An n-drain region is formed in the bottom of the trench. A side wall oxide film is formed on the side face of the trench. The trench is filled with a conductive material, on which is formed a drain electrode. A p-base region and an n-source region are self-aligned on the portion of the substrate in which the trench is not formed. A MIS gate is disposed on the p-base region. Since the portion of the substrate along the side wall oxide film functions as a drain drift region, the unit cell dimension are greatly reduced, the on-resistance is reduced, and therefore the trade-off relation between the breakdown voltage and the on-resistance is improved.

Abstract: The present invention has the object of offering a semiconductor production method which simplifies the fabrication of gate electrodes for MOS-type semiconductor elements and allows a high yield to be maintained. For this purpose, it has steps of forming a field-shield gate insulation film on a semiconductor substrate, forming polycrystalline silicon films having an etching rate which is greater at an upper side than a lower side thereon, and etching the polycrystalline silicon films under conditions which allow for side etching with the silicon oxide film as a mask, so as to make gradually tapered inclines on side walls of field-shield gate electrode.

Abstract: A method of manufacturing an integrated circuit so as to reduce overlap between an LDD region and a gate electrode is disclosed. The method includes forming a gate electrode on a gate insulator on a semiconductor substrate, implanting a lightly-doped drain (LDD) region in the substrate using the gate electrode as a mask, removing a lateral portion of the gate electrode after implanting the LDD region, and then laterally diffusing the LDD region into the substrate such that a lateral edge of the LDD region is substantially aligned with a lateral edge of the gate electrode. Preferably, the lateral portion of the gate electrode is removed using an isotropic etch. The method further includes forming a spacer adjacent to an edge of the gate electrode after removing the lateral portion, and then implanting a heavily-doped region using the spacer and gate electrode as an implant mask.

Abstract: A MOS transistor structure is provided in which the source/drain contacts are to raised polysilicon and are located entirely over field isolation. Contact integrity is maintained because the contact is located on field oxide, rather than in direct contact with the substrate junction diffusion area. Conventional contact metal spiking into the junction area is also eliminated. Contact overetch during formation of the contact opening can be increased to insure a clean contact surface because the contact is made to the raised poly regions. Furthermore, the contact barrier is no longer essential for maintaining contact reliability, because the contact is located away from the active junction.

Abstract: An anisotropic RIE procedure for creating a small diameter SAC opening, in an insulator layer, used in the fabrication sequence of a MOSFET device, and using a large area test site for RIE end point monitoring, has been developed. The RIE procedure features a RIE ambient, including oxygen as part of the RIE ambient, resulting in equal amounts of polymer deposition on the small diameter SAC opening, as well as on the large area test sites, during the reactive ion etching of the small diameter, SAC opening. This allows accurate monitoring of the RIE procedure to be performed on the large area test site, using optical ellipsometry procedures.

Abstract: An impurity adsorption layer is formed on a substrate surface and solid-phase thermal diffusion is carried out to form source and drain regions for a metal-insulator-semiconductor field-effect-transistor having lightly doped drain structure or double doped drain structure. The thus formed impurity-doped region is ultrashallow, thereby producing high speed semiconductor devices of small dimensions.

Abstract: In the fabrication of an integrated circuit having both N MOSFETs and P MOSFETs in which the respective N-type species and P-type species have substantially different diffusivities, the source implant of the dopant species having a the higher diffusivity is advantageously delayed until a contact masking process step. By delaying the dopant species having the higher diffusivity, depletion of the dopant by subsequent annealing steps is avoided. P MOSFETs formed using a high diffusivity boron implant species in an integrated circuit including both P MOSFETs and N MOSFET are fabricated with no source implant in the source regions during formation of the gate electrodes and sidewall spaces.

Abstract: N- and P-channel transistor characteristics are independently optimized for CMOS semiconductor devices with design features of 0.25 microns and under. Removable second sidewall spacers are formed on the N-channel transistor gate electrode having first sidewall spacers thereon. Ion implantation is conducted to form N-type moderately/heavily doped implants followed by activation annealing. The second sidewall spacer is then removed from the P-channel transistor leaving first sidewall spacers thereon serving as an ion implantation mask for the P-type lightly doped implants. Subsequently, third sidewall spacers are formed on the P-channel gate electrode having first sidewall spacers thereon followed by ion implantation to form the P-type moderately or heavily doped implants, with subsequent activation annealing. Embodiments enable complete independent control of the channel lengths of the N- and P-channel transistors by varying the width of the first, second and third sidewall spacers.

Abstract: VLSI I/O structures to reduce the effects of simultaneous switching noise (SSN) on output driver circuits and enhance electrostatic discharge immunity, while reducing chip area, in both input receiver circuits and output driver circuits include improved transistors having deep-junction drain and a multi-cascaded, resistive deep-junction source structure.

Abstract: The present invention provides a process for forming an MOS semiconductor device having an LDD structure, which includes a forming a gate electrode by first etching a conductive layer to a certain depth by an RIE process and by second etching the conductive layer by an isotropic plasma etching process. In forming the source/drain of the device, an n.sup.+ source/drain and an n.sup.- source/drain are formed in a sequential manner. The gate line first is formed with its width over-sized compared with its channel length, and finally is formed to its final size.

Abstract: A first photoresist layer has opening portions in a region where an n-channel MOS transistor should be formed and in a region where a collector leading region should be formed. Then, phosphorous is implanted with taking the first photoresist layer as a mask. The first photoresist layer is then removed and a second photoresist layer is formed. The second photoresist layer has opening portions in a region where an emitter region should be formed and in the region where the collector leading region should be formed. Phosphorous is implanted with taking the second photoresist layer as a mask to form an n-type selective diffusion region in a region below the region where the emitter region should be formed and in the region where the collector leading region should be formed. Then, the second photoresist layer is removed. A polycrystalline silicon layer is formed over the entire surface and arsenic is implanted therein to make it n-type.

Abstract: A complementary semiconductor device which includes: a semiconductor substrate having a principal surface, with a first region doped with an impurity of a first conductivity type and a second region doped with an impurity of a second conductivity type; a first MOS transistor provided on the second region; and a second MOS transistor provided on the first region. In such a complementary semiconductor device, at least one of the first MOS transistor and the second MOS transistor is an asymmetric MOS transistor of the same conductivity type as the conductivity type of the corresponding region which is either the first region or the second region.

Abstract: A method of making NMOS and PMOS devices with different gate lengths includes providing a semiconductor substrate with first and second active regions, forming a first gate over a portion of the first active region and a second gate over a portion of the second active region, wherein the first and second gates are formed in sequence and have different lengths, and forming a source and drain in the first active region and a source and drain in the second active region. Preferably, the first gate is defined by a first photoresist layer patterned with a first exposure time, the second gate is defined by a second photoresist layer patterned with a second exposure time, and the difference in gate lengths is due primarily to a difference between the first and second exposure times.

Abstract: A method of forming an integrated circuit device, and in particular a CMOS integrated circuit device, having an improved lightly doped drain region. The methods include the steps of providing a semiconductor substrate with a P type well region and an N type well region. Gate electrodes are formed overlying gate dielectric over each P type well and N type well regions. The present LDD fabrication methods then provide a relatively consistent and easy method to fabricate CMOS LDD regions with N type and P type implants at a combination of different dosages and angles using first and second sidewall spacers, with less masking steps and improved device performance.

Abstract: A method of manufacturing a transistor having LDD regions in which the source and drain regions are formed by implanting ions through a photoresist layer at an energy of 1 MeV and greater and the LDD regions are formed by low energy ion implantation after the oxide layer is removed from the active region and the gate. In a second embodiment, the source and drain regions are formed without a photoresist layer by ion implantation and the LDD regions are formed by low energy ion implantation after the oxide layer is removed from the active region and the gate.

Abstract: A method for fabricating an MOS transistor of an LDD structure having reduced short channel effects and GIDL (Gate Induced Drain Leakage) including the steps of providing a semiconductor substrate, forming a field oxide film in a field region of the semiconductor substrate, forming a gate electrode having a gate insulating film and a cap gate insulating film in an active region on the semiconductor substrate, forming L-shaped insulating sidewalls at sides of the gate electrode, forming high density source/drain regions in the semiconductor substrate in the active region using the gate electrode and the L-shaped insulating sidewalls as masks,etching the L-shaped insulating sidewalls into I-shaped insulating sidewalls, and forming lightly doped source/drain regions in the semiconductor substrate active region using the I-shaped insulating sidewalls and the gate electrode as masks.

Abstract: The double lightly diffused transistor has drain regions with a lightly doped arsenic region 42 entirely contained within a lightly doped phosphorus region 40. The arsenic region is implanted with a dose less than 1.times.10.sup.15 ions/cm.sup.2 and is preferably implanted with a dose of about 3.times.10.sup.3 to 2.times.10.sup.14 ions/cm.sup.2. The drains are silicided for ohmic contact.

Abstract: A BiCMOS device and a manufacturing method thereof according to the present invention has a gate insulating layer of NMOSFET having non-uniform thickness. The thickness of the end portion of the gate insulating layer, which is near LDD regions, is thicker than that of center portion. Therefore, the GIDL and the gate-drain overlap capacitance is reduced. In addition, in case of the bipolar transistor of the BiCMOS device, there exists a portion of an oxide film below the side portion of the emitter polysilicon and over the side portions of the emitter region. Since this structure serves as a gate of field effect transistor, N- channel is produced in the emitter region when the emitter-base junction is reversely biased and thus the hot carrier reliability is improved.

Abstract: A high density metal gate metal-oxide semiconductor fabrication process to selectively and locally oxidize specific regions of a wafer without increasing the numbers of mask, so as to separately control the thickness of the oxide at the gate, P+ zones and N+ zones, the process including the step of forming a first tye trap zone, the step of forming a shielding layer consisting of an oxide pad and a nitride layer, and the step of forming an oxide layer and removing the nitride layer but the oxide pad to be left before the growing of an insulative oxide layer.

Abstract: A diffused channel insulated gate field effect transistor comprised of a gate isolation layer and a gate electrode positioned on an upper surface of a semiconductor substrate of a first conductivity type; a body region of a second conductivity type present in the semiconductor substrate lying below a part of the gate electrode, on at least one side thereof, and extending downwards to a first depth; a source region of said first conductivity type present in the body region, spaced away from the first end of the gate electrode, at the upper surface and extending downwards therefrom to a second depth, shallower than the first depth; and a lightly doped region of the first conductivity type present in the body region, at least partly between the source region and the gate electrode, extending downwards to a substantially shallower depth than the second depth.

Abstract: This invention relates to a semiconductor device and method for fabricating the semiconductor device, for forming a source and drain structure having no side diffusion. The semiconductor device includes a silicon substrate, a gate formed on the silicon substrate with a gate insulation film in between, and a source and drain formed of conductive material layers buried in the substrate to a designated depth at opposite sides of the gate, thereby providing a source with no side diffusion, preventing reduction of channel length, and improving element integration.

Abstract: A MOS device and method of fabricating the same, wherein the source/drain region has polysilicon trench structure which are formed by self-alignment using silicon oxide layers as masks. The source/drain regions extend to the field oxide layer and/or above the gate. Therefore, contacts can be formed on source/drain conductive regions above the field oxide layer.

Abstract: The present invention relates to a method and device for providing CMOS logic which can be operated at various operating voltages, without resulting in unbalanced operation of n-channel and p-channel CMOS transistors. In accordance with the present invention, CMOS circuitry can be provided that is operable over a range of voltages (e.g., a range from below 3 volts to a range over 5 volts) without producing unbalanced operation of n-channel and p-channel transistors. Thus, integrated circuits formed in accordance with the present invention can be operated at different voltage power sources without requiring a redesign or relayout of the integrated circuit. In accordance with the present invention, CMOS transistors can be fabricated without increased fabrication complexity to provide transistors which operate within a relatively safe region of their operating characteristics and which operate with a speed that is unaffected by the reduced voltage supply (i.e.

Abstract: A novel, reliable, high performance MOS transistor with a composite gate electrode which is compatible with standard CMOS fabrication processes. The composite gate electrode comprises a polysilicon layer formed on a highly conductive layer. The composite gate electrode is formed on a gate insulating layer which is formed on a silicon substrate. A pair of source/drain regions are formed in the substrate and are self-aligned to the outside edges of the composite gate electrode.

Abstract: A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; b) masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and c) in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration

Abstract: A method of fabricating a short-channel MOS device on a substrate is provided. First, stacked pad oxide/nitride layers are formed on the substrate. Then a patterned photoresist film is formed on the planned gate region which covers the gate region and its sidewall spacers. A LPD (Liquid Phase Deposition) oxide is selectively deposited on the pad nitride layer by a liquid phase deposition process, except on the pre-formed photoresist film. After removing the photoresist layer nitride spacers leaning against the LPD oxide layer are formed by lithography and etching. The width of the nitride spacers controls the channel length of the MOS device. After forming a gate structure laterally sandwiched by the nitride spacers on the exposed substrate, a two-stage salicide process, which can form shallow junctions and self-aligned contacts on the source and the drain, is performed to complete the MOS device.

Abstract: A crystalline silicon thin film transistor having an LDD (lightly doped drain) structure and a process for fabricating the same, which comprises establishing an LDD by forming a gate insulating film and a gate electrode on an island-like semiconductor region and implanting thereafter impurities in a self-aligned manner to establish an LDD, anodically oxidizing the gate electrode and introducing impurities to form source and drain regions, partially or wholly removing the anodic oxide from the surface of the island-like semiconductor region to expose the LDD region, and irradiating a laser beam or an intense light having an intensity equivalent to that of the laser beam to activate the impurity region inclusive of the LDD.

Abstract: The present invention relates to a method of forming lightly doped drains in metallic oxide semiconductor (MOS) components. The method includes forming a first, second, and third insulating layer above a silicon substrate having a gate, etching back the layers to leave behind L-shaped first spacers on sidewalls of the gate, followed by doping second type ions into the silicon substrate to form first lightly doped drains in the silicon substrate surface below the L-shaped first spacers, and second lightly doped drains in the silicon substrate surface elsewhere, further forming a fourth insulating to form third spacers, and using the using the third spacers, the first insulating layer, and the gate as masks when doping second type ions into the silicon substrate so as to form source/drain regions in silicon substrate surfaces not covered by the third spacers. Such a method produces greater yield and reduces leakage current from the transistor components.

Abstract: A process sequence for fabricating CMOS devices of the LDD type includes forming spacers along the sides of gates defined on p- and n-regions of the device. In a two-mask sequence, a thin layer of silicon dioxide is utilized to protect the n-region spacers while the p-region spacers are etched away. In one-mask variants of this sequence, a thin layer of silicon oxynitride is utilized to prevent oxide growth over one type of region while an oxide implant mask is grown on the surface of the other type of region and on exposed surfaces of the gates overlying the other type of region.

Abstract: An asymmetrical IGFET including a lightly and heavily doped drain regions and an ultra-heavily doped source region is disclosed. Preferably, the lightly doped drain region and ultra-heavily doped source region provide channel junctions.

Abstract: A method for fabricating a CMOSFET includes the steps of forming a first well of a first conduction type and a second well of a second conduction type on a substrate of the first conduction type; forming gate electrodes having sides on the first well and the second well; forming semiconductor sidewall spacers of the first conduction type at the sides of the gate electrodes; forming a semiconductor layer of the second conduction type over the first well; implanting impurity ions of the first conduction type into the second well; and annealing the semiconductor substrate to form lightly doped shallow impurity regions of the first conduction type in the first and second wells under the semiconductor sidewall spacers, and heavily doped deep impurity regions of the second conduction type in the first well, and simultaneously activating the impurity ions in the second well to formed heavily doped deep impurity regions of the first conduction type in the second well.

Abstract: A semiconductor device fabrication process in which an active region of a semiconductor device is formed by diffusing a dopant out of a sidewall spacer. According to the process, a gate electrode is formed on a substrate and an active region of the substrate adjacent the gate electrode is doped with a first dopant of a first conductivity type to form a heavily-doped region in the active region. A spacer layer having a second dopant disposed therein is then formed. The second dopant has a second conductivity type opposite of the first conductivity type. Portions of the spacer layer are removed to form a spacer containing the second dopant on a sidewall of the gate electrode. The second dopant is diffused out of the spacer into a portion of the heavily-doped region to form a lower conductivity region in the active region. The lower conductivity region may form an LDD region of an LDD structure.

Abstract: A metal oxide semiconductor field effect transistor includes source and drain regions formed between a gate. The gate comprises a first conductive layer and a second conductive layer formed on the first conductive layer, and the second conductive layer has curved sidewalls with an insulating layer formed adjacent to the sidewalls. The method of making such a transistor improves the fabrication process, since the deposition thickness is controlled rather than the amount of etching. The transistor has a shortened channel width with reduced overlap capacitance, and the LDD doping compensation phenomenon is removed.

Abstract: A process for manufacturing a semiconductor device which prevents a short-circuit between a source region, a drain region and a gate electrode of a transistor. The process includes forming a sacrificial BPSG film on at least one of a top surface and a sidewalls of the gate electrode of the transistor, and forming a silicide film and removing the BPSG film by etching through a thin, incomplete, and unwanted silicide film formed on the BPSG film. In the step of removing the BPSG film, the unwanted silicide film formed on the BPSG film is also removed.

Abstract: A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N-LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.

Abstract: A semiconductor device having a reduced junction capacitance of the source and drain and a method for manufacturing same. The method includes the steps of selectively forming an element separating region on a main surface of a <100> oriented semiconductor substrate of a first conductivity type, a step of providing a gate electrode on the region separated by the element separating region with an intervening insulating film, and a step of implanting impurities of a second conductivity type in regions under the source and drain regions using the gate electrode as a mask and with a predetermined angle of ion implantation to generate a channeling implantation condition.

Abstract: A method for forming an asymmetrical LDD structure is described. A polysilicon gate electrode is formed overlying a layer of gate silicon oxide on the surface of a semiconductor substrate. The surfaces of the semiconductor substrate and the gate electrode are oxidized to form a surface oxide layer. Polysilicon spacers are formed on the sidewalls of the gate electrode wherein one side of the gate electrode is a source side and the other side of the gate electrode is a drain side. The polysilicon spacer on the source side of the gate electrode is removed. First ions are implanted to form heavily doped source and drain regions within the semiconductor substrate not covered by the gate electrode and the polysilicon spacer on the drain side of the gate electrode. Then the drain side polysilicon spacer is removed.

Abstract: A integrated circuit field effect transistor is formed with device isolation regions disposed on opposite sides of the transistor, each of which include a shallow insulation-filled trench region which abuts an insulating region underlying an active region of the transistor. A pair of spaced apart insulation-filled trench regions are formed in a semiconductor substrate at a surface of the substrate. An insulated gate is formed on the substrate between and separated from the insulation-filled trench regions. Spaced apart source and drain insulating regions are formed in the substrate, a respective one of which is disposed between the insulated gate and a respective one of the insulation-filled trench regions. Corresponding spaced apart source and drain regions are then formed on the spaced apart source and drain insulating regions. The insulated gate is formed overlying a channel region disposed between lightly doped source and drain regions.

Abstract: An electrostatic discharge protection device structure having a lightly doped drain area at the source to allow a faster time to start conduction in an electrostatic discharge event and an abrupt junction at the drain to allow for a low voltage during the conduction of an electrostatic discharge event. The electrostatic discharge protection device structure will be fabricated using standard lightly doped drain CMOS processing.

Abstract: A method for fabricating a metal oxide semiconductor field effect transistor, capable of achieving a reduction in topology by forming a trench on a silicon substrate by use of a temporary field oxide film and forming a gate electrode in the trench and capable of eliminating occurrence of a spiking phenomenon due to a metal wiring being in direct contact with the silicon substrate by forming a silicide film on a source and a drain, and capable of obtaining an increased contact margin of the metal wiring by overlapping the silicide film with a field oxide film formed on the silicon substrate.