Abstract: Disclosed is a method comprising providing a silicon surface with an underlying insulator layer, providing a plurality of gates adjacent to source/drain regions, growing source/drains between the said gates such that the source/drains are thicker in regions of larger gate-to-gate pitch, and doping the source/drains with one or more dopants such that the dopants abut the underlying insulator layer.

Abstract: The present invention provides a method of forming a PMOS transistor or an NMOS transistor on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate and a gate positioned on a predetermined area of the silicon substrate. First, a protection layer of uniform thickness made of silicon nitride is formed on the semiconductor wafer to cover the surface of the gate. Then, a first ion implantation process is performed to form a first ion implantation layer with a first predetermined thickness on the silicon substrate around the gate. Then, an RCA cleaning process is performed to remove impurities on the semiconductor wafer. Next, a spacer is formed around the gate. Finally, a second ion implantation process is performed to form a second ion implantation layer with a second predetermined thickness on the silicon substrate around the gate. The second ion implantation layer is used as a source or drain (S/D) of the MOS transistor.

Abstract: Metal Oxide Semiconductor Field Effect Transistors (MOSFET) are disclosed. One MOSFET includes, a substrate having a well of a first conductivity type. The MOSFET also includes source and drain regions, of a second conductivity type, formed in the well arranged apart from each other. Moreover, the MOSFET includes a first region, of a second conductivity type, formed in the well near the drain region. The first region has a low doping. Furthermore, the MOSFET includes a second region of a second conductivity type, formed near the source region. The second region has a doping substantially higher than the doping of the first region. A second MOSFET includes a substrate having a well of a first conductivity type and source and drain regions, of a second conductivity type, formed in the well apart from each other. Moreover, the MOSFET includes a drain extension region of the second conductivity type, formed in the well near the drain region.

Abstract: A semiconductor device having a gate electrode on a Si-substrate through a gate oxide film; a first impurity diffusion region having a conductivity type reversed to a well which will form a part of source and drain regions in the two opposing sides of the gate electrode through gate electrode sidewall dielectric films; a second impurity diffusion region having the same conductivity type as the first impurity diffusion region beneath the gate electrode sidewall dielectric film, touching a channel region directly below the gate electrode and being shallower than the first impurity diffusion region; a titanium silicide film on the gate electrode and the surface of the Si-substrate of the first impurity diffusion region in the two opposing sides of the gate electrode sidewall dielectric film; and a third impurity diffusion region, formed in the first impurity diffusion region, having a higher concentration than the first impurity diffusion region and the same conductivity type as the first and second impurity dif

Abstract: For forming a highly conductive junction in an active device area of a semiconductor substrate, a first dopant is implanted into the active device area to form a preamorphization region. A second dopant is then implanted into the preamorphization region to have a dopant profile along a depth of the preamorphization region, and the dopant profile has a dopant peak within the preamorphization region. A RTA (Rapid Thermal Anneal) is performed to recrystallize a portion of the preamorphization region from an interface between the preamorphization region and the semiconductor substrate to below the dopant peak. A LTP (Laser Thermal Process) is then performed to recrystallize a remaining portion of the preamorphization region that has not been recrystallized during the RTA (Rapid Thermal Anneal) to activate a substantial portion of the second dopant in the preamorphization region.

Abstract: A method for a T-gate and salicide process that allows narrow bottom gate widths below 0.25 &mgr;m and wide top gate widths to allow silicide gate contacts on the top of the T-gate. A dummy gate composed of an insulating material is formed over the substrate. Then we form LDD regions adjacent to the dummy gate preferably by ion implanting f (I/I) impurity ions into the substrate using the dummy gate as a mask. A pad oxide layer and dielectric layer are formed over the substrate surface. The dielectric layer over the dummy gate is removed preferably by a CMP process. We then remove the dummy gate to form a gate opening exposing the substrate surface. A gate dielectric layer is formed over the substrate surface in the gate opening. We form a polysilicon layer over the dielectric layer and the substrate surface in the gate opening. The polysilicon layer is patterned to form a T-gate. The dielectric layer is removed. We forming source/drain (S/D) regions adjacent to the T-gate by an Ion implant process.

Abstract: A MOS transistor of the present invention includes a semiconductor substrate of a first conductivity type impurity, a gate insulating layer formed on the semiconductor substrate, gate electrodes formed on the gate insulating layer, and an oxide layer formed by surface oxidation of the gate electrodes. A first spacer is formed on the side wall of the gate electrodes, and a second spacer is formed on the inclined side wall. A first impurity layer of low concentration is formed at a first depth by a second conductivity type impurity implanted in the vicinity of surface of the semiconductor substrate to be self-aligned at the edge of the gate electrode. A second impurity layer of middle concentration is formed at a deeper second depth than the first depth by the second conductivity type impurity implanted in the vicinity of surface of the semiconductor substrate.

Abstract: A semiconductor device fabrication method and resulting device in which a gate insulating film is formed on a semiconductor substrate, a gate electrode is formed on the gate insulating film, a gate cap is formed on the gate electrode, a heavy density impurity region is formed in the substrate and outside the gate electrode, first side walls are formed on sides of the gate electrode, the gate cap and the gate insulating film. The substrate outside the gate insulating film is etched down to a portion having a highest impurity density, and a light doping region surrounding the heavy impurity region is formed in the substrate. The method and resulting device prevents a hot carrier from being injected into a gate oxide film or a side wall, and reduces the generation of a junction current leakage and a short channel.

Abstract: A method for forming borderless contact capable of reducing junction leakage current by forming a deep junction in the source/drain region nearest the borderless contact to eliminate most of the leakage current. The method includes the steps of first forming a shallow trench isolation structure for isolating devices in a semiconductor substrate. In the subsequent step, an ion implantation is carried out implanting ions at a small tilt angle to form source/drain regions such that source/drain region nearest to the shallow trench isolation structure has a deep junction. Finally, a borderless opening is formed above the source/drain region and the shallow trench isolation structure, and then conductive material is deposited into the borderless opening to form the borderless contact.

Abstract: The invention comprises a method of determining the thermal straggle of microelectronic devices having a pocket dopant implant that is formed under substantially the same doping conditions. The method comprises measuring the operating characteristics of each device (32) and obtaining a one-dimensional doping profile of dopant ions in the devices (30). A total lateral straggle of the dopant ions in the devices is determined in response to the operating characteristics and the one-dimensional doping profile of the dopant ions (34). An as-implanted straggle of the dopant ions in the devices is determined in response to the doping conditions (36). A thermal straggle of the dopant ions is calculated utilizing the as-implanted straggle and the total lateral straggle (38).

Abstract: A method is disclosed in which a low-resistance portion of the gate electrode of a transistor is formed independently of the formation of low-resistance portions in the drain and source regions. Accordingly, the device features a thick low-resistance portion in the gate electrode, for example, a thick gate silicide for supporting low gate delays by minimizing the gate resistance, and a thin low-resistance portion in the drain and source in order to meet the requirements for shallow junction integration. Moreover, a transistor is disclosed having a low-resistance gate electrode portion, the composition of which is different from the low-resistance portion of the drain and source.

Abstract: A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; b) masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and c) in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration

Abstract: After a source-drain region is formed, fluorine 24 is ion-implanted into the entire surface of a substrate and thereafter a heat treatment is conducted, for example, at 600 to 800° C. Through this heat treatment, the dangling binds and the Si—H bonds in the channel regions 26 are substituted by the Si—F bonds, which prevents the generation of the negative bias temperature instability effect in a MOSFET.

Abstract: A method of fabricating a semiconductor device wherein there is provided a semiconductor substrate, preferably of silicon, having a gate insulator thereover, preferably of silicon dioxide, forming a junction, preferably a silicon/silicon dioxide interface, and a gate electrode, preferably of doped polysilicon, over the partially fabricated device. Deuterium is implanted into the structure and the deuterium is caused to diffuse through the deivce. The device fabrication is then completed.

Abstract: The present invention is directed to a control method for maintaining the drive current of a transistor within acceptable limits. The method comprises determining a size variation of a component of a transistor, e.g., the width of a gate conductor, the width of sidewall spacers or the thickness of the gate dielectric, determining the parameters of an anneal process based upon the determined size variation of the component and performing the anneal process using the determined parameters.

Abstract: The present invention provides a CMOS process, wherein a halo structure can be fabricated without employing an additional lithographic mask for protecting the transistors of the opposite conductivity during a halo implant. The halo implant has a projected range or depth that lies in the range of an LIP implant or a counter-doping implant in the well containing the transistors of the opposite conductivity. The LIP or counter-doping implant effectively cancels the halo impurities.

Abstract: A method for increasing gate surface area for depositing silicide material. A silicon substrate having device isolation structures therein is provided. A stack of sacrificial layers comprising a first sacrificial layer at the bottom, a second sacrificial layer in the middle and a third sacrificial layer on top is formed over the silicon substrate. A gate opening that exposes a portion of the substrate is formed in the stack of sacrificial layers. A portion of the second sacrificial layer exposed by the gate opening is next removed to form a side opening on each side of the gate opening. The gate opening together with the horizontal side opening form a cross-shaped hollow space. A gate oxide layer is formed at the bottom of the gate opening. Polysilicon material is deposited to fill the gate opening and the side openings, thereby forming a cross-shaped gate polysilicon layer. The third, the second and the first sacrificial layers are removed. A metal silicide layer is formed over the gate polysilicon layer.

Abstract: A method (100) of forming a transistor (50, 80) includes forming a gate oxide (120) over a portion of a semiconductor material (56, 122) and forming a doped polysilicon film (124) having a dopant concentration over the gate oxide (122). Subsequently, the doped polysilicon film (124) is etched to form a gate electrode (52) overlying a channel region (58) in the semiconductor material (56, 122), wherein the gate electrode (52) separates the semiconductor material into a first region (60) and a second region (68) having the channel region (58) therebetween. The method (100) further includes forming a drain extension region (64) in the first region (60) and a source extension region (72) in the second region (68), and forming a drain region (62) in the first region (60) and a source region (70) in the second region (68). The source/drain formation is such that the drain and source regions (62, 70) have a dopant concentration which is less than the polysilicon film (124) doping concentration.

Abstract: A process for fabricating input/output, N channel, (I/O NMOS) devices, featuring an ion implanted nitrogen region, used to reduce hot carrier electron, (HEC), injection, has been developed. The process features implanting a nitorgen region, at the interface of an overlying silicon oxide layer, and an underlying lightly doped source/drain, (LDD), region. The implantation procedure can either be performed prior to, or after, the deposition of a silicon oxide liner layer, in both cases resulting in a desired nitrogen pile-up at the oxide-LDD interface, as well as resulting, in a more graded LDD profile. An increase in the time to fail, in regards to HCE injection, for these I/O NMOS devices, is realized, when compared to counterparts fabricated without the nitrogen implantation procedure.

Abstract: A non-volatile semiconductor memory device including a memory cell having a memory transistor and a selection transistor, comprising: a composite gate structure of the memory transistor formed on a surface of a semiconductor substrate at its first region with a first insulating film interposed therebetween and including a laminate of a floating gate electrode, a second insulating film and a control gate electrode; a gate electrode of the selection transistor formed on the surface of the semiconductor substrate at its second region close to the first region with a third insulating film interposed therebetween; and an impurity diffusion layer formed in the semiconductor substrate at its region between the first and second regions and functioning as a drain of the memory transistor, common to a source of the selection transistor, the impurity diffusion layer having at least an extension region extending to a part of the semiconductor substrate disposed under the composite gate structure, the extension region hav

Abstract: This invention teaches methods and apparatus for forming self-aligned photosensitive material spacers about protruding structures in semiconductor devices. One embodiment of the invention is a method for forming a LDD structure, utilizing disposable photosensitive material spacers. A second embodiment of the invention comprises a method for forming a transistor, having salicided source/drain regions, utilizing photosensitive polyimide spacers for forming the salicided source/drain regions, without disposing of the spacers. A third embodiment of the invention comprises a method for creating an offset from a protruding structure on a semiconductor substrate, using disposable photosensitive material spacers.

Abstract: Disclosed herein is a method of forming a gate in a semiconductor device capable of preventing a deterioration in the property of a gate electrode formed of a refractory metal in a heat treatment process.

Abstract: A method for fabricating a self-aligned ultra short channel. The method uses double spacers as a hard mask, so that DRAM with the ultra short channel is formed in a self-aligned process. This method not only reduces the channel length, but also adjusts the dopants in lightly doped drains (LDD) at a side of the storage node opening and at the side of the bit line, respectively, so as to optimize the device property.

Abstract: Semiconductor devices of different conductivity types are formed on a semiconductor substrate using a minimal number of critical masks. Embodiments include forming conductive gates on the main surface of the semiconductor substrate, and disposable amorphous silicon spacers on the sidewalls of the gates. A photoresist mask is then formed on gates and portions of the main surface intended to be implanted with impurities of a first conductivity type. Moderate or heavy source/drain implants of a second impurity type are then formed in the substrate, the disposable spacers on the unmasked gates are then removed, and lightly or moderately doped source/drain extension implants of the second impurity type are formed in the substrate. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates and implanted portions of the main surface.

Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor. A substrate having a gate structure is provided. The method of the invention includes forming a liner spacer on each side of the gate structure and a low dopant density region deep inside the substrate. The low dopant density region has a lower dopant density than that of a lightly doped region of the MOS transistor. Then a interchangeable source/drain region with a lightly doped drain (LDD) structure and an anti-punch-through region is formed on each side of the gate structure in the low dopant density region. The depth of the interchangeable source/drain region is not necessary to be shallow.

Abstract: A process for forming a shallow source/drain region, for a sub-micron MOSFET device, has been developed. The process features a process sequence comprised of a series of ion implantation procedures, followed by a low temperature, rapid thermal anneal procedure. Each ion implantation procedure, uses a specific energy and a specific dose, resulting in a series of ion implant regions, each located at a specific depth in the semiconductor substrate. A rapid thermal anneal is used to activate the implanted ions, forming the shallow source/drain region. The creation of several ion implant regions, reduced the risk of crystal damage which can result with the use of a single, more concentrated, ion implant region. The risk of crystal damage is also reduced via the use of a rapid thermal anneal procedure, which can be employed at lower temperatures than counterpart anneal procedures, that are used to distribute ions from a single, ion implanted region.

Abstract: Disclosed is a method of manufacturing a semiconductor device which includes a source region, a channel region, a drain region, a gate electrode formed on the channel region through a gate insulating film 6 and a drift region (N− layer 22) formed between the channel region and the drain region, wherein the process of forming the drift region (N− layer) comprises the steps of: ion-implanting and diffusing at least two kinds of second conduction type impurities (e.g. phosphorus and arsenic ions) having different diffusion coefficients in a P-type well region 21; ion-implanting at least one kind first conduction type impurities (e.g. boron ions) having a diffusion coefficient substantially equal to or larger than that of at least one of said second conduction type impurities (e.g. phosphorus); and diffusing the first conduction type impurities after the gate insulating film 6 has been formed.

Abstract: A method of forming a MOSFET device is provided. First lightly doped regions are formed, the first lightly doped regions including LDD extension regions of the device. Second very lightly doped regions are formed at least partially below the first lightly doped regions, respectively, the second very lightly doped regions having a dopant concentration less than the first lightly doped regions, and the second very lightly doped regions being implanted at a higher energy level than the first lightly doped regions.

Abstract: An embodiment of the instant invention is a method of fabricating an electronic device over a semiconductor substrate, the method comprising the steps of: forming a doped polycrystalline silicon layer insulatively disposed over the semiconductor substrate; and subjecting the doped polycrystalline silicon layer to a temperature of around 700 to 1100 C. in an oxidizing ambient for a period of around 5 to 120 seconds. Preferably, the oxidizing ambient is comprised of: O2,O3, NO, N2O, H2O, and any combination thereof. The temperature is, preferably, around 950 to 1050 C. (more preferably around 1000 C.). The step of subjecting the doped polycrystalline silicon layer to a temperature of around 700 to 1100 C. in an oxidizing ambient for a period of around 5 to 120 seconds, preferably, forms an oxide layer on the polycrystalline silicon layer, which has a thickness which is, preferably, greater than the thickness of a native oxide layer.

Abstract: A method of asymmetrically doping a region beneath a gate by controlling the lateral surface profile of the gate using a mask. A first embodiment of the method includes forming a mask over the gate such that it extends beyond the opposing sides of the gate in an uneven manner. A second embodiment of the method includes forming a mask including sidewall spacers on both sides of the gate in an uneven manner. The uneven manner of providing the mask for ion implantation can be used to define an asymmetric lateral channel profile, which can be advantageously used to vary gate overlap, channel VT, or source/drain doping as necessary.

Abstract: A semiconductor fabrication method is provided for the fabrication of a polysilicon-based load circuit (called poly-load) for SRAM (static random-access memory). In accordance with this method, a lightly doped polysilicon layer is formed. This lightly doped polysilicon layer is doped with an impurity element to a predetermined concentration corresponding to the desired resistive characteristic of the poly-load. Further, this lightly-doped polysilicon layer is partitioned into two parts: a first part to be formed into the desired poly-load and a second part to be formed into a conductive interconnecting line that is electrically connected to the poly-load. After this, a metal silicide layer is formed over the second part of the lightly doped polysilicon layer to serve as the conductive interconnecting line. Next, an ILD (Inter Layer Dielectric) layer is formed over the poly-load and the conductive interconnecting line, and then the ILD layer is subjected to a densification process.

Abstract: The level converting circuit includes a first current cutting circuit, a second current cutting circuit, a level shift circuit and an inverter. The first current cutting circuit includes two PMOS transistors connected to a node having a boosted potential Vpp. The second current cutting circuit includes two NMOS transistor connected to a ground node. The level shift circuits include two PMOS transistors and two NMOS transistors. Before a through current flows between the node having the boosted potential Vpp and the ground node, any of the transistor included in the first current cutting circuit and any of the transistors included in the second current cutting circuits are turned off. Therefore, through current between the node having the boosted potential Vbb and the ground node can be prevented.

Abstract: An IGFET with elevated source and drain regions in close proximity to a gate with sloped sidewalls is disclosed. A method of making the IGFET includes forming a lower gate level over a semiconductor substrate, wherein the lower gate level includes a top surface, a bottom surface and sloped opposing sidewalls, and the top surface has a substantially greater length than the bottom surface, and depositing a semiconducting layer on the lower gate level and on underlying source and drain regions of the semiconductor substrate to form an upper gate level on the lower gate level, an elevated source region on the underlying source region, and an elevated drain region on the underlying drain region. The elevated source and drain regions are separated from the lower gate level due to a retrograde slope of the sidewalls of the lower gate level, and the elevated source and drain regions are separated from the upper gate level due to a lack of step coverage in the semiconducting layer.

Abstract: A method for providing triangle shapes of high-density plasma CVD film, thereby the grad and source/drain implantation can be applied in the same step, and an offset source/drain mask layer can be eliminated. A substrate is provided incorporating a device, wherein the device is defined as a high-voltage MOS region. Sequentially, a plurality of field oxides are formed on the substrate, one of the field oxides is spaced from another of the field oxides by a high-voltage MOS region. Then, a gate oxide layer is formed above the silicon substrate. Moreover, a polysilicon layer is deposited over the gate oxide layer. A photoresist layer is formed above the polysilicon layer and gate oxide layer, wherein the photoresist layer is defined and etched to form a gate. Then, the photoresist layer is removed. Consequentially, a dielectric layer is deposited and etched above the polysilicon layer by using high-density plasma CVD to result in the inherit triangle shape of high-density plasma CVD film characteristic.

Abstract: A method of for fabrication a metal oxide semiconductor transistor is described. A substrate with an isolation structure thereon is provided. A gate oxide layer is formed on the substrate. A polysilicon layer is formed on the gate oxide layer. The polysilicon layer is patterned to form a gate on the gate oxide layer. An offset spacer is formed on the sidewall of the gate. A source/drain extension is formed in the substrate on two sides of the gate by ion implantation. An insulating spacer is formed on the sidewall of the offset spacer. A source/drain region is formed in the substrate by ion implantation using the gate, the offset spacer and the insulating spacer as a mask. Salicide is formed on the gate and on the surface of the source/drain region. After forming the salicide, the offset spacer is removed. After removing the offset spacer, a halo doped region is formed in the substrate below the source/drain extension by ion implantation.

Abstract: A method for fabricating an integrated circuit transistor begins with doping the substrate in the device active areas after field oxide regions have been formed. This dopant helps to reduce short channel transistor effects. A thin layer of epitaxial silicon is then grown over the substrate active regions. A field effect transistor is formed in the epitaxial layer and underlying substrate. The transistor channel region is in the relatively lightly doped epitaxial layer, but the underlying doped substrate layer helps minimize short channel effects.

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions which utilizes a dual amorphization technique. The technique creates a shallow amorphous region and a deep amorphous region 300 nm thick. The shallow amorphous region is between 10-15 nm below the top surface of the substrate, and the deep amorphous region is between 150-200 nm below the top surface of the substrate. The shallow amorphous region helps to reduce ion implant channeling effects, and the deep amorphous region helps to getter point defects generated during dopant implants. The process can be utilized for P-channel or N-channel metal field effects semiconductor transistors (MOSFETs).

Abstract: An integrated circuit transistor and a method for making the same are provided. The transistor is resistant to junction shorts due to the overetch of local interconnect trenches. The transistor includes a source/drain region with a first junction and a second junction that is located deeper than the first junction in the portion of the active area susceptible to the overetch junction short phenomena. The second junction is established by ion implantation through a mask that is patterned to create an opening corresponding to the intersection of the layouts of the active area and the local interconnect trench. Using this method, the second junction is only established where needed to prevent shorting and does not impede transistor performance.

Abstract: A new method is provided for the creation of an ESD protection device for deep submicron semiconductor technology. An STI trench is created and filled with oxide. The surface of the STI region is polished after which a gate structure is created over the STI region. A high energy ESD implant is performed that is self-aligned with the created gate structure after which the EDS device structure is completed by implanting the source and drain regions of the ESD device.

Abstract: In the manufacture of integrated circuits with an embedded non-volatile memory, it is known to first provide the greater part of the memory and subsequently provide the CMOS logic in a second series of steps of a standard CMOS process. By virtue of this separation of process steps, it is possible to optimize the non-volatile memory substantially without degrading the logic. According to the invention, this process is further optimized in that, particularly for the periphery of the memory, and simultaneously with the memory transistors (21, 24, 27), transistors are manufactured which can cope with a higher voltage than the transistors of the logic. In the case of an EEPROM, each cell of the memory is provided with such a high-voltage transistor as a selection transistor (22, 24).

Abstract: A method for doping a poly depleted semiconductor transistor, the semiconductor transistor including a gate region, a source region adjacent the gate region and a drain region adjacent the gate region and opposite the source region, the method comprising steps of exposing the gate region to a first ion implantation and shielding the gate region from a second ion implantation step.

Abstract: The invention relates to a method of manufacturing a field effect transistor, in particular a discrete field effect transistor, comprising a source region (1) and a drain region (2) and, between said regions, a channel region (4) above which a gate region (3) is located. The gate region (3) is formed by applying an insulating layer (5) to the semiconductor body and providing this insulating layer with a stepped portion (6) in the thickness direction, whereafter a conductive layer (30) is applied to the surface of the semiconductor body (10), which layer is substantially removed again by etching, so that a part (3A) of the conductive layer (30), which part forms part of the gate region (3) and which lies against the stepped portion (6), remains intact.

Abstract: The present invention provides a method for fabricating a submicron metal-oxide semiconductor field-effect transistor (MOSFET). The method includes providing a gate on a substrate, the substrate having a source side and a drain side, the drain side having a spacer area; forming a spacer at the spacer area; performing a halo implant at the source side and the drain side, wherein the spacer prevents implantation in the spacer area, where the spacer facilitates formation of a lateral asymmetric channel; forming heavily doped extensions in the source side and the drain side, where the spacer prevents doping in the spacer area; removing the spacer; and forming a lightly doped extension in the drain side, where the heavily doped extensions and the lightly doped extension prevent hot carrier injection.

Abstract: A method of making a MOS transistors in an integrated circuit includes forming a plurality of doped source and drain regions adjacent respective gate structures that include gate dielectrics, gate conductors and spacers. The plurality of doped source and drain regions are formed at different depths, at different doses and with differing dopants. In one embodiment, first doped source and drain regions are formed at a first depth, at a first dose using a first dopant while second doped source and drain regions are formed at a second depth, at a second dose using a second dopant. The first depth is shallower than the second depth so that the first doped source and drain regions serve as sacrificial doped regions that are consumed in a silicidation process when they are converted into a silicide by being combined with a silicidation metal. However, the second doped source and drain regions maintain their doping profiles and dopant levels.

Abstract: In order to produce a MOS transistor with HDD profile and LDD profile, the HDD profile is firstly formed, followed by the LDD profile, in the area for the LDD profile in order to produce steep dopant profiles. The LDD profile is preferably produced by etching and in situ doped selective epitaxy.

Abstract: An integrated circuit fabrication process is provided for forming a transistor in which the channel length is mandated by the width of a gate conductor formed upon a gate dielectric having a dielectric constant greater than about 3.8. The thickness of the gate dielectric may be made sufficiently large to serve as a mask during subsequent implantation of impurities into a substrate. The gate conductor and the gate dielectric are first patterned using lithography and an etch step. In one embodiment, a masking layer is then formed across a select portion of the gate conductor and an ensuing source region of the substrate. The uncovered portion of the gate conductor is etched to expose a region of the gate dielectric. A first implant of impurities is forwarded into regions of the substrate not covered by the masking layer to form an LDD area underneath the exposed region of the gate dielectric and a heavily doped drain region laterally adjacent the LDD area.

Abstract: A method of developing a transistor, such as a complimentary MOS (CMOS) transistor, that includes lightly doped drain (LDD) regions which uses disposable spacers, and includes the step of adding an oxide spacer etch after a disposable nitride spacer removal and between source/drain implant and LDD implant. Because of this additional step, an ultra shallow LDD implant can be achieved. Moreover, uniformity of the depth of the junction is improved as the non-uniformity of the screen/liner oxide is eliminated.

Abstract: The present invention provides a method and system for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects. The method and system includes implanting first low-dose arsenic into an area in the substrate, thermally diffusing the first low-dose arsenic through a portion of the substrate, implanting a second higher-dose arsenic into the area in the substrate, and diffusing the second higher-dose arsenic into the area in the substrate. Under the present invention, the combination of the first and second arsenic implants has a graded lateral profile which reduces band-to-band tunneling current and short-channel effects. The method also improves the reliability and performance of the semiconductor devices.

Abstract: A method of forming an asymmetric transistor and an asymmetric transistor. The method includes patterning a first spacer material and a second spacer material over a gate electrode material on a substrate with one side of the second spacer material adjacent to a first spacer material. The gate electrode material is patterned according to the first spacer material and the second material. Junction regions are formed in the substrate adjacent to the gate electrode material. One of the first spacer material and the second spacer material is then removed and the gate electrode material is patterned into a gate electrode according to the other of the first spacer and the second spacer material. Finally, second junction regions are formed in the substrate adjacent to gate electrode.

Abstract: A method of forming a MOS transistor. According to the method of the present invention, a pair of source/drain contact regions are formed on opposite sides of a gate electrode. After forming the pair of source/drain contact regions, semiconductor material is deposited onto opposite sides of the gate electrode. Dopants are then diffused from the semiconductor material into the substrate beneath the gate electrode to form a pair of source/drain extensions.