Abstract: A semiconductor wafer including an electrostatic discharge (ESD) protective device, and methods for fabricating the same. In one aspect, the method includes forming a first semiconductor device in a first semiconductor die region on the semiconductor wafer; forming a second semiconductor device in a second semiconductor die region on the semiconductor wafer; and forming a protective device in a scribe line region between (i) the first semiconductor die region and (ii) the second semiconductor die region.

Abstract: A method of manufacturing a display device, the method including forming a first layer on a rigid glass substrate, the first layer having a hydrophobic surface; forming a second layer to be bonded to a rigid thin glass substrate on the first layer to prepare a carrier substrate; bonding the rigid thin glass substrate onto the second layer; forming and encapsulating a display portion on an upper surface of the rigid thin glass substrate; and irradiating a laser beam to delaminate the first layer and detaching the rigid thin glass substrate from the rigid glass substrate.

Abstract: The present disclosure relates to a method and apparatus to increase breakdown voltage of a semiconductor power device. A bonded wafer is formed by bonding a device wafer to a handle wafer with an intermediate oxide layer. The device wafer is thinned substantially from its original thickness. A power device is formed within the device wafer through a semiconductor fabrication process. The handle wafer is patterned to remove section of the handle wafer below the power device, resulting in a breakdown voltage improvement for the power device as well as a uniform electrostatic potential under reverse biasing conditions of the power device, wherein the breakdown voltage is determined. Other methods and structures are also disclosed.

Abstract: A method is disclosed which includes: forming at least one layer of material on at least part of a surface of a first substrate, wherein a first surface of the at least one layer of material is in contact with the first substrate thereby defining an interface; attaching a second substrate to a second surface of the at least one layer of material; forming bubbles at the interface; and applying mechanical force; whereby the second substrate and the at least one layer of material are jointly separated from the first substrate. Related arrangements are also described.

Abstract: A method for manufacturing a semiconductor device makes it possible to efficiently polish with a polishing tape a peripheral portion of a silicon substrate under polishing conditions particularly suited for a deposited film and for silicon underlying the deposited film. The method includes pressing a first polishing tape against a peripheral portion of a device substrate having a deposited film on a silicon surface while rotating the device substrate at a first rotational speed, thereby removing the deposited film lying in the peripheral portion of the device substrate and exposing the underlying silicon. A second polishing tape is pressed against the exposed silicon lying in the peripheral portion of the device substrate while rotating the device substrate at a second rotational speed, thereby polishing the silicon to a predetermined depth.

Abstract: In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.

Abstract: A manufacturing method is provided which achieves an SOI substrate with a large area and can improve productivity of manufacture of a display device using the SOI substrate. A plurality of single-crystalline semiconductor layers are bonded to a substrate having an insulating surface, and a circuit including a transistor is formed using the single-crystalline semiconductor layers, so that a display device is manufactured. Single-crystalline semiconductor layers separated from a single-crystalline semiconductor substrate are applied to the plurality of single-crystalline semiconductor layers. Each of the single-crystalline semiconductor layers has a size corresponding to one display panel (panel size).

Abstract: A light-emitting element, a light-emitting module, a light-emitting panel, or a light-emitting device in which loss due to electrical resistance is reduced is provided. The present invention focuses on a surface of an electrode containing a metal and on a layer containing a light-emitting organic compound. The layer containing a light-emitting organic compound is provided between one electrode including a first metal, whose surface is provided with a conductive inclusion, and the other electrode.

Abstract: A method for testing a strip of MEMS devices, the MEMS devices including at least a respective die of semiconductor material coupled to an internal surface of a common substrate and covered by a protection material; the method envisages: detecting electrical values generated by the MEMS devices in response to at least a testing stimulus; and, before the step of detecting, at least partially separating contiguous MEMS devices in the strip. The step of separating includes defining a separation trench between the contiguous MEMS devices, the separation trench extending through the whole thickness of the protection material and through a surface portion of the substrate, starting from the internal surface of the substrate.

Abstract: A substrate includes a plurality of semiconductor chips arranged in a grid pattern and laterally spaced from one another by channel regions. The substrate includes a vertical stack of a semiconductor layer and at least one dielectric material layer embedding metal interconnect structures. The at least one dielectric material layer are removed along the channel regions and around vertices of the grid pattern so that each semiconductor chip includes corner surfaces that are not parallel to lines of the grid pattern. The corner surfaces can include straight surfaces or convex surfaces. The semiconductor chips are diced and subsequently bonded to a packaging substrate employing an underfill material. The corner surfaces reduce mechanical stress applied to the metal interconnect layer during the bonding process and subsequent thermal cycling processes.

Abstract: A wafer processing laminate, a wafer processing member, a temporary adhering material for processing a wafer, and a method for manufacturing a thin wafer, which facilitates to establish a temporary adhering the wafer and the support, enables to form a layer of uniform thickness on a heavily stepped substrate, and is compatible with the TSV formation and wafer back surface interconnect forming steps, and the wafer processing laminate includes a support, a temporary adhesive material layer formed thereon and a wafer laminated on the temporary adhesive material layer, where the wafer has a circuit-forming front surface and a back surface to be processed, wherein the temporary adhesive material layer includes a three-layered structure composite temporary adhesive material layer.

Abstract: An SOI substrate is manufactured by forming an embrittled layer in a bond substrate by increasing the dose of hydrogen ions in the formation of the embrittled layer to a value more than the dose of hydrogen ions of the lower limit for separation of the bond substrate, separating the bond substrate attached to the base substrate, forming an SOI substrate in which a single crystal semiconductor film is formed over the base substrate, and irradiating a surface of the single crystal semiconductor film with laser light.

Abstract: A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar.

Abstract: A method for manufacturing an SOI wafer that has an SOI layer formed on a buried insulator layer and is suitable for photolithography with an exposure light having a wavelength ? comprises: designing a thickness of the buried insulator layer of the SOI wafer on the basis of the wavelength ? of the exposure light utilized for the photolithography that is to be performed on the SOI wafer after manufacturing; and fabricating the SOI wafer that has the SOI layer formed on the buried insulator layer having the designed thickness. As a result, there is provided a method for designing an SOI wafer and a method for manufacturing an SOI wafer that enable the variation in the reflection rate of the exposure light due to the variation in the SOI layer thickness and hence variation in the exposure state of a resist to be inhibited in a photolithography operation.

Abstract: Methods are provided for handling a device wafer. For example, a method includes providing a stack structure having a device wafer, a handler wafer, and a bonding structure disposed between the device wafer and handler wafer, and irradiating the bonding structure with long-wavelength infrared energy to ablate the bonding structure.

Abstract: A method for manufacturing gallium nitride-based film chip is provided. The method comprises: growing a gallium nitride-based semiconductor multilayer structure on a sapphire substrate; thinning and polishing the sapphire substrate; coating a reflecting compound metal layer on the gallium nitride-based semiconductor multilayer structure by evaporating; coating a first glue on the reflecting compound metal layer and solidifying the first glue with a first temporary substrate; peeling the sapphire substrate off by laser; coating a second glue on the peeling surface and solidifying the second glue with a second temporary substrate; removing the first temporary substrate and the first glue; bonding the reflecting compound metal layer with a permanent substrate by eutectic bonding; removing the second temporary substrate and the second glue.

Abstract: A spalling method is provided that includes depositing a stressor layer on surface of a base substrate, and contacting the stressor layer with a planar transfer. The planar transfer surface is then traversed along a plane that is parallel to and having a vertical offset from the upper surface of the base substrate. The planar transfer surface is traversed in a direction from a first edge of the base substrate to an opposing second edge of the base substrate to cleave the base substrate and transfer a spalled portion of the base substrate to the planar transfer surface. The vertical offset between the plane along which the planar transfer surface is traversed and the upper surface of the base substrate is a fixed distance. The fixed distance of the vertical offset provides a uniform spalling force. A spalling method is also provided that includes a transfer roller.

Abstract: According to one embodiment, in a method of a nitride semiconductor light emitting device, a nitride semiconductor laminated body is formed on a first substrate having a first size. A first adhesion layer with a second size smaller than the first size is formed on the nitride semiconductor laminated body. A second adhesion layer is formed on a second substrate. The first and the second substrates are bonded while the first and second adhesion layers being overlapped each other. The first substrate is removed so as to generate a recess having a third size equal to or larger than the second size. The first substrate is etched until exposing the nitride semiconductor laminated body while injecting a chemical solution into the recess. The exposed nitride semiconductor laminated body is etched using the chemical solution so as to form a concave-convex portion in the exposed nitride semiconductor laminated body.

Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P? layer, and the P? layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P? layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P? layer. Also provided are a non-transitory computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

Abstract: According to an embodiment, a method of forming a semiconductor device includes: providing a wafer having a semiconductor substrate with a first side a second side opposite the first side, and a dielectric region arranged on the first side; mounting the wafer with the first side on a carrier system; etching a deep vertical trench from the second side through the semiconductor substrate to the dielectric region, thereby insulating a mesa region from the remaining semiconductor substrate; and filling the deep vertical trench with a dielectric material.

Abstract: The present invention is a temporary adhesive composition comprising: (A) non-aromatic saturated hydrocarbon group-containing organopolysiloxane; (B) an antioxidant; and (C) an organic solvent, wherein the component (A) corresponds to 100 parts by mass, the component (B) corresponds to 0.5 to 5 parts by mass, and the component (C) corresponds to 10 to 1000 parts by mass. There can be provided a temporary adhesive composition that has excellent thermal stability while maintaining solvent resistance and a method for manufacturing a thin wafer using this.

Abstract: A method and a system are described herein for applying etchant to edges of a plurality of wafers. The system includes a sump configured for holding etchant, a roller having an outer surface in fluid communication with the sump and configured to have etchant thereon, a wafer cassette configured to retain wafers positioned therein so that edges of the wafers are in contact with the roller. The cassette permits axial rotation of the wafers about an axis. A method of applying etchant to the edge of the wafer includes placing the wafer edge in contact with the roller and rotating the roller about a longitudinal axis of the roller. At least a portion of the roller contact an etchant contained in a sump during rotation so that etchant is applied to the wafer edge.

Abstract: An SOI substrate is manufactured by the following steps: a semiconductor substrate is irradiated with an ion beam in which the proportion of H2O+ to hydrogen ions (H3+) is lower than or equal to 3%, preferably lower than or equal to 0.3%, whereby an embrittled region is formed in the semiconductor substrate; a surface of the semiconductor substrate and a surface of a base substrate are disposed so as to be in contact with each other, whereby the semiconductor substrate and the base substrate are bonded; and a semiconductor layer is separated along the embrittled region from the semiconductor substrate which is bonded to the base substrate by heating the semiconductor substrate and the base substrate, so that the semiconductor layer is formed over the base substrate.

Abstract: A method for manufacturing a solid-state imaging device including: forming photo sensor portions in a silicon substrate; forming a wiring portion above said silicon substrate; bonding another substrate onto said wiring portion; removing said substrate in response to performing the bonding of the another substrate onto the wiring portion; and sequentially forming an anti-reflective coating on the silicon substrate, a color filter on the anti-reflective coating, and an on-chip lens.

Abstract: To provide an olefinic expandable substrate and a dicing film that exhibits less contamination characteristics, high expandability without necking, which cannot be achieved by conventional olefinic expandable substrates. In order to achieve the object, an expandable film comprises a 1-butene-?-olefin copolymer (A) having a tensile modulus at 23° C. of 100 to 500 MPa and a propylenic elastomer composition (B) comprising a propylene-?-olefin copolymer (b1) and having a tensile modulus at 23° C. of 10 to 50 MPa, wherein the amount of the component (B) is 30 to 70 weight parts relative to 100 weight parts in total of components (A) and (B).

Abstract: The invention relates to a method for transferring a layer from a donor substrate onto a handle substrate wherein, after detachment, the remainder of the donor substrate is reused. To get rid of undesired protruding edge regions that are due to the chamfered geometry of the substrates, the invention proposes to carry out an additional etching process before detachment occurs.

Abstract: On a single-crystal substrate, a drift layer is formed. The drift layer has a first surface facing the single-crystal substrate, and a second surface opposite to the first surface, is made of silicon carbide, and has first conductivity type. On the second surface of the drift layer, a collector layer made of silicon carbide and having second conductivity type is formed. By removing the single-crystal substrate, the first surface of the drift layer is exposed. A body region and an emitter region are formed. The body region is disposed in the first surface of the drift layer, and has the second conductivity type different from the first conductivity type. The emitter region is disposed on the body region, is separated from the drift layer by the body region, and has first conductivity type.

Abstract: An optical device wafer processing method for processing an wafer having an epitaxy substrate and an optical device layer formed on the front side of the epitaxy substrate through a buffer layer. The buffer layer is to be broken in the condition where the optical device layer is bonded through a bonding metal layer to a transfer substrate. The method includes a buffer layer breaking step of applying a pulsed laser beam having a wavelength having transmissivity to the epitaxy substrate and having absorptivity to the buffer layer from the back side of the epitaxy substrate to the buffer layer, thereby breaking the buffer layer. The buffer layer breaking step includes a first laser beam applying step of completely breaking the buffer layer corresponding to an optical device area and a second laser beam applying step of incompletely breaking the buffer layer corresponding to a peripheral marginal area.

Abstract: The present invention is directed to a method for manufacturing an SOI wafer, the method by which treatment that removes the outer periphery of a buried oxide film to obtain a structure in which a peripheral end of an SOI layer of an SOI wafer is located outside a peripheral end of the buried oxide film, and, after heat treatment is performed on the SOI wafer in a reducing atmosphere containing hydrogen or an atmosphere containing hydrogen chloride gas, an epitaxial layer is formed on a surface of the SOI layer. As a result, there is provided a method that can manufacture an SOI wafer having a desired SOI layer thickness by performing epitaxial growth without allowing a valley-shaped step to be generated in an SOI wafer with no silicon oxide film in a terrace portion, the SOI wafer fabricated by an ion implantation delamination method.

Abstract: In one embodiment, a semiconductor device includes a glass substrate, a semiconductor substrate disposed on the glass substrate, and a magnetic sensor disposed within and/or over the semiconductor substrate.

Abstract: The invention concerns a process of preparing a thin layer to be transferred onto a substrate having a surface topology and, therefore, variations in altitude or level, in a direction perpendicular to a plane defined by the thin layer, this process comprising the formation on the thin layer of a layer of adhesive material, the thickness of which enables carrying out a plurality of polishing steps of its surface in order to eliminate any defect or void or almost any defect or void, in preparation for an assembly via a molecular kind of bonding with the substrate.

Abstract: In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a mechanical device to apply localized pressure to the wafer to separate the back layer in the singulation lines. The localized pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer.

Abstract: A method for producing a bonded substrate having a Si1-xGex (0<x?1) film in which a larger than ever biaxial strain has been introduced. Specifically, the method involves at least the steps of: providing a donor wafer and a handle wafer having a thermal expansion coefficient lower than the donor wafer, implanting ions of any one or both of hydrogen and a noble gas into the donor wafer to form an ion-implanted layer, performing a plasma activation treatment on at least one of bonding surfaces of the donor wafer and the handle wafer, bonding the donor wafer to the handle wafer, splitting the donor wafer through application of a mechanical impact to the ion-implanted layer, performing a surface treatment on a split surface of the donor wafer, and epitaxially growing a Si1-xGex (0<x?1) film on the split surface to thus form a strained Si1-xGex (0<x?1) film on the bonded wafers.

Abstract: Embodiments of the invention generally relate to epitaxial lift off (ELO) thin films and devices and methods used to form such films and devices. In one embodiment, a method for forming a thin film material during an epitaxial lift off process is provided which includes forming an epitaxial material over a sacrificial layer on a substrate, adhering a non-uniform support handle onto the epitaxial material, and removing the sacrificial layer during an etching process. The etching process further includes peeling the epitaxial material from the substrate while forming an etch crevice therebetween and bending the support handle to form compression in the epitaxial material during the etching process. In one example, the non-uniform support handle contains a wax film having a varying thickness.

Abstract: A method of manufacturing a plurality of electronic devices is provided. Each one of a plurality of first conductive terminals on a plurality of integrated circuits formed on a device wafer is connected to a respective one of a plurality of second conductive terminals on a carrier wafer, thereby forming a combination wafer assembly. The combination wafer assembly is singulated between the integrated circuits to form separate electronic assemblies. The combination wafer assembly also allows for an underfill material to be introduced and to cured at wafer level and for thinning of the device wafer at wafer level without requiring a separate supporting substrate. Alignment between the device wafer and the carrier wafer can be tested by conducting a current through first and second conductors in the device and carrier wafers, respectively.

Abstract: A method (90) entails placing (124) sensor elements (122) in an array (126) arranged to correspond with locations of controller dies (24) in a controller wafer (94) and encapsulating (128) the array (126) in a mold material (74) to form a panel (130) of the sensor elements (122). The sensor elements (122) include bond pads (42) that are concealed by a material section (116, 118) of the sensor elements (122). The controller wafer (94) is bonded (134) to the panel (130) to form a stacked wafer structure (136). After bonding, methodology (90) entails forming (140) conductive elements (60) on the controller wafer (95), removing material sections (100) from the controller wafer (94) and removing the material sections (116, 118) from the sensor elements (122) to expose the bond pads (42), forming (148) electrical interconnects (56), applying (152) packaging material (64), and singulating to produce sensor packages (20, 76).

Abstract: Even when a substrate for treatment is joined with a supporting substrate having an outer shape larger than that of the substrate for treatment, with a photothermal conversion layer and an adhesive layer interposed, and the surface of the substrate for treatment on the side opposite this joined surface is treated, the occurrence of a defective external appearance on the treatment surface of the substrate for treatment is prevented. An adhesive layer 4 is formed on one surface of a substrate for treatment 3, a photothermal conversion layer 2 is formed on one surface of a supporting substrate 1 having a surface with an outer shape larger than that of the surface of the substrate for treatment, and the substrate for treatment 3 is bonded onto the surface of the photothermal conversion layer 2 with the adhesive layer 4 interposed, to obtain a layered member.

Abstract: A method of controlled layer transfer is provided. The method includes providing a stressor layer to a base substrate. The stressor layer has a stressor layer portion located atop an upper surface of the base substrate and a self-pinning stressor layer portion located adjacent each sidewall edge of the base substrate. A spalling inhibitor is then applied atop the stressor layer portion of the base substrate, and thereafter the self-pinning stressor layer portion of the stressor layer is decoupled from the stressor layer portion. A portion of the base substrate that is located beneath the stressor layer portion is then spalled from the original base substrate. The spalling includes displacing the spalling inhibitor from atop the stressor layer portion. After spalling, the stressor layer portion is removed from atop a spalled portion of the base substrate.

Abstract: A method of manufacturing a semiconductor device comprises: forming a protective film so as to cover at least a side edge of a substrate; forming a trench, which is annular in shape when viewed oppositely to a first principal surface of the substrate, on the first principal surface by etching using a photoresist pattern; and forming an insulating film so as to fill the trench, to form an insulating ring.

Abstract: A process for forming a layer (26) of semiconductor material from a substrate (20), or donor substrate, made of the same semiconductor material is described, comprising: formation in said donor substrate of a high lithium concentration zone (22), with a concentration between 5×1018 atoms/cm3 and 5×1020 atoms/cm3, then a hydrogen implantation (24) in the donor substrate, in, or in the vicinity of, the high lithium concentration zone, application of a stiffener (19) with the donor substrate, application of a thermal budget to result in the detachment of the layer (34) defined by the implantation.

Abstract: Method for manufacturing a microelectronic device from a first substrate (10), including the production of at least one electronic component in the semi-conductor substrate after transferring the first substrate (10) onto a second substrate (20), characterized in that it comprises: a first phase carried out prior to the transfer, and including forming at least one pattern made of a sacrificial material in a layer of the first substrate (10), a second phase carried out after the transfer and including the substitution of the electronic component for the pattern.

Abstract: A method for fabrication of a multijunction photovoltaic (PV) cell includes providing a stack comprising a plurality of junctions on a substrate, each of the plurality of junctions having a respective bandgap, wherein the plurality of junctions are ordered from the junction having the smallest bandgap being located on the substrate to the junction having the largest bandgap being located on top of the stack; forming a top metal layer, the top metal layer having a tensile stress, on top of the junction having the largest bandgap; adhering a top flexible substrate to the metal layer; and spalling a semiconductor layer from the substrate at a fracture in the substrate, wherein the fracture is formed in response to the tensile stress in the top metal layer.

Abstract: In a manufacturing method for manufacturing a silicon on insulator (SOI) wafer, an ion injection layer is formed within the wafer, by injecting a hydrogen ion or a rare gas ion from a surface of the single crystal silicon wafer, the ion injection surface of the single crystal silicon wafer and/or a surface of the transparent insulation substrate is processed using plasma and/or ozone, the ion injection surface of the single crystal silicon wafer is bonded to the surface of the transparent insulation substrate, by bringing them into close contact with each other at room temperature, with the processed surface(s) as bonding surface(s), and an SOI layer is formed on the transparent insulation substrate, by mechanically peeling the single crystal silicon wafer by giving an impact to the ion injection layer.

Abstract: A method for slicing a crystalline material ingot includes providing a crystalline material boule characterized by a cropped structure including a first end-face, a second end-face, and a length along an axis in a first crystallographic direction extending from the first end-face to the second end-face. The method also includes cutting the crystalline material boule substantially through a first crystallographic plane in parallel to the axis to separate the crystalline material boule into a first portion with a first surface and a second portion with a second surface. The first surface and the second surface are planar surfaces substantially along the first crystallographic plane. The method further includes exposing either the first surface of the first portion or the second surface of the second portion, and performing a layer transfer process to form a crystalline material sheet from either the first surface of the first portion or from the second surface of the second portion.

Abstract: A method of manufacturing a thin film electronic device includes applying a plastic coating to a rigid carrier substrate using a wet casting process, the plastic coating forming a plastic substrate and include a transparent plastic material doped with a UV absorbing additive. Thin film electronic elements are formed over the plastic substrate, and the rigid carrier substrate is released from the plastic substrate. This method forms transparent substrate materials suitable for a laser release process, through doping of the plastic material of the substrate with a UV absorber. This UV absorber absorbs in the wavelength of the lift-off laser (for example 308-351 nm, or 355 nm) with a very high absorption.

Abstract: Provided is an organic EL apparatus including: an organic EL panel including organic EL devices; a heat releasing member; and a pair of film sheets of which at least one is transparent, wherein the organic EL panel and the heat releasing member overlap and are interposed and encapsulated by the pair of film sheets in a state where a portion of the heat releasing member is exposed outside the pair of film sheets.

Abstract: The present invention is a method for manufacturing a bonded wafer including at least the steps of: forming an ion-implanted layer inside a bond wafer; bringing the ion-implanted surface of the bond wafer into close contact with a surface of a base wafer directly or through a silicon oxide film; and performing heat treatment for delaminating the bond wafer at the ion-implanted layer, wherein the heat treatment step for delaminating includes performing a pre-annealing at a temperature of less than 500° C. and thereafter performing a delamination heat treatment at a temperature of 500° C. or more, and the pre-annealing is performed at least by a heat treatment at a first temperature and a subsequent heat treatment at a second temperature higher than the first temperature.

Abstract: A chip-to-wafer bonding method and a three-dimensional integrated semiconductor device are provided. The method comprises providing a chip and a wafer having a bonding region of the same size and shape as the chip; preparing hydrophilic areas and hydrophobic areas on the chip; preparing in the bonding region hydrophilic areas and hydrophobic areas respectively corresponding to the hydrophilic and hydrophobic areas on the chip; adding a liquid drop onto the hydrophilic areas in the bonding region; and pre-aligning and placing the chip on the bonding region of the wafer, such that the hydrophilic areas on the chip each contacts the corresponding hydrophilic area in the bonding region via the liquid. The sum of perimeters of the hydrophilic areas on the chip is larger than a perimeter of the chip. The sum of perimeters of the hydrophilic areas in the bonding region is larger than a perimeter of the bonding region.

Abstract: A method of forming a strained silicon-on-insulator includes forming a first wafer having a compressively strained active semiconductor layer, forming a second wafer having an insulation layer formed above a bulk semiconductor layer, and bonding the compressively strained active semiconductor layer of the first wafer to the insulation layer of the second wafer.

Abstract: A method for manufacturing a bonded wafer includes: an ion implantation step of using a batch type ion implanter; a bonding step of bonding an ion implanted surface of a bond wafer to a surface of a base wafer directly or through an insulator film; and a delamination step of delaminating the bond wafer at an ion implanted layer, thereby manufacturing a bonded wafer having a thin film on the base wafer, wherein the ion implantation into the bond wafer carried out at the ion implantation step is divided into a plurality of processes, the bond wafer is rotated on its own axis a predetermined rotation angle after each ion implantation, and the next ion implantation is carried out at an arrangement position obtained by the rotation.