Abstract: A process for heat treating a silicon wafer to dissolve B-type agglomerated interstitial defects present therein. The process includes heating the silicon wafer at a temperature for a time sufficient to dissolve B-defects, the wafer being heated to said temperature at a rate sufficient to prevent B-defects from becoming stabilized such that these defects are rendered incapable of being dissolved.

Abstract: A method for evaluating the concentration of impurities in gases used in depositing an epitaxial layer on a semiconductor substrate. The method includes processing a semiconductor substrate of known impurity levels in an epitaxial reactor, and measuring the impurity levels after epitaxial processing by drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of the substrate to getter impurities from the substrate into the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were transferred to the substrate from the epitaxial susceptor.

Abstract: A method for evaluating the concentration of impurities in as-grown monocrystalline semiconductor ingots is provided. The method includes growing a monocrystalline semiconductor ingot, and measuring the bulk impurity levels of the ingot by drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of a sample of the monocrystalline semiconductor ingot to getter impurities from the sample into the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were grown into the monocrystalline semiconductor ingot.

Abstract: A semiconductor device comprising organic semiconductor material (14) has one or more barrier layers (16) disposed at least partially thereabout to protect the organic semiconductor material (14) from environment-driven changes that typically lead to inoperability of a corresponding device. If desired, the barrier layer can be comprised of partially permeable material that allows some substances therethrough to thereby effect disabling of the encapsulated organic semiconductor device after a substantially predetermined period of time. Getterers (141) may also be used to protect, at least for a period of time, such organic semiconductor material.

Abstract: Catalytic elements such as Ni are intentionally combined with defects that remain inside of a semiconductor substrate or thin film so that the energy state of the defects comes to a stable state. In this state, a heat treatment is conducted in an atmosphere containing halogen element or XV element, and gettering is conducted in such a manner that the catalytic element is taken in an oxide film. The bonds which are divided by separating the catalytic element are recombined through a heat treatment, thereby being capable of improving crystalline property of the semiconductor substrate or thin film remarkably.

Abstract: A method for evaluating the concentration of impurities in a semiconductor substrate. The method includes drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of the substrate to getter impurities from the substrate to the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were in the substrate prior to the drawing together.

Abstract: A method and apparatus are provided for eliminating contaminants including metallic and/or hydrocarbon-containing contaminants on a surface of a semiconductor substrate by heating a semiconductor substrate which may have contaminates on the surface thereof to an elevated temperature within an integrated closed system while simultaneously purging the integrated closed system with a chlorine-containing gas. At the elevated temperatures the chlorine dissociates from the chlorine-containing gas and reacts with the contaminates on the substrate surface to form volatile chloride byproducts with such contaminants which are removed from the integrated closed system while the substrate is continuously heated and purged with the chlorine-containing gas. Subsequently, the substrate is moved to a cooling chamber within the integrated closed system and cooled to provide a semiconductor substrate having a clean surface.

Abstract: An apparatus and method for forming an epitaxial layer on and a denuded zone in a semiconductor wafer. A single chamber is used to form both the epitaxial layer and the denuded zone. The denuded zone is formed by heating the wafer in the chamber and then rapidly cooling the wafer while it is supported on an annular support whereby only a peripheral edge portion of the wafer is in contact with the support.

Abstract: The invention includes an array of devices and a charge pump supported by a semiconductive material substrate. A damage region is under the array, and extends less than or equal to 50% of a distance between the array and the charge pump. The invention also includes a method in which a mask is formed over a monocrystalline silicon substrate. A neutral-conductivity-type dopant is implanted through an opening in the mask and into a section of the substrate to produce a damage region. A first boundary extends around the damage region. The masking layer is removed, and epitaxial silicon is formed over the substrate. An array of devices is formed to be supported by the epitaxial silicon. The array is bounded by a second boundary. The first boundary extends less than or equal to 100 microns beyond the second boundary.

Abstract: A method is designed to manufacture a silicon epitaxial wafer exhibiting sufficient gettering capability from the initial stage of the device process. Specifically, the method is to manufacture the silicon wafer with a nitrogen concentration of at least 1×1012 atoms/cm3 and an oxygen concentration of 10˜18×1017 atoms/cm3 by annealing at a temperature of 800˜1,100° C. after epitaxial growth treatment, satisfying the following equation (a), t≧33−((T−800)/100)  (a) wherein T(° C.) is temperature, and t(hr) is time, thereby manufacturing a high yield semiconductor device.

Abstract: The invention describes a method for gettering silicon on insulator wafers without forming regions of heavy doping. Silicon germanium layers (201, 304) are formed beneath silicon layers (200, 305) such that dislocations will form in the silicon germanium layers. These dislocations will serve to getter impurities.

Abstract: An electronic device that is sealed under vacuum includes a substrate, a transistor formed on the substrate, and a dielectric layer covering at least a portion of the transistor. The electronic device further includes a layer of non-evaporable getter material disposed on a portion of the dielectric layer; and a vacuum device disposed on a portion of the substrate. Electrical power pulses activate the non-evaporable getter material.

Abstract: A getter device is shaped like a substrate used in a deposition process. Embodiments of the device include a powdered getter material coated onto one or both sides of a support with a narrow rim portion left uncoated so that the device can be manipulated by automatic handling equipment. A method for using the getter device includes providing a vacuum chamber and automatic handling equipment, loading the device into the chamber, reducing the chamber pressure to a desired value by using the getter device in conjunction with an external pump, removing the getter device and replacing it with a substrate, and depositing a thin film on the substrate. The getter device can be in an activated state when loaded into the chamber, or it can be activated after being loaded by employing heating equipment ordinarily used to heat substrates placed in the chamber. The getter material of the device may also be activated in a separate activation chamber before the getter device is loaded into the vacuum chamber.

Abstract: A process for heat-treating a single crystal silicon wafer to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step. The wafer has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the wafer is subjected to a heat-treatment to form crystal lattice vacancies in the wafer. During the heat-treatment, the front and back surfaces of the wafer are each exposed to either a nitriding gas or a non-nitriding gas. The front surface of the heat-treated wafer is then oxidized by heating in the presence of an oxygen-containing atmosphere in order to further effect the vacancy concentration profile within the wafer.

Abstract: A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep, trench in bulk Si while forming merged logic regions on SOI.

Abstract: A process of removing metallic impurities from a polished boron-doped silicon wafer comprising forming an oxide layer on the polished wafer that is thicker than a typical native oxide layer so that the oxide layer has a greater gettering capacity than a native oxide layer gettering capacity and then annealing the wafer at a temperature of at least about 75° C. for at least about 30 seconds to decrease the concentration of the metallic impurity in the interior of the silicon wafer and increase the concentration of the metallic impurity on the polished surface of the silicon wafer and in the oxide layer. Preferably, the annealed silicon wafer is cleaned to remove the oxide layer and to remove the metallic impurity from the polished surface of the silicon wafer. By repeatedly creating an oxide layer and annealing the wafer, the wafer can be made substantially free of metallic impurities.

Abstract: According to the present invention, there are provided a method for heat treatment of silicon wafers wherein a silicon wafer is subjected to a heat treatment at a temperature of from 1000° C. to the melting point of silicon in an inert gas atmosphere, and temperature decreasing in the heat treatment is performed in an atmosphere containing 1-60% by volume of hydrogen, a method for heat treatment of silicon wafers under a reducing atmosphere containing hydrogen by using a rapid heating and rapid cooling apparatus, wherein temperature decreasing rate from the maximum temperature in the heat treatment to 700° C. is controlled to be 20° C./sec or less, and a silicon wafer which has a crystal defect density of 1.0×104 defects/cm3 or more in a wafer bulk portion, a crystal defect density of 1.0×104 defects/cm3 or less in a wafer surface layer of a depth of 0.5 &mgr;m from the surface, a crystal defect density of 0.15 defects/cm2 or less on a wafer surface and surface roughness of 1.

Abstract: A novel method of generating intrinsic gettering sites in epitaxial wafers employs co-implanting silicon and oxygen into a substrate of the wafer, annealing the substrate at a low temperature, and then depositing the epitaxial layer on a surface of the substrate. The epitaxial deposition acts as an in-situ anneal to form dislocation loops that act as gettering sites. Oxygen precipitate clusters form during the method, which clusters act to anchor the dislocation loops and prevent them from gliding to the wafer surface over time.

Abstract: There is prepared a wafer (10) having a gettering capability such as PBS wafer having deposition of polysilicon on its back surface thereof, IG wafer containing oxygen precipitates. An element separation silicon oxide film (2) is formed on the wafer (10), and a first silicon oxide film (3) is formed on the wafer (10). Then the wafer (10) is gradually cooled to a low temperature, or the wafer (10) is cooled to a low temperature and then kept at the low temperature for a fixed time. Thereafter, the first silicon oxide film (3) is removeed from the wafer (10) and then the wafer (30) is cleaned. Thereafter, a gate silicon oxide film (4) and a gate electrode (5) are formed. Subsequently, ion implantation to form a source (6) and a drain (7) and a heat treatment to activate implanted impurities are performed to form a basic MOS transistor.

Abstract: By removing halogen atoms existing on the surface of the silicon layer and in the subsurface thereof so that the concentration of halogen atoms becomes 100 ppm or lower and forming an electrode on the resulting silicon layer, the electrode which has a low resistance can be produced, and a highly reliable semiconductor device can be produces as well.

Abstract: There is provided a semiconductor manufacturing method capable of sufficiently reducing catalytic element in a crystalline silicon film and also increasing the area of the crystalline silicon film to be left on the substrate. A catalytic element for accelerating the crystallization is introduced into an amorphous silicon film on a substrate, and a first heat treatment is performed to crystallize the amorphous silicon film into a crystalline silicon film. A mask layer is provided on the surface of the crystalline silicon film, the mask layer having an opening passing thicknesswise through the mask layer. Further thereon, a sacrifice film is formed so as to continuously cover the surface of the mask layer and an opening-correspondent portion of the crystalline silicon film. A getter element for gettering the catalytic element is introduced into the sacrifice film and the opening-correspondent portion of the crystalline silicon film.

Abstract: A method of manufacturing a semiconductor memory device comprising: a step of forming a storage node in which a conductive layer 7 to be the storage node is formed in the vicinity of single crystalline silicon 3 formed on an insulator 2, a gettering step for conducting heat treatment to the single crystalline silicon 3 after the step of forming the storage node and gettering contaminants contained in the single crystalline silicon 3 by the conductive layer 7 connected to the single crystalline silicon, and a step of forming a gate oxide film 8a on the single crystalline silicon 3 after the step of gettering is provided to thereby obtain a sufficient gettering effect even though the width of an element and/or the thickness of the element is reduced in accordance with microminiaturization of the element.

Abstract: The object of the present invention is to provide a semiconductor wafer in which a diffusion of Cu generated by a thermal treatment such as a Cu wiring formation step into silicon is prevented, and variations of transistor characteristics are lessened. The object of the present invention is to provide a method of manufacturing the same and a semiconductor device formed from the same. In the present invention, a protection insulating film for preventing Cu from diffusing into the inside of the wafer is formed on a peripheral portion of a principal plane, a external side plane and a rear plane of the wafer. With this protection insulating film, the diffusion of Cu that is a wiring material into a chip formation region of the wafer is prevented, so that the variations of the transistor characteristic.

Abstract: The invention describes a method for gettering silicon on insulator wafers without forming regions of heavy doping. Silicon germanium layers (201, 304) are formed beneath silicon layers (200, 305) such that dislocations will form in the silicon germanium layers. These dislocations will serve to getter impurities.

Abstract: Disclosed is an improved CMOS fabrication method that allows an implanted well in a bare silicon wafer to be simultaneously, driven annealed and denuded in a single process step. More specifically, a single step drive-anneal-denude (DAD) process is accomplished using a non-inert ambient environment. The DAD process is accomplished in a combination argon/hydrogen ambient environment. This process causes the silicon wafer to roughen slightly and is followed by an oxidation step, that optionally takes place in a combination argon/oxygen ambient environment to smooth out the silicon surface. The oxidation step may also optionally act as a pad-oxide or screening oxide for subsequent fabrication.

Abstract: A method for gettering metallic impurities located in a semiconductor substrate. In an exemplary embodiment of the invention, the method includes forming an insulating layer upon a donor wafer. A cleaving layer is ionically implanted, through the insulating layer, into the donor wafer. The cleaving layer is formed at a first depth with respect to the insulating layer. A gettering layer is also ionically implanted, through the insulating layer, into the donor wafer. The gettering layer is formed at a second depth with respect to said insulating layer, with second depth being less than the first depth. The donor wafer is then bonded, at the insulating layer, to a substrate wafer. The donor wafer is then fractured along the cleaving layer, and a section of the donor wafer is removed along the cleaving layer. Thereby, an active semiconductor device area is formed atop the gettering layer.

Abstract: A method of removing contaminants from a silicon wafer after chemical-mechanical polishing (CMP). After a copper chemical-mechanical polishing and a subsequent barrier chemical-mechanical polishing operation, an aqueous solution of ozone in de-ionized water is applied to clean the silicon wafer so that contaminants on the wafer are removed. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after copper and barrier CMP and then the wafer is cleaned using a chemical solution or de-ionized water. Alternatively, an ozone/de-ionized water buffer-polishing process is conducted after both copper-CMP and barrier-CMP and then the wafer is cleaned using a chemical solution or de-ionized water.

Abstract: The present invention relates to a simplified method of fabricating a thin film transistor (TFT), including the steps of preparing a first conductive type TFT including a first semiconductor layer and a first gate electrode and a second conductive type TFT including a second semiconductor layer and a second gate electrode on a substrate; doping the first and second semiconductor layers with a first conductive type impurity using the first and second gate electrodes as a mask; forming a doping mask covering the first conductive type TFT; counter-doping the second semiconductor layer with a second conductive type impurity using the doping mask and the second gate electrode as masks; and forming a CMOS TFT by electrically connecting the first conductive type TFT to the second conductive type TFT.

Abstract: A single crystal silicon is produced using a Czocharalski (CZ) method. Silicon nitride powder is put in the bottom of a quartz crucible to provide a nitrogen concentration in the single crystal silicon of not less than about 1×1013 atoms/cm3. A poly-silicon raw material is then charged in the crucible. A pulling rate for the single crystal silicon is low so that an oxidation induced stacking faults ring exists or disappears at the center. Maintaining the nitrogen concentration of the single crystal silicon to not less than 1×1013 atoms/cm3 decrease the vacancy cluster and existinguish the dislocation cluster. Wafers prepared from the single crystal silicon have very high quality with minimal defects.

Abstract: An electronic device that is sealed under vacuum includes a substrate, a transistor formed on the substrate, and a dielectric layer covering at least a portion of the transistor. The electronic device further includes a layer of non-evaporable getter material disposed on a portion of the dielectric layer; and a vacuum device disposed on a portion of the substrate. Electrical power pulses activate the non-evaporable getter material.

Abstract: The present invention relates to the formation of multiple gettering structures within a semiconductive substrate by ion implantation through recesses in the semiconductive substrate. A preferred embodiment of the present invention includes forming the recesses by using a reactive anisotropic etching medium, followed by implanting a gettering material. The gettering material is implanted by changing the gettering material for the reactive anisotropic etching medium. An advantage of the method of the present invention is that gettering structures are formed without the cost of an extra masking procedure and without the expense of MeV implantation equipment and procedures. As a result, metallic contaminants will not move as freely through the semiconductive substrate in the region of an active area proximal to the gettering structures.

Abstract: To provide a method of removing a catalyst element from a crystalline silicon film obtained by solid phase growth using the catalyst element promoting crystallization, phosphorus is implanted selectively to the crystalline silicon film having the catalyst element whereby a portion of the silicon film implanted with phosphorus is made amorphous, and when a thermal annealing treatment is performed and the silicon film is heated, the catalyst element is moved to an amorphous portion implanted with phosphorus having large gettering capacity by which the concentration of the catalyst element in the silicon film is lowered and a semiconductor device is fabricated by using the silicon film.

Abstract: This invention relates to a method for manufacturing electronic devices integrated monolithically in a semiconductor substrate delimited by two opposed front and back surfaces of a semiconductor material wafer. The method comprises at least a step of implanting ions of a noble gas, followed by a thermal treatment directed to form gettering microvoids in the semiconductor by evaporation of the gas. The ion implanting step is carried out through the back surface of the semiconductor wafer prior to starting the manufacturing process for the electronic devices, and also can be before the step of cleaning the front surface of the wafer.

Abstract: A surface of a substrate is oxidized at a temperature equal to or higher than 1050° C., or at a oxidation speed equal to or higher than 7.5 nm/min to form an oxide film with a thickness equal to or more than 1500 nm. when the oxide film is removed, a density of pits existent at the surface of a substrate is equal to or less than that prior to the oxidation treatment and a depth of a pit existent there is equal to or less than 50 nm. An element isolation withstand voltage can be prevented from lowering and a fabrication yield of a miniaturized, highly integrated semiconductor device can be improved.

Abstract: A combined preanneal/oxidation step using a rapid thermal process (RTP) for treatment of a silicon wafer to form a thermal oxide of a given thickness while simultaneously adjusting the denuded zone depth and bulk micro defect density (BMD) comprising: exposing the wafer to a controlled temperature and a controlled preannealing time in an oxidation ambient at ambient pressure to obtain a target thermal oxide thickness that is preselected to correspond to a preselected denuded zone depth.

Abstract: In a method of producing a semiconductor device, an a-Si film is crystallized using nickel to form a CGS film. Then, an a-Si film containing phosphorus is directly formed on the whole surface of the CGS film, and then the CGS film and the a-Si film are subjected to heat treatment to thereby getter the nickel from the CGS film the a-Si film. The a-Si film containing nickel and phosphorus is removed. Then, using the thus obtained CGS film for an active region, a thin-film transistor is formed.

Abstract: A preprocessing method of a metal film formation process before formation of a BLM film on a resist film of a substrate to be processed, wherein the resist film of substrate to be processed is irradiated with plasma, utilizing a plasma processing apparatus providing independent plasma generating power source and substrate bias power source to form an overhand area at the end face of a connecting hole and change the property of the surface area.

Abstract: A method for evaluating the concentration of impurities in gases and equipment used in heat treatment of a semiconductor substrate is provided. The method includes processing a semiconductor substrate of known impurity levels in a heat treatment furnace, and measuring the impurity levels after the heat treatment processing by drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of the substrate to getter impurities from the substrate into the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were transferred to the substrate from the heat treatment process.

Abstract: According to the present invention, an impurity region, to which a rare gas element (also called a rare gas) and one kind or a plurality of kinds of elements selected from the group consisting of H, H2, O, O2, and P are added, are formed in a semiconductor film having a crystalline structure, using a mask, and gettering for segregating a metal element contained in the semiconductor film to the impurity region by heat treatment. Thereafter, pattering is conducted using the mask, whereby a semiconductor layer made of the semiconductor film having a crystalline structure is formed.

Abstract: A high-resistance substrate with good RF characteristics, which has an interstitial oxygen concentration ([Oi]) of 8E17 cm−3 or less, an oxygen precipitate density ([BMD]) of 1E8 cm−3 or more, and a substrate resistivity of 500 &OHgr;·cm or more is used. A heat-treating step of the device process is performed for 25 hrs or less as a value calculated assuming that the temperature is 1,000° C. This suppresses a decrease in the resistance of the substrate, prevents crystal defects such as slip, and improves the yield.

Abstract: The invention concerns a method for treating, a substrate comprising a semi-conducting layer (4) on at least one of its surfaces. Said method comprises a step for annealing the substrate and a step for forming, an oxide layer (6) at the semi-conducting layer (4) surface, carried out before the end of the annealing step, protecting the remainder of the semi-conducting layer (4).

Abstract: A method of manufacturing a semiconductor device including the steps of (a) forming an element isolation insulating film in an element isolation region of a SOI substrate of a stacked structure in which a semiconductor substrate, insulating layer, and semiconductor layer are stacked in this order, and (b) forming, in an element formation region of the SOI substrate, a transistor having a channel formation region selectively disposed in a main surface of the semiconductor layer, a gate structure on the channel formation region, and source/drain regions disposed is the main surface of the semiconductor layer and the adjacent channel formation region. The method also includes the step of (c) selectively growing, after said steps (a) and (b), a polycrystal semiconductor layer on the source/drain regions in a self-aligned manner, which is prescribed by the element isolation insulating film and the gate structure.

Abstract: The invention includes semiconductor processing methods, including trench isolation. In one implementation, an oxide layer is deposited over a substrate. The deposited oxide layer is exposed to a chlorine containing gas effective to getter metals outwardly therefrom. In one implementation, a dielectric layer, for example silicon dioxide, is plasma enhanced chemical vapor deposited over a substrate within a chamber comprising an internal metal surface under conditions effective to incorporate metal from the chamber surface within the dielectric layer. The dielectric layer is then exposed to a chlorine containing gas effective to getter at least some of said metal outwardly therefrom. In one implementation, a trench isolation method comprises forming a series of isolation trenches into a semiconductive substrate Silicon dioxide is chemical vapor deposited to within the trenches, with the silicon dioxide comprising metal impurity therein.

Abstract: A method for non-destructively evaluating the concentration of impurities in an epitaxial susceptor used in the processing of a semiconductor substrate. The method includes processing a semiconductor substrate of known impurity levels on the epitaxial susceptor, and measuring the impurity levels after epitaxial processing by drawing together at least a portion of the impurities and measuring the concentration of impurities that were drawn together. In one embodiment of the invention, a gettering layer is formed adjacent one or more surfaces of the substrate to getter impurities from the substrate into the gettering layer. The impurity concentration of the gettering layer is then measured and the results are used to determine at least a range of impurity concentrations that were transferred to the substrate from the epitaxial susceptor.

Abstract: A semiconductor wafer manufacturing process is disclosed wherein extremely flat, double side polished semiconductor wafers having enhanced gettering characteristics on the back surface are produced. The process includes creating an enhanced gettering layer on the back surface of a double side polished semiconductor wafer. A protective layer is subsequently grown on the enhanced gettering layer and the wafer is subsequently subjected to a second double side polishing operation. Finally, the protective layer is removed and the front surface final polished to produce an extremely flat semiconductor wafer having enhanced gettering characteristics on the back surface.

Abstract: Decreasing foreign materials adhering to a semiconductor substrate to improve a yield and decreasing handling errors for the semiconductor substrate to improve an operating ratio of the semiconductor manufacturing apparatus.

Abstract: In a method of manufacturing a semiconductor device, a first polysilicon film is formed on a surface of a semiconductor substrate for a semiconductor element to be formed thereon. Ion implantation is performed in such a manner that impurity ions are implanted into the semiconductor substrate surface through the first polysilicon film. The semiconductor substrate is heated to a first temperature after the step of performing ion implantation. Then, the semiconductor substrate is gradually cooled with a predetermined cooling rate at least from a second temperature to a third temperature while the semiconductor substrate is cooled from the first temperature. The second and third temperatures are lower than the first temperature. Subsequently, the polysilicon film is removed after the gradually cooling step.

Abstract: Disclosed is an improved CMOS fabrication method that allows an implanted well in a bare silicon wafer to be simultaneously, driven annealed and denuded in a single process step. More specifically, a single step drive-anneal-denude (DAD) process is accomplished using a non-inert ambient environment. The DAD process is accomplished in a combination argon/hydrogen ambient environment. This process causes the silicon wafer to roughen slightly and is followed by an oxidation step, that optionally takes place in a combination argon/oxygen ambient environment to smooth out the silicon surface. The oxidation step may also optionally act as a pad-oxide or screening oxide for subsequent fabrication.

Abstract: A method of treating a semiconductor wafer thermally and a semiconductor wafer fabricated thereby and, more particularly, a method of producing a wafer ideal for fabricating semiconductor devices thereon through thermal treatment. The method of removing defects contained in single crystalline semiconductor by treating the wafer thermally includes the steps of carrying out a first heat treatment on the wafer at a temperature equal to or higher than 1200° C., and carrying out a second heat treatment on the wafer at a temperature equal to or lower than 800° C.

Abstract: A method for making a metallic pattern that includes redundant photolithography to significantly reduce the occurrence of defects in the metal layer that defines the desired metallic pattern. The presence of contaminants in the photoresist layer during exposure and developing away of portions of a photoresist layer can cause defects in the metal layer that defines the desired metallic pattern. Contaminants in the photoresist layer prevent portions of the photoresist layer from being exposed and developed away, so that portions of the photoresist layer that should be developed away remain in place, thereby causing the development of defects in the metal layer that defines the desired metallic pattern. These contaminants move to different positions during the developing away of the photoresist.