Abstract: Methods for forming a microcrystalline silicon layer in a thin film transistor structure are provided. In one embodiment, a method for forming a microcrystalline silicon layer includes providing a substrate in a processing chamber, supplying a first gas mixture having a hydrogen containing gas to a silicon containing gas flow rate ratio greater than about 200:1 into the processing chamber, maintaining a first process pressure greater than about 6 Torr in the processing chamber to deposit a first microcrystalline silicon containing layer in presence of a plasma formed from the first gas mixture, supplying a second gas mixture into the processing chamber, and maintaining a second process pressure less than about 5 Torr in the processing chamber to deposit a second microcrystalline silicon containing layer in presence of a plasma formed from the second gas mixture.

Abstract: Methods for forming a microcrystalline silicon layer in a thin film transistor structure are provided. In one embodiment, a method for forming a microcrystalline silicon layer includes providing a substrate in a processing chamber, supplying a gas mixture having a hydrogen-based gas, a silicon-based gas and an argon gas into the processing chamber, the gas mixture having a volumetric flow ratio of the hydrogen-based gas to the silicon-based gas greater than about 100:1, wherein a volumetric flow ratio of the argon gas to the total combined flow of hydrogen-based gas and the silicon-based gas is between about 5 percent and about 40 percent, and maintaining a process pressure of the gas mixture within the processing chamber at greater than about 3 Torr while depositing a microcrystalline silicon layer on the substrate.

Abstract: A reliability of a semiconductor device having a phase-change memory is improved. A phase-change memory device has a bottom-electrode plug buried in an interlayer insulator that is provided on a main surface of a semiconductor substrate, an electric conductive material layer provided on an upper portion of the bottom-electrode plug and on the interlayer insulator, a phase-change material layer provided on the electric conductive material layer, and an upper-electrode plug provided on the phase-change material layer. The bottom-electrode plug and the upper-electrode plug which configure the phase-change memory device are provided at respective different positions in a plane of the semiconductor substrate.

Abstract: In a transistor adapted to suppress characteristic degradation resulting from fluorine contained in a deposited film, the concentration of fluorine contained in a gate insulating film (3) is reduced to 1.0×1020 atoms/cm3 or less. As a result, the transistor can provide excellent reliability even when it is continuously driven for a long period of time at a relatively high temperature.

Abstract: A method for producing a crystalline film by melting and resolidifying a film, characterized in preparing a film having a specific region and obtained either by (A) a step of forming a film in which a “specific region” and an “region continuous to a periphery of the specific region and different in thickness from the specific region” co-exist, or by (B) a step of irradiating a film with an electromagnetic wave or particles having a mass in mutually different conditions between a specific region and a peripheral region thereof, and melting and resolidifying at least a part of the film. As the spatial position of the specific region can be exactly and easily controlled, it is possible to obtain a crystalline film in which a crystal grain is formed in a desired position.

Abstract: A method for depositing a germanium containing film on a substrate is disclosed. A reactor, and at least one substrate disposed in the reactor, are provided. A germanium containing precursor is provided and introduced into the reactor, which is maintained at a temperature of at least 100° C. Germanium is deposited onto the substrate through a deposition process to form a thin film on the substrate.

Abstract: An object is to provide a semiconductor device including a microcrystalline semiconductor film with favorable quality and a method for manufacturing the semiconductor device. In a thin film transistor formed using a microcrystalline semiconductor film, yttria-stabilized zirconia having a fluorite structure is formed in the uppermost layer of a gate insulating film in order to improve quality of a microcrystalline semiconductor film to be formed in the initial stage of deposition. The microcrystalline semiconductor film is deposited on the yttria-stabilized zirconia, so that the microcrystalline semiconductor film around an interface with a base particularly has favorable crystallinity while by crystallinity of the base.

Abstract: A method of manufacturing a semiconductor device includes forming transistors including gate electrodes and source/drain regions over a substrate. A protective layer is placed over the source/drain regions and the gate electrodes. A portion of the protective layer is removed to expose a portion of the gate electrodes. The exposed portions of the gate electrodes are amorphized, and remaining portions of the protective layer located over the source/drain regions are removed. A stress memorization layer is formed over the gate electrodes, and the substrate is annealed in the presence of the stress memorization layer to at least reduce an amorphous content of the gate electrodes. The stress memorization layer is removed subsequent to the annealing.

Abstract: Trisilane is used in chemical vapor deposition methods to deposit silicon-containing films over mixed substrates. Such methods are useful in semiconductor manufacturing to provide a variety of advantages, including uniform deposition over heterogeneous surfaces, high deposition rates, and higher manufacturing productivity. An example is in forming the base region of a heterojunction bipolar transistor, including simultaneous deposition over both single crystal semiconductor surfaces and amorphous insulating regions.

Abstract: An apparatus and a method for steering optical frequency beams using nanowire. A method includes providing one or more nanowire waveguide arrays, generating an optical frequency beam, wherein the optical frequency beam is incident on the one or more nanowire waveguide arrays, controlling the one or more nanowire waveguide arrays to produce a phase delay in the optical frequency beam as it traverses the nanowire waveguide array, wherein the phase delay causes the optical frequency beam to deflect upon exiting the one or more nanowire waveguide arrays, and steering the optical frequency beam exiting the one or more nanowire waveguide arrays by increasing or decreasing the phase delay, wherein the angle of deflection of the exiting optical frequency beam is determined by the amount of phase delay.

Abstract: In methods of forming a phase-change material layer pattern, an insulation layer having a recessed portion may be formed on a substrate, and a phase-change material layer may be formed on the insulation layer to fill the recessed portion. A first polishing process may be performed on the phase-change material layer using a first slurry composition to partially remove the phase-change material layer, the first slurry composition having a first polishing selectivity between the insulation layer and the phase-change material layer. A second polishing process may be performed on the phase-change material layer using a second slurry composition to form a phase-change material layer pattern in the recessed portion, the second slurry composition having a second polishing selectivity substantially lower than the first polishing selectivity.

Abstract: Methods of creating isolated electrodes and integrating a nanowire therebetween each employ lateral epitaxial overgrowth of a semiconductor material on a semiconductor layer to form isolated electrodes having the same crystal orientation. The methods include selective epitaxial growth of a semiconductor feature through a window in an insulating film on the semiconductor layer. A vertical stem is in contact with the semiconductor layer through the window and a ledge is a lateral epitaxial overgrowth of the vertical stem on the insulating film. The methods further include creating a pair of isolated electrodes from the semiconductor feature and the semiconductor layer. A nanowire-based device includes the pair of isolated electrodes and a nanowire bridging between respective surfaces of the isolated electrodes of the pair.

Abstract: A method for forming a microcrystalline semiconductor film over a base formed of a different material, which has high crystallinity in the entire film and at an interface with the base, is proposed. Further, a method for manufacturing a thin film transistor including a microcrystalline semiconductor film with high crystallinity is proposed. Furthermore, a method for manufacturing a photoelectric conversion device including a microcrystalline semiconductor film with high crystallinity is proposed. By forming crystal nuclei with high density and high crystallinity over a base film and then growing crystals in a semiconductor from the crystal nuclei, a microcrystalline semiconductor film which has high crystallinity at an interface with the base film, which has high crystallinity in crystal grains, and which has high adhesion between the adjacent crystal grains is formed.

Abstract: An integrated circuit includes a first electrode, resistivity changing material coupled to the first electrode, and a second electrode. The integrated circuit includes a dielectric material layer between the resistivity changing material and the second electrode. The dielectric material layer includes nanocrystals.

Abstract: A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the method comprises forming a gate electrode overlying and defining a channel region in a monocrystalline semiconductor substrate. A trench having a side surface facing the channel region is etched into the monocrystalline semiconductor substrate adjacent the channel region. The trench is filled with a second monocrystalline semiconductor material having a first concentration of a substitutional atom and with a third monocrystalline semiconductor material having a second concentration of the substitutional atom. The second monocrystalline semiconductor material is epitaxially grown to have a wall thickness along the side surface sufficient to exert a greater stress on the channel region than the stress that would be exerted by a monocrystalline semiconductor material having the second concentration if the trench was filled by the third monocrystalline material alone.

Abstract: Disclosed is a method of manufacturing microelectronic devices including forming a silicon substrate with first and second wells of different dopant characteristics, forming a first strained silicon-germanium-carbon layer of a first formulation proximate to the first well, and forming a second strained silicon-germanium-carbon layer of a second formulation distinct from the first formulation proximate to the second well. Capping and insulating layers, gate structures, spacers, and sources and drains are then formed, thereby creating a CMOS device with independently strained channels.

Abstract: The present invention provides amorphous silicon thin-film transistors and methods of making such transistors for use with active matrix displays. In particular, one aspect of the present invention provides transistors having a structure based on a channel passivated structure wherein the amorphous silicon layer thickness and the channel length can be optimized. In another aspect of the present invention thin-film transistor structures that include a contact enhancement layer that can provide a low threshold voltage are provided.

Abstract: A multilevel phase change memory may be formed of a chalcogenide material formed between a pair of spaced electrodes. The cross-sectional area of the chalcogenide material may decrease as the material extends from one electrode to another. As a result, the current density decreases from one electrode to the other. This means that a higher current is necessary to convert the material that has the largest cross-sectional area. As a result, different current levels may be utilized to convert different amounts of the chalcogenide material to the amorphous or reset state. A distinguishable resistance may be associated with each of those different amounts of amorphous material, providing the opportunity to engineer a number of different current selectable programmable states.

Abstract: The present invention provides for nanostructures grown on a conducting substrate, and a method of making the same. The nanostructures grown according to the claimed method are suitable for manufacturing electronic devices such as an electron beam writer, and a field emission display.

Abstract: Germanium, tellurium, and/or antimony precursors are usefully employed to form germanium-, tellurium- and/or antimony-containing films, such as films of GeTe, GST, and thermoelectric germanium-containing films. Processes for using these precursors to form amorphous films are also described. Further described is the use of [{nBuC(iPrN)2}2Ge] or Ge butyl amidinate to form GeTe smooth amorphous films for phase change memory applications.

Abstract: A method of forming a localized region of relaxed Si in a layer of strained Si arranged within a strained silicon directly on insulator (SSDOI) semiconductor substrate is provided by the invention. The strained Si layer is formed on a buried oxide (BOX) layer disposed on a Si substrate base. The method includes depositing a nitride hard mask pattern above a region of the strained Si layer in which enhanced electron mobility is desired, leaving an unmasked region within the strained Si layer, and carrying out various other processing steps to modify and relax the unmasked portion of the strained region. The method includes growing an EPI SiGe region upon the unmasked region using pre-amorphization implantation, and forming a buried amorphous SiGe region in a portion of the EPI SiGe region, and an amorphous Si region, below the amorphous SiGe region. Then, using SPE regrowth, modifying the amorphous SiGe and amorphous Si regions to realize an SPE SiGe region and relaxed SPE Si layer.

Abstract: The invention relates to a method of improving a surface of a semiconductor substrate which is at least partially made of silicon. Defects present in or on the semiconductor substrate can be really repaired to provide a semiconductor substrate with a high surface quality. This is achieved by a selective epitaxial deposition in the at least one hole in the surface of the semiconductor substrate. Generally, the deposition step is preceded by an etching step which removes the defects and leaves behind at least one hole that can be plugged or filled with the selective epitaxial deposition of silicon to repair the substrate.

Abstract: Processes for non-selectively forming one or more conformal silicon-containing epitaxial layers on recess corners are disclosed. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the formation of a non-selective epitaxial layer involves exposing a substrate in a process chamber to deposition gases including a silicon source such as silane and a higher order silane, followed by heating the substrate to promote solid phase epitaxial growth.

Abstract: A method is described to form a rewriteable memory cell including a diode and an oxide layer, wherein the resistivity of the oxide layer can be reversibly switched. In preferred embodiments, the oxide layer is a grown oxide. The diode is preferably formed of polysilicon which has been crystallized in contact with a silicide which has a close lattice match to silicon. The silicide provides a crystallization template such that the polysilicon is large-grained with few defects, and thus relatively low-resistivity. In preferred embodiments, a monolithic three dimensional memory array can be formed, in which multiple memory levels of such rewriteable memory cells are monolithically formed vertically stacked above a substrate.

Abstract: A process of forming a compound film includes formulating a nano-powder material with a controlled overall composition and including particles of one solid solution The nano-powder material is deposited on a substrate to form a layer on the substrate, and the layer is reacted in at least one suitable atmosphere to form the compound film. The compound film may be used in fabrication of a radiation detector or solar cell.

Abstract: In one example, a method of epitaxially forming a silicon-containing material on a substrate surface is presented which includes positioning a substrate into a process chamber. The substrate has a monocrystalline surface and at least a second surface, such as an amorphous surface and/or a polycrystalline surface. The substrate is exposed to a deposition gas to deposit an epitaxial layer on the monocrystalline surface and a polycrystalline layer on the second surface. The deposition gas preferably contains a silicon source and at least a second elemental source, such as a germanium source, a carbon source and/or combinations thereof. Thereafter, the method further provides exposing the substrate to an etchant gas to etch the polycrystalline layer and the epitaxial layer in a manner such that the polycrystalline layer is etched at a faster rate than the epitaxial layer.

Abstract: A method of crystallizing an amorphous semiconductor thin film used for a thin film transistor (TFT) is provided. The method includes the steps of: forming first and second crystallization induced metal patterns locally in respective portions of a source region and a drain region of the TFT on an amorphous semiconductor thin film; and crystallizing an amorphous semiconductor via independent two-times heat treatment using the first and second crystallization induced metal patterns. In this case, the independent two-times heat treatment is executed before and after ions of impurities are injected, respectively. In this way, a metal induced lateral crystallization double heat treatment is executed before and after ions of impurities are injected, respectively. As a result, the entire crystallization heat treatment time necessary for crystallizing the amorphous semiconductor thin film can be greatly reduced, and a poly-crystalline TFT having low leakage current can be obtained.

Abstract: A self-converged memory material element is created during the manufacture of a memory cell comprising a base layer, with a bottom electrode, and an upper layer having a third, planarization stop layer over the base layer, a second layer over the third layer, and the first layer over the second layer. A keyhole opening is formed through the upper layer to expose the bottom electrode. The first layer has an overhanging portion extending into the opening. A dielectric material is deposited into the keyhole opening so to create a self-converged void within the keyhole opening. An anisotropic etch forms a sidewall of the dielectric material in the keyhole opening with an electrode hole aligned with the void and exposing the bottom electrode. A memory material is deposited into the electrode hole in contact with the bottom electrode and is planarized down to the third layer to create the memory material element.

Abstract: A method to selectively etch, and hence pattern, a semiconductor film deposited non-selectively is described. In one embodiment, a carbon-doped silicon film is deposited non-selectively such that the film forms an epitaxial region where deposited on a crystalline surface and an amorphous region where deposited on an amorphous surface. A four-component wet etch mixture is tuned to selectively etch the amorphous region while retaining the epitaxial region, wherein the four-component wet etch mixture comprises an oxidizing agent, an etchant, a buffer and a diluent.

Abstract: To realize a high productivity while maintaining excellent film deposition characteristics on a substrate even if a plurality of processing gases of different gas species are used.

Abstract: In certain embodiments a method of forming a multi-layer silicon film is provided. A substrate is placed in a process chamber. An amorphous silicon film is formed on the substrate by flowing into the process chamber a first process gas comprising a silicon source gas. A polysilicon film is formed on the amorphous silicon film by flowing into the deposition chamber a first process gas mix comprising a silicon source gas and a first dilution gas mix comprising H2 and an inert gas at a first temperature. In certain embodiments, the polysilicon film has a crystal orientation which is dominated by the <220> direction. In certain embodiments, the polysilicon film has a crystal orientation dominated by the <111> orientation. Structures comprising a lower amorphous silicon film and an upper polysilicon film having a random grain structure or a columnar grain structure are provided as well.

Abstract: The manufacturing method of a semiconductor device according to the present invention comprises steps of forming a metal film, an insulating film, and an amorphous semiconductor film in sequence over a first substrate; crystallizing the metal film and the amorphous semiconductor film; forming a first semiconductor element by using the crystallized semiconductor film as an active region; attaching a support to the first semiconductor element by using an adhesive; causing separation between the metal film and the insulating film; attaching a second substrate to the separated insulating film; separating the support by removing the adhesive; forming an amorphous semiconductor film over the first semiconductor element; and forming a second semiconductor element using the amorphous semiconductor film as an active region.

Abstract: Various embodiments of the present invention comprise systems and methods of fabricating porous silicon. One application of such porous silicon is in the fabrication of electro-osmotic pumps and electro-osmotic pump substrates. The method can comprise operations performed on a silicon wafer. A liner material can be deposited on the silicon wafer, and a photoresist layer can be deposited on the liner material. The photoresist layer can be adapted to define a predetermined pattern on the silicon wafer. Then, porous silicon can be formed on the silicon wafer according to the predefined pattern. As a result, solid silicon can support porous silicon regions of the silicon wafer, providing a support structure for the pumping medium. Other embodiments, aspects, and features are also claimed and described.

Abstract: As an electrode area of a plasma CVD apparatus is enlarged, influence of the surface standing wave remarkably appears, and there is a problem in that in-plane uniformity of quality and a thickness of a thin film formed over a glass substrate is degraded. Two or more high-frequency electric powers with different frequencies are supplied to an electrode for producing glow discharge plasma in a reaction chamber. With glow discharge plasma produced by supplying the high-frequency electric powers with different frequencies, a semiconductor thin film or an insulating thin film is formed. High-frequency electric powers with different frequencies (different wavelengths), which are superimposed on each other, are applied to an electrode in a plasma CVD apparatus, so that increase in plasma density and uniformity for preventing effect of surface standing wave of plasma are attained.

Abstract: The present invention relates to a semiconductor device including a thin film transistor comprising a microcrystalline semiconductor which forms a channel formation region and includes an acceptor impurity element, and to a manufacturing method thereof. A gate electrode, a gate insulating film formed over the gate electrode, a first semiconductor layer which is formed over the gate insulating film and is formed of a microcrystalline semiconductor, a second semiconductor layer which is formed over the first semiconductor layer and includes an amorphous semiconductor, and a source region and a drain region which are formed over the second semiconductor layer are provided in the thin film transistor. A channel is formed in the first semiconductor layer when the thin film transistor is placed in an on state.

Abstract: A mask for crystallization of amorphous silicon to polysilicon is provided. The mask includes a plurality of slit patterns for defining regions to be illuminated. The plurality of slit patterns are formed along a longitudinal first direction and the mask moves along a longitudinal second direction. The first longitudinal direction is substantially perpendicular to the second longitudinal direction. Each of the split patterns is deviated apart by substantially a same distance from another. Thus, the polysilicon using the mask.

Abstract: A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.

Abstract: A structural film, typically of silicon, in MEMS or NEMS devices is fabricated by depositing the film in the presence of a gas other than nitrogen, and preferably argon as the carrier gas.

Abstract: The invention includes a method of fabricating a gate structure for a field effect transistor and the gate structure. The method includes providing a crystalline silicon substrate and epitaxially growing a gate insulating layer of crystalline rare earth insulating material on the crystalline silicon substrate. A gate stack of crystalline silicon is then epitaxially grown on the layer of crystalline rare earth insulating material and doped to provide a desired type of conductivity. The gate insulating layer and the gate stack are etched and a metal electrical contact is deposited on the epitaxially grown gate stack of crystalline silicon to define a gate structure.

Abstract: A method for manufacturing a semiconductor device is provided, which comprises at least a steps of forming a gate insulating film over a substrate, a step of forming a microcrystalline semiconductor film over the gate insulating film, and a step of forming an amorphous semiconductor film over the microcrystalline semiconductor film. The microcrystalline semiconductor film is formed by introducing a silicon hydride gas or a silicon halide gas when a surface of the gate insulating film is subjected to hydrogen plasma to generate a crystalline nucleus over the surface of the gate insulating film, and by increasing a flow rate of the silicon hydride gas or the silicon halide gas.

Abstract: A pre-metal dielectric structure of a single-poly EEPROM structure includes a UV light-absorbing film, which prevents the charge on a floating gate of the EEPROM structure from being changed in response to UV radiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer, an amorphous silicon layer located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the amorphous silicon layer.

Abstract: A phase change memory structure with multiple resistance states and methods of forming, programming, and sensing the same. The memory structure includes two or more phrase change elements provided between electrodes. Each phase change element has a respective resistance curve as a function of programming voltage which is shifted relative to the resistance curves of other phase change elements. In one example structure using two phase change elements, the memory structure is capable of switching among four resistance states.

Abstract: A phase-change-memory cell is provided which comprises two insulated regions formed in a first phase-change material connected by a region formed in a second phase-change material. The crystallization temperature of the second phase-change material is below the crystallization temperature of the first phase-change material. By locally changing the material properties using a second PCM material, which switches phase at a lower temperature, a localized “hot spot” is obtained.

Abstract: A method of manufacturing a semiconductor film capable of suppressing difficulty in temperature control of a catalytic wire is obtained. This method of manufacturing a semiconductor film includes steps of heating a catalytic wire to at least a prescribed temperature and forming a semiconductor film by introducing source gas for a semiconductor and decomposing the source gas with the heated catalytic wire after heating the catalytic wire to at least the prescribed temperature.

Abstract: A method of manufacturing a semiconductor film capable of inhibiting the quality of a semiconductor film from destabilization is obtained. This method of manufacturing a semiconductor film includes steps of introducing source gas for a semiconductor, controlling the pressure of an atmosphere formed by the source gas to a prescribed level, heating a catalytic wire to at least a prescribed temperature after controlling the pressure of the atmosphere to the prescribed level and forming a semiconductor film by decomposing the source gas with the heated catalytic wire.

Abstract: A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current density distribution around the first electrode.

Abstract: An artificial amorphous semiconductor material, and a junction made from the material, has a plurality of crystalline semiconductor material quantum dots substantially uniformly distributed and regularly spaced in three dimensions through a matrix of dielectric material or thin layers of dielectric materials. The material is formed by first forming a plurality of layers of dielectric material comprising a compound of a semiconducting material, and forming alternating layers as layers of stoichiometric dielectric material and layers of semiconductor rich dielectric material respectively. The material is then heated causing quantum dots to form in the semiconductor rich layers of dielectric material in a uniform and regularly spaced distribution in three dimensions through the dielectric material.

Abstract: A storage cell, integrated circuit (IC) chip with one or more storage cells that may be in an array of the storage cells and a method of forming the storage cell and IC. Each storage cell includes a stylus, the tip of which is phase change material. The phase change tip may be sandwiched between an electrode and conductive material, e.g., titanium nitride (TiN), tantalum nitride (TaN) or n-type semiconductor. The phase change layer may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) (GST) layer.

Abstract: A method and associated substrate is provided for applying a layer or pattern of metal on a substrate. The method includes providing a target substrate, immobilizing a layer of polymeric material on the target substrate, and applying and immobilizing a layer or pattern of metal on the layer of polymeric material on the target substrate using a stamp onto which the layer or pattern of metal has previously been applied, by bringing the stamp into conformal contact with the target substrate.

Abstract: Disclosed herein is a method of manufacturing a thin film transistor including titanium oxides as an active layer and the structure of the thin film transistor film manufactured using the method. The thin film transistor includes: a substrate; an active layer formed on the substrate using polycrystalline or amorphous titanium oxides; and an insulating layer formed on the active layer. Further, the method of manufacturing the thin film transistor includes: forming a substrate; forming an active layer on the substrate using polycrystalline or amorphous titanium oxides; and forming an insulating layer on the active layer.