Abstract: In the present invention, a vertical type MOSFET and a Schottky barrier diode which are used as a switching device of a DC--DC converter are formed on the same semiconductor substrate. Further, a barrier metal which is required for the Schottky barrier diode is also formed on an electrode portion of the vertical type MOSFET. In addition, a Schottky barrier diode forming region is formed to have low impurity concentration than a vertical type MOSFET forming region.

Abstract: A hot carrier transistor can be formed with semiconductor thin-film technology, for example hydrogenated amorphous silicon (a-Si:H) technology as used for large-area electronics devices. The emitter and collector regions (2 and 3) comprise hydrogenated amorphous semiconductor material (a-Si:H) adjoining an intermediate semiconductor-rich amorphous metal-semiconductor alloy layer (a-Si.sub.1-x M.sub.x :H) which provides the base region 1. The amorphous nature of the alloy layer (1) and its low percentage of metal M, e.g 5%, presents a range of quantum mechanical environments for the hot carriers (21) through the base region (1) with spatial variations of wavelength and effective mass (m*.sub.1, m*.sub.2). The current transport through this base region (1) will therefore be spatially self-selective in that the carriers (21) will tend to pass through those areas where there is a resonance between the wave function, the barrier heights (h1,h2) and the base width (x1,x2).

Abstract: A method of defining a line width includes forming a spacer (45) over a layer (42) and using the spacer (45) as an etch mask (57) while etching the layer (42). In this manner, a width (47) of the spacer (45) is used to define a width or line width (47) for the layer (42). Another method of using a spacer to define a line width includes forming a spacer (14) over a substrate (11), depositing a layer (15) over the substrate (11) and the spacer (14), planarizing the layer (15) to expose the spacer (14), and removing the spacer (14) to form an opening (19) over the substrate (11), wherein the opening (19) has a width or line width (17) of the spacer (14).

Abstract: Method for fabricating a semiconductor device is disclosed, including the steps of: forming a first resist layer on a substrate; patterning a predetermined region of the first resist layer to form a pattern having a first width which exposes the substrate; forming an insulating film on an entire surface of the substrate including the first resist layer; forming a second resist layer on the insulating film; patterning a predetermined region of the second resist layer to form a pattern over the pattern of the first resist layer having a second width which exposes the insulating film; using the second resist layer as a mask in etching the exposed insulating film to form sidewall spacers at sides of the pattern of the first resist layer; forming a metal layer on an entire resultant surface including the second photoresist layer; and, removing the first and second resist layers and the insulating film to form a T form gate electrode.

Abstract: A thin conformal passivating dielectric film is deposited by ECR-CVD on an IC chip comprising semiconductor devices each of which includes a sub-micron-width irregularly shaped gate electrode. A protective layer of patterned resist is formed overlying each passivated device. Additional dielectric material is then deposited by ECP-CVD, at a temperature below the glass transition temperature of the resist, on the surface of the chip. Subsequently, in a lift-off step, the patterned resist together with the additional dielectric material overlying the resist is removed from the chip.