Abstract: Methods for making solder balls, which can be used to bump semiconductor wafers are disclosed. Methods for bumping semiconductor wafers with the solder balls are also disclosed. The solder balls can be made using an injection molded soldering (IMS) process.

Abstract: A method of forming packages containing SiC or other semiconductor devices bonded to other components or conductive surfaces utilizing transient liquid phase (TLP) bonding to create high temperature melting point bonds using in situ formed ternary or quaternary mixtures of conductive metals and the devices created using TLP bonds of ternary or quaternary materials. The compositions meet the conflicting requirements of an interconnect or joint that can be exposed to high temperature, and is thermally and electrically conductive, void and creep resistant, corrosion resistant, and reliable upon temperature and power cycling.

Abstract: A method of forming contacts between at least one metallic layer and at least one semiconductor substrate through at least one layer of dielectric in a semiconductor device. The semiconductor device includes, on at least one base face of the semiconductor substrate, the dielectric layer. The metallic layer is stacked on the dielectric layer. The heated ends of plural protruding elements assembled on a support are brought into contact with the metallic layer simultaneously, thereby creating zones of melted metal under the heated ends of the protruding elements. The melted metal traverses the dielectric and amalgamates with the semiconductor of the substrate at the level of the zones of melted metal, thereby creating the contacts.

Abstract: Disclosed are an integrated circuit component capable of simply mounting at low cost a chip part which adjusts impedance of wiring patterns as well as capable of effectively reducing switching noise from an integrated circuit, and a method for mounting the chip part. The integrated circuit component of the present invention has a constitution that a bypass capacitor is mounted on a wiring board side of a gap between the wiring board and an LSI chip. Therefore, as compared with a case where the capacitor is mounted on the LSI chip side, a transmission path through the capacitor can be extremely shortened. As a result, inductance components of the feeder line can be reduced, so that a response delay of power transmitted through the feeder line can be sufficiently suppressed.

Abstract: A manufacturing method of a semiconductor device comprises: (a) setting up a paste including a resin on an electrical connection part which is electrically connected to a semiconductor substrate; (b) setting up a soldering material above the electrical connection part so as to be in contact with the paste; and (c) forming an external terminal from the soldering material and forming a reinforcement from the paste by fusing the soldering material and the paste. The reinforcement exposes part of the external terminal and covers a periphery of an edge of a base connected to the electrical connection part of the external terminal.

Abstract: An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond is described wherein the bond pad on a surface of the semiconductor device comprises a layer of copper and at least one layer of metal and/or at least a barrier layer of material between the copper layer and one layer of metal on the copper layer to form a bond pad.

Abstract: One example electronic assembly includes a substrate that has a plurality of contacts which become bonded to a plurality of contacts on a die. The electronic assembly further includes a male member that extends from at least one of the substrate and the die and a female member that extends from the other of the substrate and the die. The male member is inserted into the female member to align the die relative to the substrate. The male member and the female member may have any configuration as long as one or more portions of the male member extend partially, or wholly, into the female member. An example method includes aligning a die relative to a substrate by inserting a male member that extends from one of the die and the substrate into a female member that extends from the other of the die and the substrate.

Abstract: A nickel silicon alloy barrier layer formed between a metal bonding pad on an integrated circuit and a tin-based solder ball, for example, a lead-free solder. The nickel silicon alloy contains at least 2 wt % silicon and preferably less than 20 wt %. An adhesion layer may be formed between the barrier layer and the bonding pad. For copper metallization, the adhesion layer may contain titanium or tantalum; for aluminum metallization, it may be aluminum. The nickel silicon alloy may be deposited by magnetron sputtering. Commercially available NiSi4.5% sputter targets have provided a superior under-bump metallization (UBM) with lead-free tin solder bumps. Dopants other than silicon/may be used to reduce the magnetic permeability and provide other advantages of the invention.

Abstract: A method of providing electrically conductive bumps on electrode pads of a microelectronic substrate, and bumped substrate formed according to the method. The method includes: providing a substrate including first electrode pads and second electrode pads thereon, the first electrode pads exhibiting a first pattern, and the second electrode pads exhibiting a second pattern different from the first pattern; attaching first solder portions to a solder delivery head according to the first pattern, and second solder portions to a solder delivery head according to the second pattern, the second solder portions being larger than the first solder portions; after attaching, releasing the first solder portions onto the first electrode pads, and the second solder portions onto the second electrode pads; after releasing, reflowing the first solder portions and second solder portions to form, respectively, first solder bumps and second solder bumps on the electrode pads.

Abstract: A method for reducing gold embrittlement in solder joints, and a copper-bearing solder according to the method, are disclosed. Embodiments of the invention comprise adding copper to non-copper based solder, such as tin-lead solder. The embodiments may further comprise using the copper-bearing solder as a solder interconnect on a gold-nickel pad.

Abstract: Embodiments of a method for attaching a die to a substrate using a flame or other heat source are disclosed. The flame may be produced by combustible gas. Also disclosed are embodiments of a system for performing die attach using a flame. Other embodiments are described and claimed.

Abstract: Balls are sucked onto a carrier board so as to be temporarily arranged in a ball arrangement region of the board, and then the balls are transferred and bonded onto an objective substance with their positions being adjusted. Gas blow is applied to the temporarily arranged balls or alternatively the temporarily arranged balls are sucked, so as to remove excess balls other than balls that have been exactly sucked onto the ball arrangement region. Cooperation with application of fine vibration to the carrier board makes the removal of the excess balls more efficient.

Abstract: A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.

Abstract: Methods of forming a conductive structure on a substrate prior to packaging, and a test probe structure generated according to the method, are disclosed. The conductive structure includes a high aspect ratio structure formed by injected molded solder. The invention can be applied to form passive elements and interconnects on a conventional semiconductor substrate after the typical BEOL, and prior to packaging. The method may provide better electromigration characteristics, lower resistivity, and higher Q factors for conductive structures. In addition, the method is backwardly compatible and customizable.

Abstract: A solder ball 50 according to the present invention includes a spherical core 2 and a solder layer 4, which includes Sn and Ag and which is provided so as to wrap the core 2 up. The amount of water contained in the solder layer 4 is 100 ?l/g or less when represented by the amount of water vapor in standard conditions.

Abstract: A method of reducing a likelihood that a die pad will be delaminated from a die in an integrated circuit die package for a structure design during an attachment of a heat sink member to the die pad using solder, is provided. A sample structure of the structure design is evaluated to determine whether a volume of last solidification for the solder is centrally located with respect to the die pad and is located at or near an interface of the solder and the die pad. If the last solidification volume is centrally located and is located at or near the interface of the solder and the die pad, and if the die pad is delaminated from the die, the structure design is modified so that less metal of the heat sink member is centrally located than before the modifying.

Abstract: A carrier for use in a chip-scale package, including a polymeric film with apertures defined therethrough. The apertures, which are alignable with corresponding bond pads of a semiconductor device, each include a quantity of conductive material extending substantially through the length thereof. The carrier may also include laterally extending conductive traces in contact with or otherwise in electrical communication with the conductive material in the apertures of the carrier. Contacts may be disposed on a backside surface of the carrier. The contacts may communicate with the conductive material disposed in the apertures of the carrier. A conductive bump, such as a solder bump, may be disposed adjacent each or any of the contacts. A chip-scale package including the carrier of the present invention is also within the scope of the present invention.

Abstract: A method of making an electronic package is described, wherein a substrate is provided with a pattern of conductive pads and a portion of solder positioned on selected ones of the pattern of copper pads. The solder is then reflowed to form partial hemispherically shaped caps on the selected copper pads. The partial hemispherically shaped caps are then coated with a solder flux. A thin semiconductor chip with a pattern of conductive elements, corresponding to partial hemispherically shaped capped pads, is then positioned on the substrate so that the conductive elements of the thin semiconductor chip substantially line up with the partial hemispherically shaped capped pads of the substrate. The solder is then heated to reflow temperature and an electrical couple is formed between the thin semiconductor chip and the substrate.

Abstract: The present invention relates to a flip chip on leadframe package and the method for making the same. The method comprises: (a) providing a leadframe having a plurality of inner leads; (b) providing a chip having an active surface; (c) forming a plurality of first bumps and at least one second bump on the active surface of the chip, wherein the material of the first bumps is same as that of the second bump, and the height of the second bump is lower than that of the first bumps; (d) dipping the top of the bumps in a flux so that the first bumps are dipped with the flux, and the second bump is not dipped with the flux; (e) contacting the first bumps to the corresponding inner leads; (f) proceeding with a reflow step so that the first bumps are melted and connected to the corresponding inner leads, and the second bump is connected to the corresponding inner lead without being melted so as to maintain the gap between the chip and the inner leads.

Abstract: Vias (210, 210B) are formed in a surface of a substrate. At least portions of contact pads (139, 350) are located in the vias. Contact pads (150, 340) of an integrated circuit structure are inserted into the vias and attached to the contact pads (139, 350) of the substrate. The vias provide a strong, reliable mechanical and electrical connection. A via may expose not only a contact pad (350) in the substrate but also a surrounding region. Solder (930) wets the contact pad better than the surrounding region, resulting in a stronger solder joint and better electrical conductivity. Alternatively, the contact may include multiple conductive layers (910.1, 910.2), with the top layer (910.2) being more solder wettable than the bottom layer (910.1) and the top layer covering only a portion of the bottom layer.

Abstract: A process for fabricating a pad frame for an integrated circuit package includes building up metal on selective portions of a first side of a substrate to define a plurality of contact pads disposed in a first layer of dielectric material, depositing a metal seed layer on an exposed side of the contact pads and the dielectric material, applying a second metal layer on the metal seed layer, selectively etching the second metal layer and the metal seed layer to provide pad frame circuitry, and building up metal on selective portions of the pad frame circuitry to define a plurality of die connect pads separated by a second layer of dielectric material, the die connect pads being electrically connected to the contact pads by the pad frame circuitry.

Abstract: The present invention relates to an integrated device comprising an electronic circuit chip, a solder contact structure to provide contact to the electronic circuit chip and an elastic contact structure to provide contact to the electronic circuit chip, wherein the solder contact structure and the elastic contact structure are arranged on a contacting surface of the integrated device.

Abstract: Disclosed are embodiments of a method of attaching a die to a substrate and a heat spreader to the die in a single heating operation. A number of conductive bumps extending from the die may also be reflowed during this heating operation. Other embodiments are described and claimed.

Abstract: The present invention relates to an improved method of forming and structure for under bump metallurgy (“UBM”) pads for a flip chip which reduces the number of metal layers and requires the use of only a single passivation layer to form, thus eliminating a masking step required in typical prior art processes. The method also includes repatterning bond pad locations.

Abstract: An assembly of a semiconductor chip (301) having an integrated circuit (IC) including at least one contact pad (320) on its surface (301a), wherein the contact pad has a metallization suitable for wire bonding, and an interconnect bonded to said contact pad. This interconnect includes a wire (304) attached to the pad by ball bonding (305), a loop (306) in the wire closed by bonding the wire to itself (307) near the ball, and a portion (307) of the remainder of the wire extended approximately parallel to the surface. The interconnect can be confined to a space (308) equal to or less than three ball heights from the surface.

Abstract: Solder bump structures for semiconductor device packaging is provided. In one embodiment, a solder bump structure comprises a semiconductor substrate, the substrate has at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad. At least one patterned and etched polymer layer is formed on a portion of the contact pad. At least one patterned and etched conductive metal layer is formed above the polymer layer and is aligned therewith. And at least one layer of solder material having a solder height is provided above the conductive metal layer, the layer of solder is aligned with the conductive metal layer, the layer of solder is thereafter reflown thereby creating a solder ball.

Abstract: A method of bonding semiconductor devices is disclosed. The method comprises providing a first substrate having a first conductive interconnecting structure formed thereon and a second substrate having a second conductive interconnecting structure formed thereon. A first conductive passivation layer is selectively formed over exposed areas of the first conductive interconnecting structure. A second conductive passivation layer is selectively formed over exposed areas of the second conductive interconnecting structure. The first substrate and the second substrate are bonded together in such a way that the first conductive passivation layer bonds to the second conductive passivation layer to create a passivation-passivation interface.

Abstract: A bonding structure with a buffer layer, and a method of forming the same are provided. The bonding structure comprises a first substrate with metal pads thereon, a protection layer covered on the surface of the substrate, a first adhesive metal layer formed on the metal pads, a buffer layer coated on the protection layer and the metal pads, a first metal layer covered on the buffer layer, and a second substrate with electrodes and a bonding layer thereon. The first metal layer, the electrodes and the bonding layer are bonded to form the bonding structure. Direct bonding can be performed through surface activation or heat pressure. The method uses fewer steps and is more reliable. The temperature required for bonding the structure is lower. The bonding density between the contacted surfaces is increased to a fine pitch. The quality at the bonding points is increased because fewer contaminations between the contacted surfaces are generated.

Abstract: A method for mounting a passive component on a wafer. A passivation layer is disposed on a wafer having at least one first metal pad and at least one second metal pad thereon, which substantially exposes the first and second metal pads. A capping layer is formed on the exposed first metal pad, and an under ball metallurgy (UBM) layer is formed on the exposed second metal pad. A photoresist pattern layer is formed overlying the wafer to cover the capping layer and the passivation layer and expose the UBM layer. A solder bump is formed on the exposed UBM layer. After the photoresist pattern layer and the capping layer are successively removed, a passive component is mounted on the wafer through the solder bump.

Abstract: A bonding pad of a semiconductor device and a fabrication method thereof are disclosed. A semiconductor device having a pad formed by exposing a predetermined region of a metal line formed over a semiconductor substrate includes an alloy layer formed on the metal line exposed through the pad. The alloy layer is formed from a reaction between the metal line and a metal having a melting point less than or equal to 1000° C.

Abstract: A microelectronic package is disclosed including a microelectronic device, a substrate, and a signaling path coupling the microelectronic device with the substrate. The signaling path includes a conductive material, a solder joint, and a barrier material disposed between the conductive material and the solder joint. The barrier material may include nickel, cobalt, iron, titanium, and combinations thereof.

Abstract: The resist film is provided on the surface of the substrate having electrodes, and openings are provided in the resist film at positions of the electrodes on the substrate. The first metal is supplied into the openings. The first metal is then heated to melt and coagulate it. The second metal is then supplied into the openings on the first metal. The first metal and the second metal are heated to melt and coagulate them. The resist film is finally removed. By this method, excellent solder bumps can be formed on the substrate without remnants of the resist film being left on the substrate.

Abstract: The present invention is directed to a method for enhancing functionality for photonic devices each including at least one operable surface. This method includes stacking the photonic devices such that each of the operable surfaces are aligned to form a composite surface, applying a film adapted to receive a replication to the composite surface and replicating a pattern of nanostructures in the applied film. Substantially, each of the operable surfaces is replicated with a sufficient portion of the replicated pattern of nanostructures to enhance operation of the devices by performing a given function associated with the nanostructures.

Abstract: The present invention provides a method for producing a temporary chip carrier for semiconductor chip burn-in test and speed sorting. A multi-layered substrate or card, usually comprised of one of various materials is made by offsetting the conductor-filled vias or holes in the outer few layers with the outer most layer not being filled with a conductor, such that a partially filled via or hole is produced. This effectively produces a smaller surface conductor feature, on which the semiconductor chip is temporarily attached, electrically tested, and subsequently removed using various methods, at forces much lower than normal chip removal processes require.

Abstract: A method of forming and a device including an interconnect structure having a unidirectional electrical conductive material is described. The unidirectional conductive material may overlie interconnect materials, and/or may surround interconnect materials, such as by lining the walls and base of a trench and via. The unidirectional conductive material may be configured to conduct electricity in a direction corresponding to a projection to or from a contact point and conductive material overlying the unidirectional conductive material, but have no substantial electrical conductivity in other directions. Moreover, the unidirectional conductive material may be electrically conductive in a direction normal to a surface over which it is formed or in directions along or across a plane, but have no substantial electrical conductivity in other directions.

Abstract: A metal electrode is formed on a substrate. The metal electrode includes a first layer, a second layer, and a third layer lying, from an outermost surface of the metal electrode toward the substrate, in this order. The first layer contains tin as a principal constituent and the second layer contains a metallic element which produces an eutectic reaction with tin, wherein the melting point of the first layer is higher than the melting point of the second layer. The third layer is an underlying metallic layer for the first and second layers.

Abstract: A manufacturing method of a semiconductor device includes a support member for fixing a semiconductor chip, the support member being formed between leads without applying stress to the leads. The semiconductor device includes a plurality of leads composing a lead frame, a resin island (a support member) that is formed between the leads, a semiconductor chip that is fixed on the resin island and is electrically connected to the leads by bonding wires, and sealing resin for partially sealing the semiconductor chip, the bonding wire, and the lead by resin, wherein a liquid cured resin is formed (filled) between the leads to form the resin island (the support member).

Abstract: A method of forming a bump electrode on an IC electrode includes the steps of forming a ball bond on an IC electrode by a wire bonding apparatus, moving a bonding capillary upward, moving the bonding capillary sideways and then downward, bonding an Au wire to the ball bond portion, and cutting the Au wire. The Au wire is prevented from coming in contact with portions around the ball bond portion other than the ball bond portion by presetting a descent position of the bonding capillary to a position higher than a position in which the ball bond is formed.

Abstract: A method of forming a multi-layer semiconductor structure includes providing a first layer of a patterned copper bond film having a first predetermined thickness onto a first surface of a first semiconductor. The method further includes providing a second layer of a patterned copper bond film having a second predetermined thickness onto a first surface of a second semiconductor. The first and second semiconductor structures can be aligned, such that the first and second patterned copper bond films are disposed in proximity. A virtually seamless bond can be formed between the first and second patterned copper bond films to provide the first and second semiconductors as the multi-layer semiconductor structure.

Abstract: A dam for substantially laterally confining a quantity of encapsulant material over a region of a substrate, such as an interposer. The dam is configured to protrude upwardly from a surface of the interposer or other substrate. The interposer may be positioned at least partially around a slot or aperture through the substrate so as to laterally confine encapsulant material over the slot or aperture and over any intermediate conductive elements extending through the slot or aperture. The dam may be fabricated by stereolithography. A package including the interposer, the dam, and a semiconductor die to which the interposer is secured may include a sealing element between the interposer and the active surface of the die. All or part of the sealing element may also be fabricated using stereolithography. Methods and systems using machine vision in conjunction with stereolithography equipment are also disclosed.

Abstract: A method of making a microelectronic assembly buying restraining a substrate in a fixture at room temperature, placing a flip chip on the substrate so that conductive bumps on the flip chip are aligned with contact pads on the substrate, heating the flip chip, the substrate and the fixture to reflow the conductive bumps on the flip chip, cooling the flip chip, substrate and fixture to solidify the conductive bumps and to mount the flip chip to the substrate, depositing an underfill between the flip chip and the substrate, curing the underfill by heating the flip chip, substrate, underfill and fixture to an elevated temperature, and removing the flip chip mounted substrate from the fixture.

Abstract: A method of constructing an electrical contact on an electronic component comprises first forming a protruding electrically conducting stud at a contact location by wire bonding a metal wire to a contact pad of the component. The stud is then contacted with solder, without using a mask, so that a solder bump is deposited on and adheres to the metal stud to form a composite solder contact which is able to form with a contact of another component a solder joint which has good electrical and mechanical properties and which may be reliable fabricated at high density by a low cost method. An electronic component provided with such solder contacts and an electronics component package including such a component are also disclosed.

Abstract: A method for manufacturing an integrated circuit package is provided with a substrate having first and second contact pads exposed through a passivation layer on the substrate. A first metallurgy layer is formed over the substrate. A second metallurgy layer is formed over the first metallurgy layer. The first metallurgy layer is removed while leaving a portion thereof over the second contact pad. The second metallurgy layer is removed while leaving a portion thereof over the second contact pad. A protective layer is formed over the first contact pad while removing the first metallurgy layer.

Abstract: A wafer-level chip-scale package includes a semiconductor die having planar top and bottom surfaces and a plurality of metal pads formed at the top surface in an area array. A first protective layer is formed on the top surface of the semiconductor die, the first protective layer having a plurality of first apertures for allowing the metal pads to be opened upward. A second protective layer is formed on a surface of the first protective layer, the second protective layer having a plurality of second apertures which are larger than and overly corresponding first apertures of the first protective layer so that regions of the metal pads and the first protective layer are exposed to the outside of the semiconductor die. Solder balls are fused to each metal pad, which are opened to the outside through the first apertures of the first protective layer and the second apertures of the second protective layer.

Abstract: Disclosed herein are a method of manufacturing a solder bump on a semiconductor device, a solder bump structure formed on a substrate, and an intermediate solder bump structure. In one embodiment, the method includes creating a bonding pad over a semiconductor substrate, and placing a mask layer over the substrate and the bonding pad. The method also includes forming an opening in the mask layer having a primary solder mold and at least one secondary solder mold joined with the primary mold, where the opening exposes a portion of the bonding pad. In this embodiment, the method further includes filling the primary solder mold and the at least one secondary solder mold with solder material to form corresponding primary and at least one secondary solder columns in electrical contact with the bonding pad. The method also includes removing the mask layer after the filling of the solder molds with the solder material.

Abstract: Solder joints coupling pins to a microelectronic package substrate are enshrouded with an encapsulation material. In this manner, pin movement is limited even if the pin solder subsequently melts.

Abstract: A method for protecting a semiconductor process wafer surface from contacting thermally degraded photoresist including providing a semiconductor process wafer having a process surface; forming a protective layer over selected areas of the process surface said protective layer including a resinous organic material having a glass transition temperature (Tg) that is about greater than a thermal treatment temperature; forming a photoresist layer over at least a portion of the protective layer to include a photolithographic patterning process; and subjecting the semiconductor process wafer to the thermal treatment temperature.

Abstract: A semiconductor die having multiple solder bumps, each having a diameter less than about 100 microns, and the method for making such a die are described. The solder bumps are preferably about 10 microns in diameter, and the pitch between the solder bumps is less than 100 microns, and preferably less than or equal to 10 microns. A thermal solder jet apparatus is utilized to deposit solder material to form the solder bumps. The apparatus includes a print head having a plurality of solder ejection ports. Each ejection port has an associated gas ejection conduit connected to a chamber containing one or more hydride films. The hydride film is heated to disassociate hydrogen gas. The hydrogen gas rapidly builds up in the conduit which leads to the ejection port which is loaded with a solder material and forces the ejection of the solder material from the port.

Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a structure that couples a first conductive body of a first substrate to a second conductive body of a second substrate (e.g., a chip to a chip carrier; a chip carrier to a circuit card). The melting point of the first conductive body exceeds the melting point of the second conductive body. The second conductive body may include eutectic lead-tin alloy, while the first conductive body may include non-eutectic lead-tin alloy. A portion of the first conductive body is coated with, or volumetrically surrounded by, a material that is nonsolderable and nonconductive. The first and second conductive bodies are coupled mechanically and electrically by surface adhesion at an uncoated portion of the first conductive body, by application of a temperature that lies between the melting points of the first and second conductive bodies.

Abstract: A method is provided for producing a substrate arrangement. The process includes the preparation of a substrate and bringing connecting surfaces of the substrate into contact with inner contacts of a wiring layer, the application of contact material to outer contacts of the wiring layer defining an outer connecting surface arrangement to form base contact bumps (31) and the application of joining material to the base contact bumps to form contact bump tops joined to the base contact bumps, wherein the joining material is applied as joining material moldings (35) and the contact bump tops are formed by at least partial melting of the joining material moldings by the action of laser energy.