Abstract: An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer comprising a porous matrix, as well as a porogen in certain variations, is formed adjacent a sacrificial dielectric layer. Subsequent to other processing treatments, a portion of the sacrificial dielectric layer is decomposed and removed through a portion of the porous matrix using supercritical carbon dioxide leaving voids in positions previously occupied by portions of the sacrificial dielectric layer. The resultant structure has a desirably low k value as a result of the voids and materials comprising the porous matrix and other structures. The composite dielectric layer may be used in concert with other dielectric layers of varying porosity, dimensions, and material properties to provide varied mechanical and electrical performance profiles.

Abstract: A temporary support layer 2 is formed on a semiconductor substrate 1, and the temporary support layer 2 is provided with a hole 4 that reaches the semiconductor substrate 1. The hole 4 is filled in with a conductor material 5, and by pressurizing the conductor material 5, the conductor material 5 and the semiconductor substrate 1 are pressure-bonded. Thereby, an aerial wiring structure whose bonding strength is improved and that has excellent self-sustainability can be obtained.

Abstract: A method of making a semiconductor device comprising: providing a semiconductor substrate having a plurality of discrete devices formed therein, and a plurality of metal layers and support layers, the support layers comprising an uppermost support layer and other support layers, and wherein each metal layer has an associated support layer having at least a portion underlying the metal layer, and wherein the plurality of metal layers includes an uppermost metal layer including a sealing pad having an opening therethrough, and a passivation layer having at least one opening therein exposing a portion of the sealing pad including the opening therethrough, and the uppermost support layer having a portion exposed through the opening in the sealing pad; exposing the uppermost support layer to an etching material through the opening in the sealing pad and etching away the support layers; and sealing the opening in the sealing pad.

Abstract: After flattening a surface of an underlying film that has pores or includes an organic material by treating the underlying film in a supercritical fluid, a resist film made of a chemically amplified resist material is formed on the underlying film whose surface has been flattened. Next, pattern exposure is performed by selectively irradiating the resist film with exposing light, and then, the resist film is developed after the pattern exposure, so as to form a resist pattern.

Abstract: A wafer level fabricated chip scale integrated circuit package having an air gap formed between the integrated circuit die of the package and compliant leads located over and conductively attached to the die is described. Contact bumps offset on the compliant leads provide for connection of the integrated circuit package to other substrates. In some embodiments, the compliant leads include a conductive layer overlaid with an outer resilient layer, and may further include an inner resilient layer beneath the conductive layer. The outer resilient layer has a via formed through it exposing the underlying conductive layer. The via is offset along the compliant lead a horizontal distance from the bond pad to which the compliant lead is conductively coupled. The chip scale package provides a highly compliant connection between the die and any substrate that the die is attached to.

Abstract: A method for forming interlevel dielectric levels in a multilevel interconnect structure formed by a damascene process. The conductive features characteristic of the damascene process are formed in a removable mandrel material for each level of the interconnect structure. In at least one level, a portion of the mandrel material underlying the bond pad is clad on all sides with the metal forming the conductive features to define a support pillar. After all levels of the interconnect structure are formed, the mandrel material surrounding the conductive features is removed to leave air-filled voids that operate as an interlevel dielectric. The support pillar is impermeable to the etchant such that mandrel material and metal inside the support pillar is retained. The support pillar braces the bond pad against vertical mechanical forces applied by, for example, probing or wire bonding and thereby reduces the likelihood of related damage to the interconnect structure.

Abstract: A semiconductor device having an interlayer insulation film with a low capacitance and a method of fabricating the same are disclosed. An example semiconductor device having a multi-layered metal wire structure includes first and second interlayer insulation films provided between lower metal wire layers and upper metal wire layers. The example semiconductor device also includes air gaps formed in the first interlayer insulation film at an interlevel between the upper and lower metal wire layers and via holes connecting the upper and lower metal wire layers.

Abstract: A method for forming a gas dielectric with support structure on a semiconductor device structure provides low capacitance and adequate support for a conductor of the semiconductor device structure. A conductive structure, such as via or interconnect, is formed in a wing-layer dielectric. A support is then formed that connects to the conductive structure, the support including an area thereunder. The wiring-layer dielectric is then removed from the area to form a gas dielectric.

Abstract: An embodiment of the present invention includes a method to form an air gap in a multi-layer structure. A dual damascene structure is formed on a substrate. The dual damascene structure has a metallization layer, a barrier layer, a sacrificial layer, and a hard mask layer. The sacrificial layer is made of a first sacrificial material having substantial thermal stability and decomposable by an electron beam. The sacrificial layer is removed by the electron beam to create the air gap between the barrier layer and the hard mask layer.

Abstract: A low-k dielectric sacrificial material is formed within a microelectronic structure covered with a layer defining an exhaust vent. At an appropriate time, the underlying sacrificial material is decomposed and exhausted away through the exhaust vent. Residue from the exhausted sacrificial material accumulates at the vent location during exhaustion until the vent is substantially occluded. As a result, an air gap is created having desirable characteristics as a dielectric.

Abstract: An integrated circuit having at least one electrical interconnect for connecting at least two components and a process for forming the same are disclosed. At least two opposing, contoured, merging dielectric surfaces define at least one elongated passageway which has at least one opening. A conductive material then substantially fills the at least one opening and at least one elongated passageway to form at least one electrical interconnect guided by the at least one elongated passageway and extended through the layer of dielectric material along the length to electrically connect at least two of the components of the integrated circuit.

Abstract: An inter-level insulator structure is provided having an effective insulator dielectric constant approaching 1. An embodiment of the inter-level insulator comprises a first metal layer comprising a first plurality of metal lines; a second metal layer comprising a second plurality of metal lines, and at least one via connected to the first metal layer; and an air gap interposed between the first metal layer and the second metal layer. In one embodiment, the air gap is also present between metal lines on either metal layer, such that air gaps act as intra-level as well as inter-level insulators. A method is also provided to deposit and pattern a sacrificial polymer, and form metal layers. The sacrificial polymer is capable of being decomposed to become air gaps during annealing.

Abstract: A method for forming back-end-of-line (BEOL) interconnect structures in disclosed. The method and resulting structure includes etchback for low-k dielectric materials. Specifically, a low dielectric constant material is integrated into a dual or single damascene wiring structure which contains a dielectric material having relatively high dielectric constant (i.e., 4.0 or higher). The damascene structure comprises the higher dielectric constant material immediately adjacent to the metal interconnects, thus benefiting from the mechanical characteristics of these materials, while incorporating the lower dielectric constant material in other areas of the interconnect level.

Abstract: A semiconductor device has a first insulating film deposited over a semiconductor substrate, an interconnect opening portion formed in the first insulating film, an interconnect disposed in the interconnect opening portion, and a second insulating film formed over the first insulating film and the interconnect. The interconnect has a first conductor film, a second conductor film formed via the first conductor film and comprised of one of titanium silicon nitride, tantalum silicon nitride, tantalum nitride and titanium nitride, a third conductor film formed via the first and second conductor films and comprised of a material having good adhesion with copper; and a fourth conductor film formed via the first, second and third conductor conductor film having a copper as a main component. Thus, it is possible to improve adhesion between a conductor film composed mainly of copper and another conductor film having a copper-diffusion barrier function in the interconnect.

Abstract: In one embodiment, an apparatus comprises a first layer having at least one interconnect formed in an interlayer dielectric (ILD), a second layer formed over the first layer having a second at least one interconnect, a third layer formed over the second layer, the third layer defining at least one air gap between the second at least one interconnect and the third layer, and at least one shunt selectively covering the first and second at least one interconnects. In another embodiment, a method comprises forming a first layer comprising an ILD and a first at least one interconnect, forming a second layer over the first layer, the second layer having a second at least one interconnect, depositing at least one shunt over the first and second at least one interconnects, forming a third layer over the second layer, and evaporating a portion of the second layer to create at least one air gap between the second at least one interconnect and the third layer.

Abstract: A method to fabricate a silicon-on-nothing device on a silicon substrate is provided. The disclosed silicon-on-nothing device is fabricated on an isolated floating silicon active area, thus completely isolated from the silicon substrate by an air gap. The isolated floating silicon active area is fabricated on a silicon germanium layer with a surrounding isolation trench. A plurality of anchors is then fabricated to anchor the silicon active area to the silicon substrate before selectively etching the silicon germanium layer to form the air gap. Isolation trench fill and planarization complete the formation of the isolated floating silicon active area. The silicon-on-nothing device on the isolated floating silicon active area can be polysilicon gate or metal gate and with or without raised source and drain regions.

Abstract: A semiconductor device having contact surfaces of different heights electrically connected to conductors defined on one or more patterned metal planes and a method for fabricating the semiconductor device. In one embodiment, the semiconductor device comprises a substrate having a process surface; a first contact and a second contact arranged on the substrate, a second contact surface of the second contact being at a greater distance, in a substrate-normal direction, from the substrate than a first contact surface of the first contact; a first conductor disposed in a first patterned metal plane and electrically connected to the first contact surface; and a second conductor disposed in a second patterned metal plane and electrically connected to the second contact surface, wherein the second metal plane is disposed at a greater distance, in the substrate-normal direction, from the substrate than the first metal plane.

Abstract: A plurality of metal interconnects are formed on a lower interlayer insulating film provided on a semiconductor substrate. An upper interlayer insulating film is formed so as to cover the plural metal interconnects. The upper interlayer insulating film has an air gap between the plural metal interconnects, and a top portion of the air gap is positioned at a level higher than the plural metal interconnects.

Abstract: A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.

Abstract: The device and process include the deposition of polycrystalline germanium in the interconnect spaces between conductive metal elements. The device and process further include the removal of the germanium in order to form air-filled interconnect spaces.

Abstract: A protective pattern is formed on a semiconductor substrate in a shape covering a circuit region and exposing an air bridge connecting portion, a metallic film and an insulating film are formed to cover the protective pattern, the metallic film and the insulating film are patterned to form air bridge wiring and an air bridge protective film covering the air bridge wiring, and thereafter, the protective pattern is removed to form a hollow between the air bridge wiring and the circuit region.

Abstract: A typical air bridge is an aluminum conductor suspended across an air-filled cavity to connect two components of an integrated circuit, two transistors for example. The air-filled cavity has a low dielectric constant which reduces cross-talk between neighboring conductors and improves speed and efficiency of the integrated circuit. However, current air bridges must be kept short because typical aluminum conductors sag too much. Accordingly, one embodiment of the invention forms air-bridge conductors from an aluminum-beryllium alloy, which enhances stiffness and ultimately provides a 40-percent improvement in air-bridge lengths.

Abstract: In one aspect, the present invention features a method of manufacturing an integrated circuit package including providing a substrate having a first surface, a second surface opposite the first surface, a cavity through the substrate between the first and second surfaces and a conductive via extending through the substrate and electrically connecting the first surface of the substrate with the second surface of the substrate, applying a strip to the second surface of the substrate, mounting a semiconductor die on the strip, at least a portion of the semiconductor die being disposed inside the cavity, encapsulating in a molding material at least a portion of the first surface of the substrate, and removing the strip from the substrate.

Abstract: A semiconductor device having conductive paths separated by cavities is formed by depositing organic spin-on glass between the conductive paths, forming gaps between the organic spin-on glass and the conductive paths, and then removing the organic spin-on glass through the gaps. The gaps may be formed as a dummy pattern of via holes that are misaligned with the conductive paths, so that they extend past the upper surfaces of the conductive paths and form fine slits beside the conductive paths. This method of removing the spin-on glass leaves cavities that are free of unwanted oxide residue and debris, thereby minimizing the capacitive coupling between adjacent conductive paths.

Abstract: A method of forming a multilevel conductor structure for ULSI circuits is provided. The structure includes a substrate having a plurality of dielectric supports extending from the substrate to support conductor layers. A removable material is deposited progressively on the substrate. An insulating ‘dome’ is formed over the conductor envelope and the material. Openings are provided through the dome for removing the material. The evacuated ‘dome envelope’ is filled with a near-unity dielectric constant gas or liquid at or above atmospheric pressure to enhance heat removal. The openings are sealed to provide a dielectric medium around the conductors within the envelope. Metal conductors within the envelope electrically connect active devices to other active regions as well as to the external environment.

Abstract: Embodiments of the invention generally provide a method of forming an air gap between conductive elements of a semiconductor device, wherein the air gap has a dielectric constant of approximately 1. The air gap may generally be formed by depositing a dielectric material between the respective conductive elements, depositing a porous layer over the conductive elements and the dielectric material, and then stripping the dielectric material out of the space between the respective conductive elements through the porous layer, which leaves an air gap between the respective conductive elements. The dielectric material may be, for example, an amorphous carbon layer, the porous layer may be, for example, a porous oxide layer, and the stripping process may utilize a downstream hydrogen-based strip process, for example.

Abstract: The present invention provides a method of manufacturing an electronic device provided with metal regions, that are mutually separated by air spaces. In the method a first isolating layer, a seed layer and a second isolating layer are provided before applying metal regions. The seed layer and the second isolating layer are only removed after the provision of the metal regions. The method can be advantageously applied for the manufacture of a multilevel interconnect structure and for the manufacture of micro-electromechanical elements.

Abstract: A new method of creating a relatively thick layer of PE silicon nitride. A conventional method of creating a layer of silicon nitride applies a one-step process for the creation thereof. Film stress increases as the thickness of the created layer of PE silicon nitride increases. A new method is provided for the creation of a crack-resistant layer of PE silicon nitride by providing a multi-step process. The main processing step comprises the creation of a relatively thick, compressive film of PE silicon nitride, over the surface of this relatively thick layer of PE silicon nitride is created a relatively thin (between about 150 and 500 Angstrom) layer of tensile stress PE silicon nitride. This process can be repeated to create a layer of PE silicon nitride of increasing thickness.

Abstract: One via contact through which upper and lower interconnections of a multilevel interconnection are connected to each other is provided when the width or volume of the lower interconnection is not larger than a given value. A plurality of via contacts are arranged at regular intervals, each of which is not larger than a given value, in an effective diffusion region of voids included in the lower interconnection, when the width or volume of the lower interconnection exceeds a given value.

Abstract: Conductive lines, such as co-axial lines, integrated circuitry incorporating such conductive lines, and methods of forming the same are described. In one aspect, a substrate having an outer surface is provided. A masking material is formed over the outer surface and subsequently patterned to form a conductive line pattern. An inner conductive layer is formed within the conductive line pattern, followed by formation of a dielectric layer thereover and an outer conductive layer over the dielectric layer. Preferred implementations include forming the inner conductive layer through electroplating, or alternatively, electroless plating techniques. Other preferred implementations include forming the dielectric layer from suitable polymer materials having desired dielectric properties. A vapor-deposited dielectric layer of Parylene is one such preferred dielectric material.

Abstract: In the method of manufacturing a semiconductor device, via holes and first trenches to form an air gap are concurrently formed in a first insulating film on a semiconductor substrate and a second insulating film is formed thereon. Thereafter, the second insulating film lying outside the area corresponding to the regions where the first trenches to form an air gap are formed is partially removed to form trenches for wiring by using a mask. A plurality of wirings are formed by filling in the trenches for wiring with a metal film. The second insulating film remaining in the regions where the first trenches to form an air gap are formed is then removed to form second trenches to form an air gap. Subsequently, in forming a third insulating film, air gaps are formed within the second trenches to form an air gap.

Abstract: A system and method for removing a conductive line from a semiconductor device is disclosed. The conductive line includes a conductive layer and a barrier layer separating the conductive layer from a portion of the semiconductor device. The method and system include exposing a portion of the barrier layer, etching the barrier layer after the barrier layer has been exposed, and lifting off the conductive layer after the barrier layer has been etched.

Abstract: A method of fabricating an interconnect line comprises forming a wall, depositing an etch mask having a thickness that decreases towards a bottom of the wall, and isotropically etching the wall at the bottom to form the interconnect line having a pre-determined gap between the substrate and a bottom of the line.

Abstract: A plurality of metal interconnects are formed on a lower interlayer insulating film provided on a semiconductor substrate. An upper interlayer insulating film is formed so as to cover the plural metal interconnects. The upper interlayer insulating film has an air gap between the plural metal interconnects, and a top portion of the air gap is positioned at a level higher than the plural metal interconnects.

Abstract: An ultraviolet sensitive material may be formed within a semiconductor structure covered with a suitable hard mask. At an appropriate time, the underlying ultraviolet sensitive material may be exposed to ultraviolet radiation, causing the material to exhaust through the overlying hard mask. As a result, an air gap may be created having desirable characteristics as a dielectric.

Abstract: In a method for producing a diaphragm sensor unit having a semiconductor material substrate, a flat diaphragm and an insulating well for thermal insulation below the diaphragm are generated, for the formation of sensor element structures for at least one sensor. The substrate, made of semiconductor material, in a specified region, which defines sensor element structures, receives a deliberately different doping from the surrounding semiconductor material, that porous semiconductor material is generated from semiconductor material sections between the regions distinguished by doping, and semiconductor material in the well region under semiconductor is rendered porous and under parts of the sensor element structure is removed and/or rendered porous.

Abstract: A method for implementing a bismaleimide (BMI) polymer as a sacrificial material for an integrated circuit air gap dielectric. The method of one embodiment comprises forming a first and second metal interconnect lines on a substrate, wherein at least a portion of the first and second metal interconnect lines extend parallel to one another and wherein a trough is located between the parallel portion of said first and second metal interconnect lines. A layer of bismaleimide is spin coated over the substrate. The layer of bismaleimide is polished with a chemical mechanical polish, wherein the trough remains filled with the bismaleimide. A diffusion layer is formed over the substrate. The substrate is heated to activate a pyrolysis of the bismaleimide. An air gap is formed in the trough in the space vacated by the bismaleimide.

Abstract: An interconnect arrangement (100) has a first layer (101), a first layer surface (102), thereon at least two interconnects (104) having a second layer surface (105) essentially parallel to the first layer surface (102), thereon a respective second layer (106) for each interconnect (104), the second layers (106) of adjacent interconnects covering regions between the adjacent interconnects (104), and thereon a third layer (107), which completely closes off the regions between the adjacent interconnects (104) by means of coverage.

Abstract: A method of producing a contact structure for establishing electrical connection with contact targets. The contact structure is formed of a contactor carrier and a plurality of contactors. The contactor has an upper end oriented in a vertical direction, a straight beam portion oriented in a direction opposite to the upper end and having a lower end which functions as a contact point for electrical connection with a contact target, a return portion returned from the lower end and running in parallel with the straight beam portion to create a predetermined gap therebetween, a diagonal beam portion provided between the upper end and the straight beam portion to function as a spring.

Abstract: The present invention provides a method of manufacturing an electronic device provided with metal regions, that are mutually separated by air spaces. In the method a first isolating layer, a seed layer and a second isolating layer are provided before applying metal regions. The seed layer and the second isolating layer are only removed after the provision of the metal regions. The method can be advantageously applied for the manufacture of a multilevel interconnect structure and for the manufacture of micro-electromechanical elements.

Abstract: The semiconductor device comprises an interconnection layer 14 formed on a substrate 10, a cap insulation film 22 formed on the upper surface of the interconnection layer 14, and a sidewall insulation film which is formed on the side walls of the interconnection layer 14 and the cap insulation film 22 and which includes a larger layer number of insulation films 24, 26 28 covering the side wall of the interconnection layer 14 at the side wall of the cap insulation film 22 than a layer number of insulation films 24, 26 at the side wall of the cap insulation film 22. Accordingly, the sidewall insulation film can be thickened at the side wall of the interconnection layer 14, whereby a parasitic capacitance between the interconnection layer 14 and the electrodes 32 adjacent to the interconnection layer 14 through the sidewall insulation film can be low.

Abstract: An interlayer insulation film (31) on a plug (11) is etched using a silicon nitride film (32) used in pattern etching of a bit line (12) as a hard mask such that the plug (11) projects into a groove (40). Another silicon nitride film (33) is provided to cover an exposed surface of the groove (40), the bit line (12) and the silicon nitride film (32), thereby forming another interlayer insulation film (34) on the silicon nitride film (33) to fill the groove (40). The silicon nitride films (33, 32) are used as an etching stopper to etch the interlayer insulation film (34) above the plug (11). The silicon nitride film (33) on the plug (11) is etched to expose the plug (11) into a recess.

Abstract: A low-k dielectric sacrificial material is formed within a microelectronic structure covered with a suitable porous or low density permeable material. At an appropriate time, the underlying sacrificial material is decomposed and diffused away through the overlying permeable material. As a result, at least one void is created, contributing to desirable dielectric characteristics.

Abstract: A low-k dielectric sacrificial material is formed within a microelectronic structure covered with a layer defining an exhaust vent. At an appropriate time, the underlying sacrificial material is decomposed and exhausted away through the exhaust vent. Residue from the exhausted sacrificial material accumulates at the vent location during exhaustion until the vent is substantially occluded. As a result, an air gap is created having desirable characteristics as a dielectric.

Abstract: A monolithically integrated, electromechanical microwave switch, capable of handling signals from DC to millimeter-wave frequencies, and an integrated electromechanical tunable capacitor are described. Both electromechanical devices include movable beams actuated either by thermo-mechanical or by electrostatic forces. The devices are fabricated directly on finished silicon-based integrated circuit wafers, such as CMOS, BiCMOS or bipolar wafers. The movable beams are formed by selectively removing the supporting silicon underneath the thin films available in a silicon-based integrated circuit technology, which incorporates at least one polysilicon layer and two metallization layers. A cavity and a thick, low-loss metallization are used to form an electrode above the movable beam. A thick mechanical support layer is formed on regions where the cavity is located, or substrate is bulk-micro-machined, i.e., etched.

Abstract: An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure and formation method can be utilized in conjunction with a tungsten plug process. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.

Abstract: An ultraviolet sensitive material may be formed within a semiconductor structure covered with a suitable hard mask. At an appropriate time, the underlying ultraviolet sensitive material may be exposed to ultraviolet radiation, causing the material to exhaust through the overlying hard mask. As a result, an air gap may be created having desirable characteristics as a dielectric.

Abstract: A method for producing cavities, which are patterned in submicrometer dimensions, in a cavity layer of a semiconductor device, is described. In the method, a process liquid is frozen in the trenches in a process layer which has been patterned by ribs and trenches, then the process liquid is covered with a covering layer and is then expelled from the cavities resulting from the covering of the trenches.

Abstract: In accordance with the objectives of the invention a new method is provided for creating air gaps in a layer of IMD. First and second layers of dielectric are successively deposited over a surface; the surface contains metal lines running in an Y-direction. Trenches are etched in the first and second layer of dielectric in an X and Y-direction respectively. The trenches are filled with a layer of nitride and polished. A thin layer of oxide is deposited over the surface of the second layer of dielectric. Openings are created through the thin layer of oxide that align with the points of intersect of the nitride in the trenches in the layers of dielectric. The nitride is removed from the trenches by a wet etch, thereby opening trenches in the layers of dielectric with both sets of trenches being interconnected. The openings in the thin layer of oxide are closed, leaving a network of trenches containing air in the two layers of dielectric.

Abstract: The semiconductor structure has an interconnect that is isolated by a cavity from an underlying insulating layer on a support. The fabrication method provides for the interconnect firstly to be patterned on a double layer and to be provided with an insulating covering. Then, an opening is etched into the insulating covering, and the lower conductive layer is selectively removed. As a result, one the one hand, low-capacitance wiring can be fabricated and, on the other hand, this enables MOS transistors to be programmed in a simple manner.