Abstract: An interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.

Abstract: A method for forming a empty area under a layer of a given material, including forming on a substrate a stacking of a photosensitive layer and of a layer of the given material; insolating a portion of the photosensitive layer or its complement according to whether the photosensitive layer is positive or negative with an electron beam crossing the layer of the given material; and removing the portion of the photosensitive layer.

Abstract: Circuit edits may be performed through the back side of an integrated circuit die. In one embodiment, a circuit edit is achieved by exposing first and second circuit edit connection targets through a semiconductor substrate of the integrated circuit die from the back side. An insulating layer is not deposited over the first and second circuit edit connection targets and the exposed semiconductor substrate. Next, a conductor is deposited over the circuit edit connection targets from the back side of the integrated circuit to couple together the circuit edit connection targets.

Abstract: A process for fabricating an integrated electronic circuit comprises the formation of at least one air gap between interconnect elements above only a defined portion of a surface of a substrate, within an interconnect layer. The interconnect layer comprises a sacrificial material and extends beneath an intermediate layer of permeable material. The air gap is formed by removal, through the intermediate layer, of at least part of the sacrificial material by bringing the permeable material into contact with an agent for removing the sacrificial material, to which agent the permeable material is resistant.

Abstract: In a semiconductor device, a wiring pattern groove is formed in a surface portion of a silicon oxide film provided above a semiconductor substrate. A wiring layer is buried into the wiring pattern groove with a barrier metal film interposed therebetween. The barrier metal film is selectively removed from each sidewall portion of the wiring pattern groove. In other words, the barrier metal film is left only on the bottom of the wiring pattern groove. Thus, a damascene wiring layer having a hollow section whose dielectric constant is low between each sidewall of the wiring pattern groove and each side of the wiring layer can be formed in the semiconductor device.

Abstract: A multi-layered wire structure includes a substrate, a plurality of first conductive lines formed in a first layer over the substrate extending in parallel to each other in a first direction, a plurality of second conductive lines formed in a second layer over the first layer extending in parallel to each other in a second direction orthogonal to the first direction, a plurality of sets of third conductive lines formed in the second layer extending in the first direction, each set of third conductive lines corresponding to one of the first conductive lines, and a plurality of sets of conductive paths formed between the first layer and the second layer, each set of conductive paths corresponding to one of the first conductive lines and one set of third conductive lines and electrically connecting the corresponding first conductive line to the corresponding set of third conductive lines.

Abstract: An air gap structure and formation method for substantially reducing the undesired capacitance between adjacent interconnects, metal lines or other features in an integrated circuit device is disclosed. The air gap extends above, and may also additionally extend below, the interconnects desired to be isolated thus minimizing fringing fields between the lines. The integrated air gap structure and formation method can be utilized in conjunction with a tungsten plug process. Also, multiple levels of the integrated air gap structure can be fabricated to accommodate multiple metal levels while always ensuring that physical dielectric layer support is provided to the device structure underlying the interconnects.

Abstract: Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure. One embodiment includes a solid structure of an insulator material, and a precisely determined arrangement of at least one void formed within the solid structure which lowers an effective dielectric constant of the insulator structure. One aspect is a method of forming a low-k insulator structure. In one embodiment, an insulator material is deposited, and a predetermined arrangement of at least one hole is formed in a surface of the insulator material. The insulator material is annealed such that the low-k dielectric material undergoes a surface transformation to transform the arrangement of at least one hole into predetermined arrangement of at least one empty space below the surface of the insulator material. Other aspects are provided herein.

Abstract: The semiconductor device of the present invention comprises a substrate; at least one through hole formed through the substrate between front and back surfaces of the substrate; an electrical connection portion formed by a semiconductor process on at least one surface of the front and back surfaces of the substrate in a vicinity of an end opening of the through hole; an insulating layer formed of an organic material on an inside surface of the through hole; and an electroconductive layer formed on an inside surface of the insulating layer, wherein the electrical connection portion is electrically connected to the electroconductive layer to be electrically connected to a side of the other surface of the substrate.

Abstract: Methods of forming air gaps or porous dielectric materials between interconnects of integrated circuits and structures thereof. Air gaps or highly porous dielectric material having a dielectric constant of close to or equal to 1.0 are formed in a first region but not a second region of an interconnect layer. The air gaps or highly porous dielectric material are formed by depositing a first insulating material comprising an energy-sensitive material over a workpiece, depositing a second insulating material over the first insulating material, and exposing the workpiece to energy. At least a portion of the first insulating material in the first region is removed through the second insulating material. Structurally stable insulating material is disposed between conductive lines in the second region of the workpiece, providing mechanical strength for the integrated circuit.

Abstract: The invention provides a new multilevel interconnect structure of air gaps in a layer of IMD. A first layer of dielectric is provided over a surface; the surface contains metal points of contact. Trenches are provided in this first layer of dielectric. The trenches are filled with a first layer of nitride or disposable solid and polished. A second layer of dielectric is deposited over the first layer of dielectric. Trenches are formed in the second layer of dielectric, a second layer of nitride or disposable solid is deposited over the second layer of dielectric. The layer of nitride or disposable solid is polished. A thin layer of oxide is deposited over the surface of the second layer of dielectric. The thin layer of oxide is masked and etched thereby creating openings in this thin layer of oxide, these openings align with the points of intersect of the trenches in the first layer of dielectric and in the second layer of dielectric. The nitride or removable solid is removed from the trenches.

Abstract: Methods for fabricating interconnect structures implementing air gaps therein is provided. In one embodiment, a semiconductor substrate with a first barrier layer formed thereon is provided. A first dielectric layer is formed above the barrier layer. The first dielectric layer is thereafter patterned and etched to form a plurality of stakes having first openings therebetween, the plurality of stakes for providing mechanical supporting strength for the interconnect structure. A sacrificial layer is formed in the first openings and above the plurality of stakes. A hard mask layer is formed above the sacrificial layer. A light sensitive layer is formed over the hard mask layer and is thereafter patterned to define a pattern therein. The hard mask layer, the sacrificial layer, and the first barrier layer are etched according to the pattern in the light sensitive layer to form second openings. The second openings are filled with a conductive material to form metal lines.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a porous insulating film formed above the semiconductor substrate, the porous insulating film having a relative dielectric constant of 2.5 or less and including a first insulating material, at least a portion of pores in the porous insulating film having on the inner wall thereof a layer of a second insulating material which differs in nature from the first insulating material, and a plug and/or a wiring layer buried in the porous insulating film.

Abstract: A structure and method of a semiconductor device with liner air gaps next to interconnects and dielectric layers. A dielectric layer is formed over a lower dielectric layer and a lower interconnect over a substrate. We form an interconnect opening in the dielectric layer. The opening has sidewalls of the dielectric layer. A sacrificial liner is formed over the sidewalls of the interconnect opening. An upper interconnect is formed that fills the opening. We remove the sacrificial liner/spacers to form (air) liner gaps.

Abstract: An improved electrical interconnect for an integrated circuit and methods for providing the same are disclosed. The electrical interconnect includes an air bridge extending through a gaseous medium so as to reduce the capacitance of the interconnect. The air bridge is supported at a first and second end such that the air bridge is suspended above the substrate. The air bridge comprises a highly conductive material, such as silver, so as to provide the air bridge with a reduced resistivity. To inhibit gaseous medium from contaminating the air bridge, the air bridge further comprises an adherent coating interposed between the air bridge and the gaseous medium. A method of forming the electrical interconnect is also disclosed, wherein, prior to forming the adherent coating, the conductive material is processed so as to form fewer grain boundaries, which enhances the electrical properties of the air bridge.

Abstract: A method for fabricating micro pipes on a semiconductor wafer or other substrate. According to the method of the invention, a base layer is initially deposited on the substrate and then etched to form a trench which exposes the surface of the substrate. Next, a PR (photoresist) layer of selected thickness is deposited over the base layer and the trench. Finally, in a curing step, the deposited photoresist is irradiated with ionizing radiation to cause outgassing of nitrogen gas from the photoresist layer, between the PR layer and the substrate. This step facilitates buckling of the PR layer into an arcuate bubble which defines the semispherical micro pipe structure.

Abstract: Structures and methods are provided for an improved multilevel wiring interconnect in an integrated circuit assembly. The present invention provides for a multilayer copper wiring structure by electroless, selectively deposited copper in a streamlined process which further reduces both intra-level line to line capacitance and the inter-level capacitance. In particular, an illustrative embodiment of the present invention includes a novel methodology for forming multilevel wiring interconnects in an integrated circuit assembly. The method includes forming a number of multilayer metal lines, e.g. copper lines formed by selective electroless plating, separated by air gaps above a substrate. A low dielectric constant material is deposited between the number of metal lines and the substrate using a directional process. According to the teachings of the present invention, using a directional process includes maintaining a number of air gaps in the low dielectric constant material.

Abstract: A method of forming a semiconductor device, and the device so formed. Depositing alternating layers of a first and a second dielectric material, wherein the first and second dielectric materials are selectively etchable at different rates. Forming a first feature within the alternating layers of dielectric material. Selectively etching the alternating layers of dielectric material to remove at least a portion of the first dielectric material in each layer having the first dielectric material and leaving the second dielectric material as essentially unetched.

Abstract: The present invention provides a semiconductor device in which a problem such as a thermal diffusion defect in a hollow wiring technique can be solved. In the semiconductor device, a gap is formed between wirings formed on a substrate, and the gap is filled with a gas having a thermal conductivity equal to or higher than three times that of air at 0° C.

Abstract: A method of forming air gaps surrounding conductors in a dielectric layer, the dielectric layer comprising, for example, part of the interconnect structure of an integrated circuit device. The air gaps are formed, in part, by depositing a sacrificial material within a trench and/or via that have been formed in a dielectric layer, and the sacrificial material is ultimately removed after metal deposition to create the air gaps. A porous dielectric cap may be deposited over the dielectric layer, and the sacrificial material may be removed through this porous dielectric layer. Other embodiments are described and claimed.

Abstract: An adjustable self aligned low capacitance integrated circuit air gap structure comprises a first interconnect adjacent a second interconnect on an interconnect level, spacers formed along adjacent sides of the first and second interconnects, and an air gap formed between the first and second interconnects. The air gap extends above an upper surface of at least one of the first and second interconnects and below a lower surface of at least one of the first and second interconnects, and the distance between the spacers defines the width of the air gap. The air gap is self-aligned to the adjacent sides of the first and second interconnects.

Abstract: Structures and methods provide multilevel wiring interconnects in an integrated circuit assembly which alleviate problems associated with integrated circuit size and performance and include methods for forming multilevel wiring interconnects in an integrated circuit assembly, e.g., forming multilayer metal lines separated by a number of air gaps above a substrate. A silicide layer is formed on the multilayer metal lines, then oxidized. An insulator is deposited to fill interstices created by air gaps between the multilayer metal lines. In one embodiment, forming multilayer metal lines includes a conductor bridge level. In one embodiment, forming a silicide layer on the multilayer metal lines includes using a pyrolysis of silane at a temperature of between 300-500 degrees Celsius. In one embodiment, a metal layer is formed on the oxided silicide layer. The metal layer includes one of Aluminum, Chromium, Titanium, Zirconium and Aluminum oxide.

Abstract: A reliable microchip controller board and a manufacturing method thereof suitable for mass production are provided. A board wherein a programmable microchip controller is mounted includes; terminals for writing a program into the microchip controller and a circuit pattern connecting an operating terminal to shared terminals which are disconnected. A non-programmed microchip controller is mounted on the board in a state where patterns are disconnected and then programmed. The disconnected portion is connected thereafter.

Abstract: An interconnect structure and fabrication method are provided to form air gaps between interconnect lines and between interconnect layers. A conductive material is deposited and patterned to form a first level of interconnect lines. A first dielectric layer is deposited over the first level of interconnect lines. One or more air gaps are formed in the first dielectric layer to reduce inter-layer capacitance, intra-layer capacitance or both inter-layer and intra-layer capacitance. At least one support pillar remains in the first dielectric layer to promote mechanical strength and thermal conductivity. A sealing layer is deposited over the first insulative layer to seal the air gaps. Via holes are patterned and etched through the sealing layer and the first dielectric layer. A conductive material is deposited to fill the via holes and form conductive plugs therein. Thereafter, a conductive material is deposited and patterned to form a second level of interconnect lines.

Abstract: Methods for producing waveguides are disclosed. In one embodiment, a waveguide is produced by depositing a first metal layer on a substrate, depositing a sacrificial material on the first metal layer, depositing a second metal layer on the sacrificial material, the second metal layer contacting the first metal layer and defining therebetween a cavity for the waveguide, the cavity filled with the sacrificial material, and removing the sacrificial material.

Abstract: A method of combining components to form an integrated device, wherein at least one first component is provided on a first surface of a sacrificial substrate, and at least one second component is provided on a first surface of a non-sacrificial substrate. At least one support structure is formed on at least one of the first surfaces of the sacrificial substrate, and the non-sacrificial substrate, respectively, such that said at least one support structure is extended outwardly from at least one of the first surfaces. The sacrificial substrate carrying the first component, and the non-sacrificial substrate carrying the second component, respectively, are bonded, so that the first and second surfaces will be facing one another with a distance defined by a thickness of the support structure. At least a part of the sacrificial substrate is removed. The first component and second components are interconnected.

Abstract: A process forms an integrated device having: a first conductive region; a second conductive region; an insulating layer arranged between the first and the second conductive region; at least one through opening extending in the insulating layer between the first and the second conductive region; and a contact structure formed in the through opening and electrically connecting the first conductive region and the second conductive region. The contact structure is formed by a conductive material layer that coats the side surface and the bottom of the through opening and surrounds an empty region which is closed at the top by the second conductive region. The conductive material layer preferably comprises a titanium layer and a titanium-nitride layer arranged on top of one another.

Abstract: An improved electrical interconnect for an integrated circuit and methods for providing the same are disclosed. The electrical interconnect includes an air bridge extending through a gaseous medium so as to reduce the capacitance of the interconnect. The air bridge is supported at a first and second end such that the air bridge is suspended above the substrate. The air bridge comprises a highly conductive material, such as silver, so as to provide the air bridge with a reduced resistivity. To inhibit gaseous medium from contaminating the air bridge, the air bridge further comprises an adherent coating interposed between the air bridge and the gaseous medium. A method of forming the electrical interconnect is also disclosed, wherein, prior to forming the adherent coating, the conductive material is processed so as to form fewer grain boundaries, which enhances the electrical properties of the air bridge.

Abstract: A method of forming a cavity between metallic wirings using a polymer capable of revealing a specific heat resistant temperature and a specific heat decomposition temperature by having a specific repeating unit structure and a specific molecular weight range and of readily forming a cavity structure between metallic wirings in, for example, semiconductors. The method comprises a step of coating the surface of a first dielectric film formed on a semiconductor substrate with a cyclic olefin based addition polymer, a step of patterning the cyclic olefin based addition polymer as a void-forming polymer, a step of forming a metallic wiring in the pattern formed on the void-forming polymer, a step of forming a second dielectric film on the void-forming polymer containing a metallic wiring, and a step of removing the void-forming polymer between the multilayered wirings by heating to form a cavity between the metallic wirings.

Abstract: A dual layer of polymeric material is deposited with a base layer and top layer resist onto an integrated circuit structure with topography. The base layer planarizes the surface and fills in the native topography. The base layer decomposes almost completely when exposed to an oxidizing environment. The top layer contains a high composition of oxidizing elements and is photosensitive. (i.e., the layer can be patterned by exposing normal lithographic techniques.) The patterning allows the creation of escape paths for the decomposition products of the underlying base layer. This structure is decomposed in an oxidizing ambient (or plasma) leaving behind a thin carbon-containing membrane. This membrane layer blocks deposition of future layers, creating air gaps in the structure.

Abstract: A component having an airdome enclosure that protects the component from its external environment. An airdome enclosure according to the present techniques avoids the high costs of employing special materials and/or specialized process steps in the manufacture of a component. An electronic component according to the present techniques includes a set of substructures formed on a substrate and an airdome enclosure over the substructures that protects the substructures and that hinders the formation of parasitic capacitances among the substructures.

Abstract: In semiconductor devices which include an insulated trench electrode (11) in a trench (20), for example, trench-gate field effect power transistors and trenched Schottky diodes, a cavity (23) is provided between the bottom (25) of the trench electrode (11) and the bottom (27) of the trench (20) to reduce the dielectric coupling between the trench electrode (11) and the body portion at the bottom (27) of the trench in a compact manner. In power transistors, the reduction in dielectric coupling reduces switching power losses, and in Schottky diodes, it enables the trench width to be reduced.

Abstract: Method for forming intermetal dielectric layer is disclosed including steps of: preparing a substrate with wiring on a lower insulating layer, the wiring having a plurality of separating portions; forming first and second water marks on the lower insulating layer located in the separating portions and on upper surfaces of the wiring; transforming the first and second water marks into first and second air bubbles, respectively; depositing a first insulating layer of lower dielectric constant on the whole surface of the substrate, and at the same time, forming first and second air gaps by growing said first and second air bubbles on and between the wirings, respectively; removing the upper portion of the first insulating layer to make open the second air gap; and depositing a second insulating layer of lower dielectric constant on the first insulating layer to fill the opened second air gap.

Abstract: In one embodiment, an interconnect line on one level of an integrated circuit is electrically coupled to another interconnect line on another level. The two layers of interconnects may be coupled together using a via. To reduce capacitance between the interconnect lines, an air core is formed between them. The air core may be formed by using a chemistry that includes a noble gas fluoride to etch a sacrificial layer between the interconnect layers.

Abstract: The present invention relates to a process for integrating air as dielectric in semiconductor devices, comprising the steps of: a. applying a layer of a dielectric (2) which is to be patterned to a substrate (1); b. patterning the dielectric layer (2) which has been applied; c. applying a conductor metal (3) for the patterned dielectric layer (2) and forming a common surface from the conductor metal (3) and the dielectric (2); d. applying a layer of an organic dielectric (4) to the layer produced in step c.; and e. bringing the coated substrate produced in this way into contact with a fluorine-containing compound in order to form an arrangement which has air as dielectric between conductor structures and has a continuous dielectric layer (4) on the top side, and to a semiconductor device with air layers as dielectric produced using this process.

Abstract: A method (and structure) that selectively forms a dielectric chamber on an electronic device by forming a dummy structure over a semiconductor substrate, depositing a dielectric layer over the dummy structure, forming an opening through the dielectric layer to the dummy structure, and removing the dummy structure to form the dielectric chamber.

Abstract: A method for forming a transmission line structure for a semiconductor device includes forming an interlevel dielectric layer over a first metallization level, removing a portion of the interlevel dielectric layer and forming a sacrificial material within one or more voids created by the removal of the portion of the interlevel dielectric layer. A signal transmission line is formed in a second metallization level formed over the interlevel dielectric layer, the signal transmission line being disposed over the sacrificial material. A portion of dielectric material included within the second metallization level is removed so as to expose the sacrificial material, wherein a portion of the sacrificial material is exposed through a plurality of access holes formed through the signal transmission line. The sacrificial material is removed so as to create an air gap beneath the signal transmission line.

Abstract: Porous thermoset dielectric materials having low dielectric constants useful in electronic component manufacture are provided along with methods of preparing the porous thermoset dielectric materials. Also provided are methods of forming integrated circuits containing such porous thermoset dielectric material.

Abstract: The present invention relates to a method for forming an inductor being a passive device in RE MEMS, RFCMOS, Bipolor/SiGe, BiCMOS semiconductor devices. According to the present method, a lower photoresist layer, an intermediate anti-exposure layer and an upper photoresist layer are sequentially formed on a substrate having a lower electrode. The upper photoresist layer is patterned by means of an exposure and development process using a first mask. The exposed intermediate anti-exposure layer is etched until the lower photoresist layer is sufficiently exposed, thus forming a partial via hole. The lower photoresist layer exposed through the upper photoresist layer and the partial via hole are patterned by means of an exposure and development process using a second mask, thus forming a damascene pattern having trenches and a via hole. The damascene pattern is filled with a conductive material layer to form a copper inductor.

Abstract: Method and structure for integrating conductive and dielectric materials in a microelectronic structure having air gaps are disclosed. Certain embodiments of the invention comprise isolating dielectric layers from conductive layers using an etch stop layer to facilitate controlled removal of portions of the dielectric layers and formation of air gaps or voids. Capping and peripheral structural layers may be incorporated to increase the structural integrity of the integration subsequent to removal of sacrificial material.

Abstract: A damascene interconnect that reduces interconnect intra-layer capacitance and/or inter-layer capacitance is provided. The damascene interconnect structure has air gaps between metal lines and/or metal layers. The interconnect structure is fabricated to a via level through a processing step prior to forming contact vias, then one or more air gaps are formed into the damascene structure so that the air gaps are positioned between selected metal lines. A sealing layer is then deposited over the damascene structure to seal the air gaps.

Abstract: A method of forming a variable contact structure, and the structure so formed, comprising forming a via within the device, wherein a diameter of the via is variably determined depending upon the number of wires to be contacted.

Abstract: A method for manufacturing a semiconductor device includes: (i) depositing a sacrificial layer made of an organic polymer such as benzocyclobutene on a substrate having a circuit formed thereon; (ii) etching the sacrificial layer except for a portion where air gaps are to be formed; (iii) depositing a low-dielectric layer over the substrate until the portion for air gaps is entirely enclosed in the low-dielectric layer; (iv) etching the low-dielectric layer to form via holes and trenches there through; (v) prior or subsequent to step (iv), removing the portion for air gaps; and (vi) depositing copper in the vias and trenches which are filled with the copper contacting a surface of the substrate.

Abstract: A method for forming at least one conductive line intended to receive high-frequency or high-value currents, formed above a given portion of a solid substrate outside of which are formed other elements, including the steps of digging at least one trench in the solid substrate; forming an insulating area in the trench; and forming said conductive line above the insulating area.

Abstract: A method of forming at least a partial air gap within a semiconducting device and the resulting devices, said method comprising the steps of: (a) depositing a sacrificial polymeric composition in one or more layers of the device during its formation; (b) coating the device with one or more layers of a relatively non-porous, organic, polymeric, insulating dielectric material (hardmask) having a density less than 2.2 g/cm3; and (c) decomposing the sacrificial polymeric composition such that the decomposition products permeate at least partially through the one or more hardmask layers, thereby forming at least a partial air gap within the device.

Abstract: The present invention is directed to a structure comprised of alternating layers of metal and sacrificial material built up using standard CMOS processing techniques, a process for building such a structure, a process for fabricating devices from such a structure, and the devices fabricated from such a structure. In one embodiment, a first metal layer is carried by a substrate. A first sacrificial layer is carried by the first metal layer. A second metal layer is carried by the sacrificial layer. The second metal layer has a portion forming a micro-machined metal mesh. When the portion of the first sacrificial layer in the area of the micro-machined metal mesh is removed, the micro-machined metal mesh is released and suspended above the first metal layer a height determined by the thickness of the first sacrificial layer. The structure may be varied by providing a base layer of sacrificial material between the surface of the substrate and the first metal layer.

Abstract: In a method for producing a protective cover for a device which is formed in a substrate, a first cover layer is initially deposited on the substrate, the first cover layer covering an area of the substrate which includes the device. Subsequently, an opening is formed in the first cover layer, the opening exposing that area of the substrate which includes the device. Then the opening formed in the first cover layer is filled up using a filling material. Subsequently, a second cover layer is deposited on the first cover layer and in the opening of the first cover layer which is filled up with the filling material. Thereafter, an opening is formed in the second cover layer to expose an area of the filling material. Finally, the filling material covering that area of the substrate which includes the device is removed, and the opening formed in the second cover layer is closed.

Abstract: An interconnect is formed on the substrate. The conductive structure at least includes a first conductive structure and a second conductive structure, which have a gap region in-between. The substrate is exposed at the gap region. A first structured dielectric layer is formed over the substrate to cover the first and the second conductive structures. The first structured dielectric layer also has a void at the gap region between the first and the second conductive structures. The void significantly extends to the whole gap region. The first structured dielectric layer also has an indent region above the void. An anti-etch layer fills the indent region of the first structured dielectric layer. As a result, the first structured dielectric layer has a substantially planar surface. A second structured dielectric layer is formed on the first structured dielectric layer and the anti-etch layer.

Abstract: A method for fabricating low k and ultra-low k multilayer interconnect structures on a substrate includes: a set of interconnects separated laterally by air gaps; forming a support layer in the via level of a dual damascene structure that is only under the metal line; removing a sacrificial dielectric through a perforated bridge layer that connects the top surfaces of the interconnects laterally; performing multilevel extraction of a sacrificial layer; sealing the bridge in a controlled manner; and decreasing the effective dielectric constant of a membrane by perforating it using sub-optical lithography patterning techniques.

Abstract: A method of forming a semiconductor device to have a gap between wirings formed on a substrate, which gap is filled with a gas having a thermal conductivity equal to or higher than three times that of air at zero degrees Celsius. In the method, the following steps are performed: (A) forming a wiring and a filling layer filled between wirings, on a substrate; (B) forming a gas permeable film on the wiring and the filling layer; (C) removing the filling layer through the gas permeable film so as to form a gap between the wirings; (D) filling a gas having a thermal conductivity equal to or higher than three times that of air at 0.degree. C. through the gas permeable film into the gap; and (E) forming a gas impermeable film on the gas permeable film.