Abstract: Method for producing a metal silicon (oxy)nitride by introducing a carbon-free silicon source (for example, (SiH3)3N), a metal precursor with the general formula MXn (for example, Hf(NEt2)4), and an oxidizing agent (for example, O2) into a CVD chamber and reacting same at the surface of a substrate. MsiN, MSIo and/or MSiON films may be obtained. These films are useful are useful as high k dielectrics films.

Abstract: An interconnect structure with a plurality of low dielectric constant insulating layers acting as etch stops is disclosed. The low dielectric constant materials act as insulating layers through which trenches and vias are subsequently formed by employing a timed etching. Since the low dielectric constant materials are selected so that the etchant available for each one has only a small etch rate relative to the other low dielectric constant materials, the plurality of low dielectric constant materials act as etch stops during the fabrication of interconnect structures. This way, the etch stop layers employed in the prior art are eliminated and the number of fabrication steps is reduced.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: A method for forming, by dry etch, an opening of a given shape in a silica glass layer, the layer having a doping profile similar to the shape and the etch plasma being a non-carbonated fluorinated plasma causing a non-directional etching.

Abstract: In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.

Abstract: Organic polymers for use in electronic devices, wherein the polymer includes repeat units of the formula: wherein: each R1 is independently H, an aryl group, Cl, Br, I, or an organic group that includes a crosslinkable group; each R2 is independently H, an aryl group or R4; each R3 is independently H or methyl; each R5 is independently an alkyl group, a halogen, or R4; each R4 is independently an organic group that includes at least one CN group and has a molecular weight of about 30 to about 200 per CN group; and n=0-3; with the proviso that at least one repeat unit in the polymer includes an R4. These polymers are useful in electronic devices such as organic thin film transistors.

Abstract: A method of fabricating an organic EL device by which sealing films can be patterned, without using any wet process. The method has the steps of: preparing a substrate 1 on which a first electrode 2 has been formed and forming a laminated film 7 by laminating an organic layer 3 comprising a luminescent layer and a second electrode 4 on the first electrode 2 in this order; forming a first sealing film 5 which covers the whole region of the laminated film 7; forming on the surface of the first sealing film 5 a second sealing film 6 having an opening pattern; and patterning the first sealing film 5 by dry-etching the first sealing film 5 using the second sealing film 6 having the opening pattern as a mask.

Abstract: A method for manufacturing a dual damascene structure includes forming a wiring layer over a substrate, forming an inorganic insulating film over the wiring layer, forming a via hole in the inorganic insulating film using a first resist pattern with an opening as an etching mask, removing the first resist pattern, forming an organic insulating film on the inorganic insulating film and in the via hole, forming a hard mask on the organic insulating film, forming a hard mask pattern using a second resist pattern with an opening on the hard mask as an etching mask, forming a wiring groove by etching the organic insulating film using the second resist pattern and the hard mask pattern as etching masks until the organic insulating film inside the via hole is eliminated and simultaneously eliminating the second resist pattern, and implanting a conductive substance into the via hole and wiring groove.

Abstract: A method of forming an interconnect joint includes providing a first metal layer (210, 310), providing a film (220, 320) including metal particles (221, 321) and organic molecules (222, 322), placing the film over the first metal layer, placing a second metal layer (230, 330) over the film, and sintering the metal particles such that the organic molecules degrade and the first metal layer and the second metal layer are joined together.

Abstract: A method of forming a dual-damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using the tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth.

Abstract: A method for forming a via, comprising (a) providing a structure comprising a mask (210) disposed on a semiconductor substrate (203), wherein the structure has an opening (215) defined therein which extends through the mask and into the substrate, and wherein the mask comprises a first electrically conductive layer; (b) depositing a second electrically conductive layer (219) such that the second conductive layer is in electrical contact with the first conductive layer, the second conductive layer having a first portion which extends over the surfaces of the opening and a second portion which extends over a portion of the mask adjacent to the opening; (c) removing the second portion of the second conductive layer; and (d) depositing a first metal (221) over the first portion of the second conductive layer.

Abstract: A highly reliable method for forming contact plugs is provided. The method can prevent short circuiting from occurring between self aligned contact plugs and word lines or between self aligned contact plugs and bit lines by applying a material, whose etching speed ratio relative to that of the silicon-based insulating film is 100 or more, to an interlayer film for forming the contact plugs therein. The method comprises forming wiring lines each of which is covered with silicon oxide films at its top surface and lateral sides, forming a sacrificial interlayer film overall, which is made up of an organic coating film without containing silicon, so as to cover the wiring lines, forming contact holes by sequentially etching the sacrificial interlayer film and a lower-layer insulating film, and forming contact plugs.

Abstract: A multi-layer circuit substrate and method having improved transmission line integrity and increased routing density uses a selectively applied transmission line reference plane metal layer to achieve signal path shielding and isolation, while avoiding drops in impedance due to capacitance between large diameter vias and the transmission line reference plane metal layer. The transmission line reference plane defines voids above (or below) the signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. For voltage-plane bearing PTHs, no voids are introduced, so that signal path conductors can be routed above or adjacent to the voltage-plane bearing PTHs, with the transmission line reference plane preventing shunt capacitance between the signal path conductors and the PTHs.

Abstract: A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a depth. The method additionally includes forming a liner within the trench, the liner lining the sidewalls and bottom of the trench. Furthermore, the method includes filling the trench to a first depth with a first oxide. The first oxide is filled using a spin-on process. The method also includes performing a first densification process on the first oxide within the trench. In addition, the method includes depositing a second oxide within the trench using an HDP process to fill at least the entirety of the trench. The method also includes performing a second densification process on the first and second oxides within the trench.

Abstract: A semiconductor device manufacturing method includes: forming a via pattern in an insulating film by use of an alignment mark of a lower wiring line; forming, by use of an alignment mark of the via pattern, an upper wiring groove pattern in an upper insulating film in which the via pattern is embedded; and repeating etching in a self-aligning manner to form a via and a wiring groove in an insulating film previously stacked under the insulating film in which the via pattern has been formed.

Abstract: When a via-hole 26 and an interconnection trench 32 are formed in an interconnection films 16, 18 by using as a mask a hard mask 20 covering the region except via-hole forming region, and a hard mask 22 covering the region except an interconnection trench forming region, the hard mask 20 is isotropically etched to expose the upper surface of the inter-layer insulating film 18 at a periphery of the via-hole forming region and leave the hard mask 20 in the interconnection trench forming region except the periphery, and then the hard mask 20 and the insulating films 18, 16 are anisotropically etched, whereby the via-hole 26 having increased-width portion 34 at the upper part, and the interconnection trench 32 connected to the via-hole 26 at the increased-width portions 26 are formed.

Abstract: Disclosed herein is a method of forming metal wirings for high voltage elements. According to the present invention, after a copper film is formed, a wet etch process using an interlayer insulating film as an etch mask is performed to pattern the copper film. It is thus possible to form copper wirings for high voltage elements the width of which is very wide. Furthermore, a wet etch process using a chemical aqueous solution is performed instead of a copper polishing process. The cost for forming a metal wiring can be thus saved. Moreover, by controlling a wet etch time, the space between metal wirings, which is narrower than a width of the metal wiring, can be secured sufficiently.

Abstract: It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a desired region can be etched by evenly applying a solution including a resist and a method for manufacturing a semiconductor device having a laminated structure by forming an interlayer insulating layer with an organic resin.

Abstract: A method is provided for fabricating current-carrying formation on substrates. The method includes providing a substrate including a layer of a voltage switchable dielectric material, forming a mask over the layer of the voltage switchable dielectric material, and forming an electrically conductive layer. The mask includes gaps and the electrically conductive layer is formed in the gaps. The voltage switchable dielectric material has a characteristic voltage and the electrically conductive layer is formed by applying a voltage in excess of the characteristic voltage to the substrate and depositing the electrically conductive material through an electrochemical process such as electroplating.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: A method for forming arrays of metal, alloy, semiconductor or magnetic clusters is described. The method comprises placing a scaffold on a substrate, the scaffold comprising, for example, polynucleotides and/or polypeptides, and coupling the clusters to the scaffold. Methods of producing arrays in predetermined patterns and electronic devices that incorporate such patterned arrays are also described.

Abstract: A method for healing detrimental bonds in deposited materials, for example porous, low-k dielectric materials, including oxydatively processing a deposited material, processing the deposited material with a trialkyl group III compound, and processing in the presence of an alcohol. Also included in embodiments of the invention are materials with bonds healed by embodiments of the claimed method.

Abstract: A silicon condenser microphone package includes a transducer unit, a substrate, and a cover. The substrate includes an upper surface transducer unit is attached to the upper surface of the substrate and overlaps at least a portion of the recess wherein a back volume of the transducer unit is formed between the transducer unit and the substrate. The cover is placed over the transducer unit and either the cover or the substrate includes an aperture.

Abstract: A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect near the via.

Abstract: Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05?v?0.8, 0?w?0.9, 0.05?x?0.8, O?y?0.3, 0.05?z?0.8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

Abstract: An organic silicon film is formed by carrying out chemical vapor deposition with organic silicon compound being used as a raw material gas. The organic silicon compound contains at least silicon, hydrogen and carbon as a constituent thereof, and contains two or more groups having unsaturated bond, per a molecule thereof. The organic silicon compound is used in mixture with a silicon hydride gas.

Abstract: Disclosed is a method of manufacturing a semiconductor device comprising forming an insulating film above a substrate, forming a recess in the insulating film, successively forming an underlying layer, an immediate layer and a resist film above the insulating film having the recess formed thereon, the underlying layer being formed by a process comprising forming a first organic film above the insulating film, chemically mechanically polishing the first organic film to expose a surface of the insulating film and to remain the first organic film selectively in the recess, and forming a second organic film above the insulating film and above the first organic film, and subjecting the resist film to patterning exposure.

Abstract: A method of forming a pre-patterned high-k dielectric film onto a support layer. The method includes: providing a support layer; providing a template defining template openings therein exhibiting a pattern that is a mirror image of a pattern of the pre-patterned high-k dielectric film; disposing the template onto the support layer; providing a high-k precursor material inside the template openings; curing the high-k precursor material inside the template openings to yield a cured film; and removing the template from the support layer after curing to leave the cured film on the conductive film.

Abstract: A method for manufacturing a semiconductor device includes: preparing a substrate in which a first interlayer insulation layer having a first via hole and a first trench is formed; forming a first via plug and a first metal line by filling the first via hole and the first trench with a first metal; planarizing the first metal line and the first interlayer insulation layer; forming a second interlayer insulation layer on the first metal line and the first interlayer insulation layer; planarizing the second interlayer insulation layer; forming a second via hole and a second trench in the second interlayer insulation layer; forming a second via plug and a second metal line by filling the second via hole and the second trench with a second metal; and planarizing the second metal line and the second interlayer insulation layer.

Abstract: A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further comprising a conductive layer over the surface and in the contact. Next, in the chamber, a layer of etch resistant material is formed within the contact over the conductive layer, the etch resistant material not forming over the surface.

Abstract: The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11 in which the plug is embedded, insulating films 14, 15, 16 are formed and an opening is formed in the insulating films 14, 15, 16 and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 in order to form the opening, containing silicon and carbon. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance, however, by interposing the insulating film 14 therebetween and making the insulating film 14 have a higher density of the number of Si (silicon) atoms than that of the insulating film 11, an electrically weak interface is prevented from being formed.

Abstract: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A process for producing a layer arrangement, in which a plurality of electrically conductive structures are formed on a substrate, a first electrically insulating layer is formed on the plurality of electrically conductive structures, in such a manner than trenches are formed between mutually adjacent regions of the first electrically insulating layer, electrically insulating structures are formed in the trenches between the adjacent regions of the first electrically insulating layer, material of the first electrically insulating layer is removed, so that airgaps are formed between the electrically insulating structures and the electrically conductive structures, and a second electrically insulating layer is formed on the electrically conductive structures and on the electrically insulating structures, in such a manner that the second electrically insulating layer spans adjacent electrically conductive structures and electrically insulating structures.

Abstract: A method is provided for making an inter-level dielectric for a microelectronic device formed on a substrate. The method begins by forming first and second spacer layers over a substrate layer. The spacer layers are formed from a sacrificial dielectric material. Next, first and second dielectric layers are formed on the first and second spacer layers, respectively, such that each of the first and second dielectric layers is separated by one of the spacer layers. The first and second dielectric layers each include a first and second dielectric component. The second dielectric component is a sacrificial dielectric material. At least a portion of the second dielectric component is removed to thereby form voids in the first and second dielectric layers. At least a portion of the sacrificial dielectric material in the first and second spacer layers is also removed to thereby form voids in the first and/or second spacer layers.

Abstract: In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.

Abstract: A display substrate includes a base substrate having a display area and a peripheral area which surrounds the display area, a pixel electrode formed on the display area, a pad part formed on the peripheral area, an adhesion part formed on the peripheral area and having a plurality of holes formed in an area adjacent to the pad part on the peripheral area and a conductive adhesion member formed on the pad part and the adhesion part to make electrical contact with the pad part and a terminal of an integrated circuit.

Abstract: To provide an insulating film material that can be advantageously used for forming an insulating film having a low dielectric constant and excellent resistance to damage, such as etching resistance and resistance to liquid reagents, a multilayer interconnection structure in which a parasitic capacitance between the interconnections can be reduced, efficient methods for manufacturing the multilayer interconnection structure, and an efficient method for manufacturing a semiconductor device with a high speed and reliability. The insulating film material contains at least a silicon compound having a steric structure represented by Structural Formula (1) below. where, R1, R2, R3, and R4 may be the same or different and at least one of them represents a functional group containing any of a hydrocarbon and an unsaturated hydrocarbon.

Abstract: A method for producing an oxide confined semiconductor laser uses a dual platform to synchronously produce a light emitting active area and a wire bonding area on a semiconductor material and use a metal protective material, an electrically conductive metal material, and a dielectric material together with an etching process, an oxide confined technology, and plating technology to produce the dual platform, an oxide layer, a dielectric layer, a protective layer, and a metal layer. The light emitting active area platform and the wire bonding area platform are independent, and the wire bonding area platform is produced on the semiconductor structure, such that an ion implant process can adjust the capacitance and provide a higher wire bonding strength. Since the electric layer is filled on the external sides of the dual platforms, the wire connected metal capacitance is lowered, and the planarization facilitates the production of the metal layer.

Abstract: A method of making a circuitized substrate including a composite layer including a first dielectric sub-layer including a plurality of fibers having a low coefficient of thermal expansion and a second dielectric sub-layer of a low moisture absorptivity resin, the second dielectric sub-layer not including continuous or semi-continuous fibers or the like as part thereof. The substrate further includes at least one electrically conductive layer as part thereof.

Abstract: An interconnection substrate including therein one or more resin layers, each of the resin layers including therein a via-hole penetrating from a top surface to a bottom surface of the resin layer. A via-plug of metal particles is formed in the via-hole. Each of the metal particles has a flat shape generally parallel to a plane of the resin layer.

Abstract: A method for forming a cap layer for an interconnect structure is provided. The method includes providing a substrate; depositing a low-k dielectric layer comprising a first porogen over the substrate; depositing a low-k cap layer comprising a second porogen on the low-k dielectric layer; and curing the low-k dielectric layer and the low-k cap layer simultaneously to remove the first and the second porogens, so that a first porosity in the low-k dielectric layer and a second porosity in the low-k cap layer are created. The second porosity is preferably less than the first porosity. Preferably, the low-k dielectric layer and the low-k cap layer comprise a common set of precursors and porogens, and are in-situ performed.

Abstract: An integrated circuit structure comprising an air gap and methods for forming the same are provided. The integrated circuit structure includes a conductive line; a self-aligned dielectric layer on a sidewall of the conductive line; an air-gap horizontally adjoining the self-aligned dielectric layer; a low-k dielectric layer horizontally adjoining the air-gap; and a dielectric layer on the air-gap and the low-k dielectric layer.

Abstract: A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column.

Abstract: It is an object of the present invention to provide a method for forming an interlayer insulation film suppressing the occurrence of voids in the interlayer insulation film. A method for forming an interlayer insulation film of the present invention, comprising the steps of: (1) forming an etching stopper film of a silicon nitride film on an entire surface including a step part on a semiconductor substrate having the step part with an aspect ratio of ?3; (2) forming an interlayer insulation film of an impurity-doped silicate film on the silicon nitride film; and (3) performing reflow of the interlayer insulation film by a heat treatment, wherein the formation of the silicon nitride film is controlled such that the N—H bond density of the silicon nitride film is 1.0×1022 pieces/cm3 or less.

Abstract: The present invention provides a method for depositing nano-porous low dielectric constant films by reacting a mixture comprising an oxidizable silicon component and an oxidizable component having thermally labile groups with an oxidizing gas in gas-phase plasma-enhanced reaction. The deposited silicon oxide based film is annealed to form dispersed microscopic voids that remain in a nano-porous silicon oxide based film having a low-density structure. The nano-porous silicon oxide based films are useful for forming layers between metal lines with or without liner or cap layers. The nano-porous silicon oxide based films may also be used as an intermetal dielectric layer for fabricating dual damascene structures.

Abstract: A semiconductor IC device which includes a circuit region and a peripheral region on a main surface of a semiconductor substrate, a first insulating film formed over the main surface, external terminals arranged in the peripheral region and formed over the first insulating film, a conductive guard ring formed over the first insulating film and provided around the external terminals, and second insulating films formed in the internal region and the peripheral region, the second insulating film in the peripheral region is formed over the first insulating film and over the guard ring and is contacting the external terminals, the second insulating films of the circuit region and that of the peripheral region are separately formed and are isolated from each other. Separate second insulating film may be formed over the wirings of one or more of existing wiring levels of the semiconductor device.

Abstract: Interconnect structures are fabricated by methods that comprise depositing a thin conformal passivation dielectric and/or diffusion barrier cap and/or hard mask by an atomic layer deposition or supercritical fluid based process.

Abstract: A method of forming low dielectric contrast structures by imprinting a silsesquioxane based polymerizable composition. The imprinting composition including: one or more polyhedral silsesquioxane oligomers each having one or more polymerizable groups, wherein each of the one or more polymerizable group is bound to a different silicon atom of the one or more polyhedral silsesquioxane oligomers; and one or more polymerizable diluents, the diluents constituting at least 50% by weight of the composition.