Abstract: A method of selectively depositing a material on a substrate with a first and second surface, the first surface being different than the second surface. The depositing of the material on the substrate comprises: supplying a bulk precursor comprising metal atoms, halogen atoms and at least one additional atom not being a metal or halogen atom to the substrate; and supplying a reactant to the substrate. The bulk precursor and the reactant have a reaction with the first surface relative to the second surface to form more material on the first surface than on the second surface.

Abstract: The present invention provides a capacitor having a first structure made of a metal layer and a second structure made of the same metal layer and a dielectric layer between the first and the second metal structure, wherein the dielectric layer has a relative permittivity greater than 4, in particular greater than 6. It also provides a monolithically integrated circuit including such a capacitor and optionally other components. A method of manufacturing such a capacitor is also provided.

Abstract: An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.

Abstract: Provided are an adapter board and a method for forming the same, a packaging method, and a package structure. One form of a method for forming an adapter board includes: providing a base, including an interconnect region and a capacitor region, the base including a front surface and a rear surface that are opposite each other; etching the front surface of the base, to form a first trench in the base of the interconnect region and form a second trench in the base of the capacitor region; forming a capacitor in the second trench; etching a partial thickness of the base under the first trench, to form a conductive via; forming a via interconnect structure in the conductive via; and thinning the rear surface of the base, to expose the via interconnect structure.

Abstract: A method of forming a pattern includes forming an etching object layer on a substrate. A photoresist layer including a metal, oxygen and an organic material is formed on the etching object layer. An exposure process is performed on the photoresist layer. A developing process is performed on the photoresist layer to form a photoresist pattern including a metal oxide. Ozone is provided onto the substrate to remove a residue of the photoresist layer that includes the organic material. The etching object layer is etched using the photoresist pattern as an etching mask.

Abstract: In an embodiment, a semiconductor wafer is provided that includes a plurality of component positions with scribe line regions located at least one of adjacent to and between the component positions. The component positions include an active device structure. An auxiliary structure is positioned in one or more of the scribe line regions. The auxiliary structure is electrically coupled to an auxiliary contact pad which includes tungsten. The auxiliary structure does not interact with or affect the active device structure in the component positions.

Abstract: Integrated chips and methods of forming the same include forming a lower conductive line over an underlying layer. An upper conductive via is formed over the lower conducting lines. An encapsulating layer is formed on the lower conductive line and the upper conductive via using a treatment process that converts an outermost layer of the lower conductive line and the upper conductive via into the encapsulating layer.

Abstract: A method for manufacturing a semiconductor device includes forming a metal layer in a substrate and sequentially forming a barrier layer and an insulating layer on the substrate. The method includes performing a first etching step to form an opening in the insulating layer, and the opening does not expose the barrier layer. After the first etching step, a gap-filling layer is formed on the insulating layer and fills the opening. The method includes performing a second etching step to form a first via communicating with the opening in the gap-filling layer, and an upper portion of the opening is widened to form a trench. The method includes performing a third etching step to remove the gap-filling layer in a bottom of the opening and to deepen both the trench and the opening. The method includes forming a second via communicating with the opening to expose the metal layer.

Abstract: A method includes fabricating a semiconductor device, wherein the method includes depositing a coating layer on a first region and a second region under a loading condition such that a height of the coating layer in the first region is greater than a height of the coating layer in the second region. The method also includes applying processing gas to the coating layer to remove an upper portion of the coating layer such that a height of the coating layer in the first region is a same as a height of the coating layer in the second region.

Abstract: A method of forming a diffusion barrier layer on a dielectric or semiconductor substrate by a wet process. The method includes the steps of treating the dielectric or semiconductor substrate with an aqueous pretreatment solution comprising one or more adsorption promoting ingredients capable of preparing the substrate for deposition of the diffusion barrier layer thereon; and contacting the treated dielectric or semiconductor substrate with a deposition solution comprising manganese compounds and an inorganic pH buffer (optionally, with one or more doping metals) to the diffusion barrier layer thereon, wherein the diffusion barrier layer comprises manganese oxide. Also included is a two-part kit for treating a dielectric or semiconductor substrate to form a diffusion barrier layer thereon.

Abstract: The present application discloses method for fabricating a conductive feature and a method for fabricating a semiconductor device. The method includes providing a substrate; forming a recess in the substrate; conformally forming a first nucleation layer in the recess; performing a post-treatment to the first nucleation layer; and forming a first bulk layer on the first nucleation layer to fill the recess. The first nucleation layer and the first bulk layer configure the conductive feature. The first nucleation layer and the first bulk layer include tungsten. The post-treatment includes a borane-containing reducing agent.

Abstract: A method for forming a semiconductor device, includes: forming a metal layer on a semiconductor substrate; forming a dielectric layer over the metal layer; etching a top portion of the dielectric layer; after etching the top portion of the dielectric layer, removing first mist from a bottom portion of the dielectric layer; removing the bottom portion of the dielectric layer to expose the metal layer; performing a pre-clean operation, using an alcohol base vapor or an aldehyde base vapor, on the dielectric layer and the metal layer; and forming a conductor extending through the dielectric layer and in contact with the metal layer.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a substrate, a first through substrate via configured to penetrate at least partially through the substrate, the first through substrate via having a first aspect ratio, and a second through substrate via configured to penetrate at least partially through the substrate. The second through substrate via has a second aspect ratio greater than the first aspect ratio, and each of the first through substrate via and the second through substrate via includes a first conductive layer and a second conductive layer. A thickness in a vertical direction of the first conductive layer of the first through substrate via is less than a thickness in the vertical direction of the first conductive layer of the second through substrate via.

Abstract: Described are microelectronic devices comprising a dielectric layer formed on a substrate, a feature comprising a gap defined in the dielectric layer, a barrier layer on the dielectric layer, a two metal liner film on the barrier layer and a gap fill metal on the two metal liner. Embodiments provide a method of forming a microelectronic device comprising the two metal liner film on the barrier layer.

Abstract: The present application discloses a method for fabricating a semiconductor device with a protection structure for suppressing electromagnetic interference and air gaps for reducing parasitic capacitance. The method includes providing a first semiconductor die, forming a connecting dielectric layer above the first semiconductor die, forming a first trench in the connecting dielectric layer, forming a plurality of sacrificial spacers on sides of the first trench, forming a first protection structure in the first trench, and performing an energy treatment to turn the plurality of sacrificial spacers into a plurality of air gaps. The plurality of sacrificial spacers are formed of an energy-removable material and the first protection structure is formed of copper, aluminum, titanium, tungsten, or cobalt.

Abstract: A semiconductor structure includes an Nth metal layer, a diffusion barrier layer over the Nth metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1)th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an insulative material at least partially over an electrically conductive feature. The method can further include forming a ring of electrically non-conductive material extending at least partially about a sidewall of the insulative material that defines the opening. The method can further include removing a portion of the ring to form an opening over the electrically conductive feature, and then depositing an electrically conductive material into the opening in the ring to form a conductive via electrically coupled to the electrically conductive feature.

Abstract: A display device, and a method and apparatus for manufacturing the display device, are provided. The display device includes a cover window including a curved portion, and a display panel smaller in at least one of length or width than the cover window and laminated on a flat portion of the cover window.

Abstract: Structures for a semiconductor device including airgap isolation and methods of forming a semiconductor device structure that includes airgap isolation. The structure includes a trench isolation region, an active region of semiconductor material surrounded by the trench isolation region, and a field-effect transistor including a gate within the active region. The structure further includes a dielectric layer over the field-effect transistor, a first gate contact coupled to the gate, and a second gate contact coupled to the gate. The first and second gate contacts are positioned in the dielectric layer over the active region, and the second gate contact is spaced along a longitudinal axis of the gate from the first gate contact. The structure further includes an airgap including a portion positioned in the dielectric layer over the gate between the first and second gate contacts.

Abstract: A semiconductor device includes a substrate and a first semiconductor layer and a second semiconductor layer each extending in a first direction perpendicular to a surface of the substrate. Furthermore, the semiconductor device includes a first plug provided on the first semiconductor layer and a second plug provided on the second semiconductor layers, and a connection wiring having an upper surface that is at a same height along the first direction as upper surfaces of the first and second plugs, and having a lower surface that is at a same height along the first direction as lower surfaces of the first and second plugs. Furthermore, the semiconductor device includes a first wiring provided on the first plug and the connection wiring and a second wiring provided on the second plug and the connection wiring.

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a first insulating layer and a plurality of metal wires on the first insulating layer. The plurality of metal wires may include a first metal wire including a first upper surface and a first lower surface that faces the first insulating layer and a second metal wire including a second upper surface and a second lower surface that faces the first insulating layer and is coplanar with the first lower surface. The first metal wire may have a first width monotonically decreasing from the first lower surface to the first upper surface, and the second metal wire may have a second width monotonically increasing from the second lower surface to the second upper surface.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure has a first conductive layer on a first substrate and a second conductive layer on a second substrate. A bonding structure is disposed between the first conductive layer and the second conductive layer. A support structure is disposed between the first substrate and the second substrate. A passivation layer covers a bottom surface of the first conductive layer and has a lower surface facing an uppermost surface of the support structure.

Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit (IC) having a heterojunction bipolar transistor (HBT) device. The HBT device generally includes an emitter region, a collector region, and a base region disposed between the emitter region and the collector region, the base region and the collector region comprising different semiconductor materials. The HBT device may also include an etch stop layer disposed between the collector region and the base region. The HBT device also includes an emitter contact, wherein the emitter region is between the emitter contact and the base region, and a collector contact, wherein the collector region is between the collector contact and the base region.

Abstract: Embodiments of the present invention disclose a method forming a via and a trench. By utilizing a first etching process, a first metal layer of a multi-layered device to form a via, wherein the multi-layered device comprises the first metal layer and a second metal layer, wherein the first metal layer is formed directly on top of the second metal layer, wherein the second metal layer acts as an etch stop for the first etching process, wherein the first etching process does not affect the second metal layer. By utilizing a second etching process, the second metal layer of the multi-layered device to form a trench, wherein first metal layer is not affected by the second etching process, wherein the first etching process and the second etching process are two different etching process.

Abstract: A method includes loading a wafer into a processing chamber, wherein the processing chamber is wound by a coil, and the coil is coupled to an RF system; supplying an aromatic hydrocarbon precursor into the processing chamber; after supplying the aromatic hydrocarbon precursor, turning on an RF power of the RF system to decompose the aromatic hydrocarbon precursor into active radicals and cyclize the active radicals into a graphene layer over a metal layer on the wafer; and after an entirety of the metal layer being covered by the graphene layer, turning off the RF power of the RF system to stop forming the graphene layer.

Abstract: Methods for forming an integrated circuit are provided. Aspects include providing a wafer substrate having an embedded memory area interconnect structure and an embedded non-memory area interconnect structure, the memory area interconnect structure comprising metal interconnects formed within a first interlayer dielectric, recessing a portion of the memory area interconnect structure, forming a bottom electrode contact on the recessed portion of the memory area interconnect structure, forming a bottom electrode over the bottom electrode contact, forming a protective dielectric layer over the non-memory area interconnect structure, and forming memory element stack layers on a portion of the bottom electrode.

Abstract: Systems and methods for designing a dummy pattern layout for improving surface flatness of a wafer are provided. An exemplary system includes at least one processor and at least one memory storing instructions. The instructions, when executed by the at least one processor, cause the at least one processor to perform operations. The operations include identifying a feature pattern corresponding to a functional region of the wafer. The operations also include determining a property of the feature pattern based on a script associated with the feature pattern. The operations further include determining a dummy pattern rule based on the property of the feature pattern. Moreover, the operations include generating a dummy pattern corresponding to a vacant region of the wafer by wrap-filling dummy units in an adjacent area surrounding the feature pattern based on the dummy pattern rule.

Abstract: A planarization processing device for polishing a substrate, e.g., a semiconductor wafer, includes two planarization processing sections (SP1, SP2) that each include a holder (62) for holding a workpiece (W), a drive motor (71) that rotates the holder (62), a support plate (4) holds a pad (5), a linear guide (3) that guides reciprocal movement of the support plate (4) in a direction parallel to the surface of the pad (5), and a drive cylinder (72) that advances the holder (62) or the support plate (4) in a direction that intersects the surface of the workpiece W or the pad (5) to cause the opposing surfaces of the workpiece and the pad (5) to be at least proximal to each other. A primary driver (PD) causes the support plates (4) of the planarization processing sections (SP1, SP2) to reciprocate along the same straight line in opposite phases.

Abstract: In a method of manufacturing a piezoelectric device, during an isolation formation step, a supporting substrate has a piezoelectric thin film formed on its front with a compressive stress film present on its back. The compressive stress film compresses the surface on a piezoelectric single crystal substrate side of the supporting substrate, and the piezoelectric thin film compresses the back of the supporting substrate, which is opposite to the surface on the piezoelectric single crystal substrate side. Thus, the compressive stress produced by the compressive stress film and that produced by the piezoelectric thin film are balanced in the supporting substrate, which causes the supporting substrate to be free of warpage and remain flat. A driving force that induces isolation in the isolation formation step is gasification of the implanted ionized element rather than the compressive stress to the isolation plane produced by the piezoelectric thin film.

Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.

Abstract: A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate and a first dielectric layer on the substrate and having an opening for a first interconnect layer extending to the substrate, forming a first mask layer on a portion of the first dielectric layer spaced apart from the opening, forming a first metal layer filling the opening and covering a portion of the first dielectric layer not covered by the first mask layer, removing the first mask layer, forming a second dielectric layer on the first dielectric layer and on the first metal layer and having a trench for a second interconnect layer, the trench exposing a portion of the first metal layer; and forming a second metal layer filling the trench and in contact with the exposed portion of the first metal layer.

Abstract: Some embodiments of the present disclosure relate to an integrated circuit. The integrated circuit has a first semiconductor die and a second semiconductor die. The first semiconductor die is bonded to the second semiconductor die by one or more bonding structures. A first plurality of support structures are disposed between the first semiconductor die and the second semiconductor die. The first plurality of support structures are spaced apart from the one or more bonding structures. The first plurality of support structures are configured to hold together the first semiconductor die and the second semiconductor die.

Abstract: A touch electrode structure including first and second touch electrodes alternately arranged at same layer is provided. The touch electrode further includes first and second connecting sections electrically connecting adjacent first or second touch electrodes arranged in a first direction or a second direction, respectively. The first connecting sections and the second connecting sections overlap in some areas. A first insulating medium is arranged between the first touch electrodes and the second touch electrodes for insulation of the two. A second insulating medium is arranged between the first connecting sections and the second connecting sections in the overlapping areas for insulation of the two. The thickness of the second insulating medium, of the first connecting sections in the overlapping areas and of the second connecting sections in the overlapping areas is each less than a thickness of the first touch electrodes, and of the second touch electrodes.

Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.

Abstract: An integrated circuit (IC) device includes a semiconductor substrate having a via hole extending through at least a part thereof, a conductive structure in the via hole, a conductive barrier layer adjacent the conductive structure; and a via insulating layer interposed between the semiconductor substrate and the conductive barrier layer. The conductive barrier layer may include an outer portion oxidized between the conductive barrier layer and the via insulating layer, and the oxidized outer portion of the conductive barrier layer may substantially surrounds the remaining portion of the conductive barrier layer.

Abstract: A semiconductor device includes a plurality of semiconductor die and a plurality of conductive vias formed in the semiconductor die. An insulating layer is formed over the semiconductor die while leaving the conductive vias exposed. An interconnect structure is formed over the insulating layer and conductive vias. The insulating layer is formed using electrografting or oxidation. An under bump metallization is formed over the conductive vias. A portion of the semiconductor die is removed to expose the conductive vias. The interconnect structure is formed over two or more of the conductive vias. A portion of the semiconductor die is removed to leave the conductive vias with a height greater than a height of the semiconductor die. A second insulating layer is formed over the first insulating layer. A portion of the second insulating layer is removed to expose the conductive via.

Abstract: A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.

Abstract: A pattern substrate includes a substrate having a surface on which a first area and a second area are formed, and a pattern layer formed at the first area among the first area and the second area. The pattern layer is a wiring pattern layer or a transparent electrode, the first area has a convex/concave shape where a capillary phenomenon occurs, and the convex/concave shape includes an aggregate of a plurality of structures.

Abstract: A method for etching a layer assembly, the layer assembly including an intermediate layer sandwiched between an etch layer and a stop layer, the method including a step of etching the etch layer using a first etchant and a step of etching the intermediate layer using a second etchant. The first etchant includes a first etch selectivity of at least 5:1 with respect to the etch layer and the intermediate layer. The second etchant includes a second etch selectivity of at least 5:1 with respect to the intermediate layer and the stop layer. The first etchant being is different from the second etchant.

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a co-planar or flat top surface. Another feature is a method of forming an interconnect structure that results in the interconnect structure having a surface that is angled upwards greater than zero with respect to a top surface of the substrate. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Abstract: By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. After forming the trench isolation structure, the desired electrical connection across the trench isolation structure may be re-established by providing a further conductive material.

Abstract: A method, and the resulting structure, to make a thinned substrate with backside redistribution wiring connected to through silicon vias of varying height. The method includes thinning a backside of a substrate to expose through silicon vias. Then a thick insulator stack, including an etch stop layer, is deposited and planarized. With a planar insulating surface in place, openings in the insulator stack can be formed by etching. The etch stop layer in the dielectric stack accommodates the differing heights vias. The etch stop is removed and a conductor having a liner is formed in the opening. The method gives a unique structure in which a liner around the bottom of the through silicon via remains in tact. Thus, the liner of the via and a liner of the conductor meet to form a double liner at the via/conductor junction.

Abstract: A semiconductor device includes, on a semiconductor substrate, a gate insulating film, a pMIS metal material or an nMIS metal material, a gate electrode material, and a gate sidewall metal layer.

Abstract: A method includes defining a photoresist layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is formed over the photoresist and the first dielectric layer. The spacer layer has an opening that has a via width. The opening is disposed directly above a via location. A metal trench with a metal width is formed in the first dielectric layer. The metal width at the via location is greater than the via width. A via hole with the via width is formed at the via location in the second dielectric layer.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of semiconductor structures over a substrate, forming an interlayer dielectric layer over the semiconductor structures, etching the interlayer dielectric layer, and defining open parts between the semiconductor structures to expose a surface of the substrate, forming sacrificial spacers on sidewalls of the open parts, forming conductive layer patterns in the open parts, and causing the conductive layer patterns and the sacrificial spacers to reach each other, and defining air gaps on the sidewalls of the open parts.

Abstract: A method of forming an interconnection structure includes forming an opening in an insulation film by a dry etching process that uses an etching gas containing fluorine; cleaning a bottom surface and a sidewall surface of the opening by exposing to a superheated steam; covering the bottom surface and the sidewall surface of the opening with a barrier metal film; depositing a conductor film on the insulation film via the barrier metal film to fill the opening with the conductor film; forming an interconnection pattern by the conductor film in the opening by polishing the conductor film and the barrier metal film underneath the conductor film by a chemical mechanical polishing process until a surface of the insulation film is exposed.

Abstract: Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a layer of dielectric material overlying a doped region formed in a semiconductor substrate adjacent to a gate structure and forming a conductive contact in the layer of dielectric material. The conductive contact overlies and electrically connects to the doped region. The method continues by forming a second layer of dielectric material overlying the conductive contact, forming a voided region in the second layer overlying the conductive contact, forming a third layer of dielectric material overlying the voided region, and forming another voided region in the third layer overlying at least a portion of the voided region in the second layer. The method continues by forming a conductive material that fills both voided regions to contact the conductive contact.

Abstract: The present disclosure is directed to, among other things, an illustrative method that includes forming an opening in a dielectric material of a contact level of a semiconductor device, and selectively depositing a conductive material in the opening to form a contact element therein, the contact element extending to a contact area of a circuit element and having a laterally restricted excess portion formed outside of the opening and above the dielectric material. The disclosed method further includes forming a sacrificial material layer above the dielectric material and the contact element, the sacrificial material layer surrounding the laterally restricted excess portion. Additionally, the method includes planarizing a surface topography of the contact level in the presence of the sacrificial material so as to remove the laterally restricted excess portion from above the dielectric material.

Abstract: Techniques disclosed herein may achieve crack free filling of structures. A flowable film may substantially fill gaps in a structure and extend over a base in an open area adjacent to the structure. The top surface of the flowable film in the open area may slope down and may be lower than top surfaces of the structure. A capping layer having compressive stress may be formed over the flowable film. The bottom surface of the capping layer in the open area adjacent to the structure is lower than the top surfaces of the lines and may be formed on the downward slope of the flowable film. The flowable film is cured after forming the capping layer, which increases tensile stress of the flowable film. The compressive stress of the capping layer counteracts the tensile stress of the flowable film, which may prevent a crack from forming in the base.

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.