Planarization Patents (Class 438/626)
  • Patent number: 10770301
    Abstract: A planarization processing device for polishing a substrate, e.g., a semiconductor wafer, includes two planarization processing sections (SP1, SP2) that each include a holder (62) for holding a workpiece (W), a drive motor (71) that rotates the holder (62), a support plate (4) holds a pad (5), a linear guide (3) that guides reciprocal movement of the support plate (4) in a direction parallel to the surface of the pad (5), and a drive cylinder (72) that advances the holder (62) or the support plate (4) in a direction that intersects the surface of the workpiece W or the pad (5) to cause the opposing surfaces of the workpiece and the pad (5) to be at least proximal to each other. A primary driver (PD) causes the support plates (4) of the planarization processing sections (SP1, SP2) to reciprocate along the same straight line in opposite phases.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: September 8, 2020
    Assignee: TOHO ENGINEERING CO., LTD.
    Inventors: Tatsutoshi Suzuki, Eisuke Suzuki, Daisuke Suzuki
  • Patent number: 10707406
    Abstract: In a method of manufacturing a piezoelectric device, during an isolation formation step, a supporting substrate has a piezoelectric thin film formed on its front with a compressive stress film present on its back. The compressive stress film compresses the surface on a piezoelectric single crystal substrate side of the supporting substrate, and the piezoelectric thin film compresses the back of the supporting substrate, which is opposite to the surface on the piezoelectric single crystal substrate side. Thus, the compressive stress produced by the compressive stress film and that produced by the piezoelectric thin film are balanced in the supporting substrate, which causes the supporting substrate to be free of warpage and remain flat. A driving force that induces isolation in the isolation formation step is gasification of the implanted ionized element rather than the compressive stress to the isolation plane produced by the piezoelectric thin film.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: July 7, 2020
    Assignee: MURATA MANUFACTURING CO., LTD
    Inventor: Korekiyo Ito
  • Patent number: 10700025
    Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Yen-Chang Hu, Ching-Wen Hsiao, Mirng-Ji Lii, Chung-Shi Liu, Chien Ling Hwang, Chih-Wei Lin, Chen-Shien Chen
  • Patent number: 10553536
    Abstract: A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate and a first dielectric layer on the substrate and having an opening for a first interconnect layer extending to the substrate, forming a first mask layer on a portion of the first dielectric layer spaced apart from the opening, forming a first metal layer filling the opening and covering a portion of the first dielectric layer not covered by the first mask layer, removing the first mask layer, forming a second dielectric layer on the first dielectric layer and on the first metal layer and having a trench for a second interconnect layer, the trench exposing a portion of the first metal layer; and forming a second metal layer filling the trench and in contact with the exposed portion of the first metal layer.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: February 4, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION
    Inventors: Zuopeng He, Ji Guang Zhu
  • Patent number: 10510684
    Abstract: Some embodiments of the present disclosure relate to an integrated circuit. The integrated circuit has a first semiconductor die and a second semiconductor die. The first semiconductor die is bonded to the second semiconductor die by one or more bonding structures. A first plurality of support structures are disposed between the first semiconductor die and the second semiconductor die. The first plurality of support structures are spaced apart from the one or more bonding structures. The first plurality of support structures are configured to hold together the first semiconductor die and the second semiconductor die.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin
  • Patent number: 10379685
    Abstract: A touch electrode structure including first and second touch electrodes alternately arranged at same layer is provided. The touch electrode further includes first and second connecting sections electrically connecting adjacent first or second touch electrodes arranged in a first direction or a second direction, respectively. The first connecting sections and the second connecting sections overlap in some areas. A first insulating medium is arranged between the first touch electrodes and the second touch electrodes for insulation of the two. A second insulating medium is arranged between the first connecting sections and the second connecting sections in the overlapping areas for insulation of the two. The thickness of the second insulating medium, of the first connecting sections in the overlapping areas and of the second connecting sections in the overlapping areas is each less than a thickness of the first touch electrodes, and of the second touch electrodes.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: August 13, 2019
    Assignees: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Xuening Liu, Chen Liu, Yu Cai
  • Patent number: 10249728
    Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: April 2, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Daniel Chanemougame, Andre Labonte, Ruilong Xie, Lars Liebmann, Nigel Cave, Guillaume Bouche
  • Patent number: 10128168
    Abstract: An integrated circuit (IC) device includes a semiconductor substrate having a via hole extending through at least a part thereof, a conductive structure in the via hole, a conductive barrier layer adjacent the conductive structure; and a via insulating layer interposed between the semiconductor substrate and the conductive barrier layer. The conductive barrier layer may include an outer portion oxidized between the conductive barrier layer and the via insulating layer, and the oxidized outer portion of the conductive barrier layer may substantially surrounds the remaining portion of the conductive barrier layer.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: November 13, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-il Choi, Kun-sang Park, Son-kwan Hwang, Ji-soon Park, Byung-lyul Park
  • Patent number: 9865524
    Abstract: A semiconductor device includes a plurality of semiconductor die and a plurality of conductive vias formed in the semiconductor die. An insulating layer is formed over the semiconductor die while leaving the conductive vias exposed. An interconnect structure is formed over the insulating layer and conductive vias. The insulating layer is formed using electrografting or oxidation. An under bump metallization is formed over the conductive vias. A portion of the semiconductor die is removed to expose the conductive vias. The interconnect structure is formed over two or more of the conductive vias. A portion of the semiconductor die is removed to leave the conductive vias with a height greater than a height of the semiconductor die. A second insulating layer is formed over the first insulating layer. A portion of the second insulating layer is removed to expose the conductive via.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: January 9, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Duk Ju Na, Chang Beom Yong, Pandi C. Marimuthu
  • Patent number: 9711477
    Abstract: A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Yu Wu, Tin-Hao Kuo, Chita Chuang, Chen-Shien Chen
  • Patent number: 9603257
    Abstract: A pattern substrate includes a substrate having a surface on which a first area and a second area are formed, and a pattern layer formed at the first area among the first area and the second area. The pattern layer is a wiring pattern layer or a transparent electrode, the first area has a convex/concave shape where a capillary phenomenon occurs, and the convex/concave shape includes an aggregate of a plurality of structures.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: March 21, 2017
    Assignee: SONY CORPORATION
    Inventors: Hiroshi Tazawa, Kazuya Hayashibe
  • Patent number: 9305798
    Abstract: A method for etching a layer assembly, the layer assembly including an intermediate layer sandwiched between an etch layer and a stop layer, the method including a step of etching the etch layer using a first etchant and a step of etching the intermediate layer using a second etchant. The first etchant includes a first etch selectivity of at least 5:1 with respect to the etch layer and the intermediate layer. The second etchant includes a second etch selectivity of at least 5:1 with respect to the intermediate layer and the stop layer. The first etchant being is different from the second etchant.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: April 5, 2016
    Assignee: Infineon Technologies AG
    Inventors: Lothar Brencher, Dirk Meinhold, Michael Hartenberger, Georg Seidemann, Wolfgang Dickenscheid
  • Patent number: 9123703
    Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a co-planar or flat top surface. Another feature is a method of forming an interconnect structure that results in the interconnect structure having a surface that is angled upwards greater than zero with respect to a top surface of the substrate. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: September 1, 2015
    Assignee: Tessera, Inc.
    Inventors: Cyprian Uzoh, Vage Oganesian, Iiyas Mohammed
  • Patent number: 9023712
    Abstract: By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. After forming the trench isolation structure, the desired electrical connection across the trench isolation structure may be re-established by providing a further conductive material.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: May 5, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andy Wei, Roman Boschke, Markus Forsberg
  • Publication number: 20150097273
    Abstract: A method, and the resulting structure, to make a thinned substrate with backside redistribution wiring connected to through silicon vias of varying height. The method includes thinning a backside of a substrate to expose through silicon vias. Then a thick insulator stack, including an etch stop layer, is deposited and planarized. With a planar insulating surface in place, openings in the insulator stack can be formed by etching. The etch stop layer in the dielectric stack accommodates the differing heights vias. The etch stop is removed and a conductor having a liner is formed in the opening. The method gives a unique structure in which a liner around the bottom of the through silicon via remains in tact. Thus, the liner of the via and a liner of the conductor meet to form a double liner at the via/conductor junction.
    Type: Application
    Filed: December 15, 2014
    Publication date: April 9, 2015
    Inventors: Mukta G. Farooq, Richard P. Volant
  • Patent number: 8994125
    Abstract: A semiconductor device includes, on a semiconductor substrate, a gate insulating film, a pMIS metal material or an nMIS metal material, a gate electrode material, and a gate sidewall metal layer.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: March 31, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Kenshi Kanegae
  • Publication number: 20150072519
    Abstract: A method includes defining a photoresist layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is formed over the photoresist and the first dielectric layer. The spacer layer has an opening that has a via width. The opening is disposed directly above a via location. A metal trench with a metal width is formed in the first dielectric layer. The metal width at the via location is greater than the via width. A via hole with the via width is formed at the via location in the second dielectric layer.
    Type: Application
    Filed: February 26, 2014
    Publication date: March 12, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 8962472
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of semiconductor structures over a substrate, forming an interlayer dielectric layer over the semiconductor structures, etching the interlayer dielectric layer, and defining open parts between the semiconductor structures to expose a surface of the substrate, forming sacrificial spacers on sidewalls of the open parts, forming conductive layer patterns in the open parts, and causing the conductive layer patterns and the sacrificial spacers to reach each other, and defining air gaps on the sidewalls of the open parts.
    Type: Grant
    Filed: March 16, 2013
    Date of Patent: February 24, 2015
    Assignee: SK Hynix Inc.
    Inventors: Il-Cheol Rho, Jong-Min Lee
  • Patent number: 8956967
    Abstract: A method of forming an interconnection structure includes forming an opening in an insulation film by a dry etching process that uses an etching gas containing fluorine; cleaning a bottom surface and a sidewall surface of the opening by exposing to a superheated steam; covering the bottom surface and the sidewall surface of the opening with a barrier metal film; depositing a conductor film on the insulation film via the barrier metal film to fill the opening with the conductor film; forming an interconnection pattern by the conductor film in the opening by polishing the conductor film and the barrier metal film underneath the conductor film by a chemical mechanical polishing process until a surface of the insulation film is exposed.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: February 17, 2015
    Assignee: Fujitsu Limited
    Inventors: Shirou Ozaki, Yoshihiro Nakata
  • Patent number: 8951907
    Abstract: Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a layer of dielectric material overlying a doped region formed in a semiconductor substrate adjacent to a gate structure and forming a conductive contact in the layer of dielectric material. The conductive contact overlies and electrically connects to the doped region. The method continues by forming a second layer of dielectric material overlying the conductive contact, forming a voided region in the second layer overlying the conductive contact, forming a third layer of dielectric material overlying the voided region, and forming another voided region in the third layer overlying at least a portion of the voided region in the second layer. The method continues by forming a conductive material that fills both voided regions to contact the conductive contact.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: February 10, 2015
    Assignee: GlobalFoundries, Inc.
    Inventors: Ralf Richter, Jens Heinrich, Holger Schuehrer
  • Patent number: 8951900
    Abstract: The present disclosure is directed to, among other things, an illustrative method that includes forming an opening in a dielectric material of a contact level of a semiconductor device, and selectively depositing a conductive material in the opening to form a contact element therein, the contact element extending to a contact area of a circuit element and having a laterally restricted excess portion formed outside of the opening and above the dielectric material. The disclosed method further includes forming a sacrificial material layer above the dielectric material and the contact element, the sacrificial material layer surrounding the laterally restricted excess portion. Additionally, the method includes planarizing a surface topography of the contact level in the presence of the sacrificial material so as to remove the laterally restricted excess portion from above the dielectric material.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: February 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Axel Preusse, Norbert Schroeder, Uwe Stoeckgen
  • Patent number: 8937011
    Abstract: Techniques disclosed herein may achieve crack free filling of structures. A flowable film may substantially fill gaps in a structure and extend over a base in an open area adjacent to the structure. The top surface of the flowable film in the open area may slope down and may be lower than top surfaces of the structure. A capping layer having compressive stress may be formed over the flowable film. The bottom surface of the capping layer in the open area adjacent to the structure is lower than the top surfaces of the lines and may be formed on the downward slope of the flowable film. The flowable film is cured after forming the capping layer, which increases tensile stress of the flowable film. The compressive stress of the capping layer counteracts the tensile stress of the flowable film, which may prevent a crack from forming in the base.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: January 20, 2015
    Assignee: SanDisk 3D LLC
    Inventors: Hiroaki Iuchi, Hitomi Fujimoto, Chao Feng Yeh
  • Patent number: 8933551
    Abstract: A package includes an interposer, which includes a first substrate free from through-vias therein, redistribution lines over the first substrate, and a first plurality of connectors over and electrically coupled to the redistribution lines. A first die is over and bonded to the first plurality of connectors. The first die includes a second substrate, and through-vias in the second substrate. A second die is over and bonded to the plurality of connectors. The first die and the second die are electrically coupled to each other through the redistribution lines. A second plurality of connectors is over the first die and the second die. The second plurality of connectors is electrically coupled to the first plurality of connectors through the through-vias in the second substrate.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: January 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Chuan Chang, Jing-Cheng Lin, Chen-Hua Yu
  • Patent number: 8932951
    Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: January 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yuan Wu, Kong-Beng Thei, Chiung-Han Yeh, Harry-Hak-Lay Chuang, Mong-Song Liang
  • Patent number: 8912092
    Abstract: A method of forming a semiconductor device may include, but is not limited to, the following processes. A multi-layered structure is prepared over a semiconductor substrate. The multi-layered structure may include, but is not limited to, first and second patterns of a first insulating film, a second insulating film covering the first pattern of the first insulating film, and a first conductive film covering the second pattern of the first insulating film. The second insulating film and the first conductive film are polished under conditions that the first and second insulating films are greater in polishing rate than the first conductive film, to expose the first and second patterns of the first insulating film.
    Type: Grant
    Filed: October 19, 2011
    Date of Patent: December 16, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Kyoko Miyata
  • Patent number: 8883631
    Abstract: One illustrative method disclosed herein includes forming at least one layer of insulating material above a conductive structure, forming a patterned hard mask comprised of metal above the layer of insulating material, performing at least one etching process to define a cavity in the layer of insulating material, forming a layer of sacrificial material so as to overfill the cavity, performing at least one planarization process to remove a portion of the layer of sacrificial material and the patterned hard mask while leaving a remaining portion of the layer of sacrificial material within the cavity, and removing the remaining portion of the layer of sacrificial material positioned within the cavity.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: November 11, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kunaljeet Tanwar, Xunyuan Zhang, Xiuyu Cai
  • Patent number: 8865013
    Abstract: A method for chemical mechanical polishing of a substrate comprising tungsten using a nonselective chemical mechanical polishing composition.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: October 21, 2014
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Yi Guo, Jerry Lee, Raymond L. Lavoie, Jr., Guangyun Zhang
  • Patent number: 8859421
    Abstract: There is provided a manganese oxide film forming method capable of forming a manganese oxide film having high adhesivity to Cu. In the manganese oxide film forming method, a manganese oxide film is formed on an oxide by supplying a manganese-containing gas onto the oxide. A film forming temperature for forming the manganese oxide film is set to be equal to or higher than about 100° C. and lower than about 400° C.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: October 14, 2014
    Assignees: Tokyo Electron Limited, Tohoku University
    Inventors: Koji Neishi, Junichi Koike, Kenji Matsumoto
  • Patent number: 8835307
    Abstract: A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hakeem Akinmade-Yusuff, John A. Fitzsimmons, Ranee Wai-Ling Kwong
  • Patent number: 8802561
    Abstract: Techniques disclosed herein prevent wire flaking (collapse). One aspect is an improved way of forming wires over trenches, which may be located in a hookup region of a 3D memory array, and may be used to form electrical connections between conductive lines in the memory array and drivers. The trenches are formed between CMP dummy structures. The trenches are partially filled with a flowable oxide film, which leaves a gap in the trench that is at least as wide as the total pitch of the wires to be formed. A capping layer is formed over the flowable film. After forming a conductive layer over the dielectric layer, the conductive layer is etched to form conductive wires. Some of the capping layer, as well as the CMP dummy structures may be removed. Thus, the conductive wires may be at least temporarily supported by lines of material formed from the capping layer.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: August 12, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Chao Feng Yeh, Hiroaki Iuchi, Hitomi Fujimoto, Hisayuki Nozawa
  • Patent number: 8802569
    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of circuit devices over a substrate. The method includes forming an organic layer over the substrate. The organic layer is formed over the plurality of circuit devices. The method includes polishing the organic layer to planarize a surface of the organic layer. The organic layer is free of being thermally treated prior to the polishing. The organic material is un-cross-linked during the polishing. The method includes depositing a LT-film over the planarized surface of the organic layer. The depositing is performed at a temperature less than about 150 degrees Celsius. The depositing is also performed without using a spin coating process. The method includes forming a patterned photoresist layer over the LT-film.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Liang Lu, Ming-Feng Shieh, Ching-Yu Chang
  • Patent number: 8796859
    Abstract: A multilayer interconnect structure is formed by, providing a substrate (40) having thereon a first dielectric (50, 27) for supporting a multi-layer interconnection (39) having lower conductor MN (22, 23), upper conductor MN+1 (34, 35), dielectric interlayer (DIL) (68) and interconnecting via conductor VN+1/N (36, 36?). The lower conductor MN (22, 23) has a first upper surface (61) located in a recess below a second upper surface (56) of the first dielectric (50, 27). The DIL (68) is formed above the first (61) and second (56) surfaces. A cavity (1263) is etched through the DIL (68) from a desired location (122) of the upper conductor MN+1 (34), exposing the first surface (61). The cavity (1263) is filled with a further electrical conductor (80) to form the upper conductor MN+1 (34) and the connecting via conductor VN+1/N (36, 36?) making electrical contact with the first upper surface (61).
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: August 5, 2014
    Assignee: Globalfoundries, Inc.
    Inventor: Ryan Ryoung-Han Kim
  • Publication number: 20140203445
    Abstract: One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example.
    Type: Application
    Filed: January 18, 2013
    Publication date: July 24, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Taiwan Semiconductor Manufacturing Company Limited
  • Publication number: 20140187037
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of semiconductor structures over a substrate, forming an interlayer dielectric layer over the semiconductor structures, etching the interlayer dielectric layer, and defining open parts between the semiconductor structures to expose a surface of the substrate, forming sacrificial spacers on sidewalls of the open parts, forming conductive layer patterns in the open parts, and causing the conductive layer patterns and the sacrificial spacers to reach each other, and defining air gaps on the sidewalls of the open parts.
    Type: Application
    Filed: March 16, 2013
    Publication date: July 3, 2014
    Applicant: SK HYNIX INC.
    Inventors: Il-Cheol RHO, Jong-Min LEE
  • Publication number: 20140187036
    Abstract: Embodiments described herein provide approaches for interconnect formation in a semiconductor device. Specifically, a Cu layer is removed to a top surface of an Ru layer using CMP, the Cu layer is removed to form a recess within each of a plurality of trenches of a dielectric of the semiconductor device, and the Ru layer is removed using an etch process (e.g., a wet etch). An additional CMP is performed to reach the desired target trench height and to planarize the wafer.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventor: GLOBAL FOUNDERS Inc.
  • Patent number: 8759218
    Abstract: A chemical mechanical polishing process includes placing a substrate on a first polishing pad of a first platen, wherein the substrate has a bulk metal layer and a barrier layer; polishing the bulk metal layer by using the first polishing pad having a hardness of above 50 (Shore D) until the barrier layer is exposed; polishing the barrier layer on a second polishing pad of a second platen after removing the bulk metal layer, wherein the second polishing pad has a hardness ranging between 40 and 50 (Shore D) and includes an upper layer and a lower backing layer and the upper layer has a hardness less than 50 (Shore D).
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: June 24, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Boon-Tiong Neo, Chin-Kun Lin, Lee-Lee Lau
  • Publication number: 20140162450
    Abstract: An electromigration and stress migration enhancement liner is provided for use in an interconnect structure. The liner includes a metal that has a thickness at a bottom of the at least one via opening and on an exposed portion of an underlying conductive feature that is greater than a remaining thickness that is located on exposed sidewalls of the interconnect dielectric material. The thinner portion of the electromigration and stress migration enhancement liner is located between the interconnect dielectric material and an overlying diffusion barrier. The thicker portion of the electromigration and stress migration enhancement liner is located between the underlying conductive feature and the diffusion barrier as well as between an adjacent dielectric capping layer and the diffusion barrier. The remainder of the at least one via opening is filled with an adhesion layer and a conductive material.
    Type: Application
    Filed: February 14, 2014
    Publication date: June 12, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Baozhen Li
  • Publication number: 20140131841
    Abstract: Various embodiments of mechanisms for forming a slotted metal pad over a TSV in substrate are provided. The dielectric structures in the slotted metal pad reduce dishing effect during planarization of the slotted metal pad. As a result, the risk of having metal stringers in upper metal level(s) caused by the dishing effect is greatly reduced.
    Type: Application
    Filed: November 15, 2012
    Publication date: May 15, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chuan Tseng, Chia-Wei Liu, Cindy Kuo, Ren-Wei Xiao
  • Patent number: 8709939
    Abstract: A multilevel interconnect structure in a semiconductor device and methods for fabricating the same are described. The multilevel interconnect structure in the semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: April 29, 2014
    Assignees: Semiconductor Technology Academic Research Center, National University Corporation Tohoku University
    Inventors: Junichi Koike, Yoshito Fujii, Jun Iijima, Noriyoshi Shimizu, Kazuyoshi Maekawa, Koji Arita, Ryotaro Yagi, Masaki Yoshimaru
  • Patent number: 8703612
    Abstract: A method includes forming an etch stop layer over and contacting a gate electrode of a transistor, forming a sacrificial layer over the etch stop layer, and etching the sacrificial layer, the etch stop layer, and an inter-layer dielectric layer to form an opening. The opening is then filled with a metallic material. The sacrificial layer and excess portions of the metallic material over a top surface of the etch stop layer are removed using a removal step including a CMP process. The remaining portion of the metallic material forms a contact plug.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shich-Chang Suen, Liang-Guang Chen, He Hui Peng, Wne-Pin Peng, Shwang-Ming Jeng
  • Publication number: 20140091390
    Abstract: A thin-film transistor having a protection layer for a planarization layer. The protection layer prevents reduction of the planarization layer during an ashing process, thereby preventing the formation of a steeply tapered via hole through the planarization layer. In this manner, the via hole may be coated with a conductive element that may serve as a conductive path between a common electrode and the drain of the transistor.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: Apple Inc.
    Inventors: Ming-Chin Hung, Byung Duk Yang, Kyung Wook Kim, Shih Chang Chang
  • Patent number: 8679966
    Abstract: A method of manufacturing a biosensor semiconductor device in which copper electrodes at a major surface of the device are modified to form Au—Cu alloy electrodes. Such modification is effected by depositing a gold layer over the device, and then thermally treating the device to promote interdiffusion between the gold and the electrode copper. Alloyed gold-copper is removed from the surface of the device, leaving the exposed electrodes. The electrodes are better compatible with further processing into a biosensor device than is the case with conventional copper electrodes, and the process windows are wider than for gold capped copper electrodes. A biosensor semiconductor device having Au—Cu alloy electrodes is also disclosed.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: March 25, 2014
    Assignee: NXP, B.V.
    Inventors: David Van Steenwinckel, Thomas Merelle, Franciscus Petrus Widdershoven, Viet Hoang Nguyen, Dimitri Soccoi, Jan Leo Dominique Fransaer
  • Patent number: 8679967
    Abstract: The present invention provides apparatus, methods, and systems for fabricating memory lines and structures using double sidewall patterning for four times half pitch relief patterning. The invention includes forming features from a first template layer disposed above a substrate, forming half-pitch sidewall spacers adjacent the features, forming smaller features in a second template layer by using the half-pitch sidewall spacers as a hardmask, forming quarter-pitch sidewall spacers adjacent the smaller features, and forming conductor features from a conductor layer by using the quarter-pitch sidewall spacers as a hardmask. Numerous additional aspects are disclosed.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: March 25, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Yoichiro Tanaka
  • Patent number: 8669176
    Abstract: Disclosed herein are various methods of forming copper-based conductive structures on integrated circuit devices by performing a copper deposition process to fill the trench or via with copper, which can be performed by fill, plating or electroless deposition. Copper clearing of copper overburden is performed using CMP to stop on an existing liner. Copper in the trenches or vias is recessed by controlled etch. An Nblok cap layer is deposited to cap the trenches or vias so that copper is not exposed to ILD. Nblok overburden and adjacent liner is then removed by CMP. Nblok cap layer is then deposited. The proposed approach is an alternative CMP integration scheme that will eliminate the exposure of copper to ILD during CMP, will prevent any dendrite formation, can be used for all metal layers in BEOL stack, and can be utilized for multiple layers, as necessary, whenever copper CMP is desired.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: March 11, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Kunaljeet Tanwar
  • Patent number: 8637403
    Abstract: A method of manufacturing a semiconductor structure includes varying local chemical mechanical polishing (CMP) abrading rates of an insulator film by selectively varying a carbon content of the insulator film.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yoba Amoah, Graham M. Bates, Joseph P. Hasselbach, Thomas L. McDevitt, Eva A. Shah
  • Patent number: 8609528
    Abstract: Methods for patterning high-density features are described herein. Embodiments of the present invention provide a method comprising patterning a first subset of a pattern, the first subset configured to form a plurality of lines over the substrate, and patterning a second subset of the pattern, the second subset configured to form a plurality of islands over the substrate, wherein said patterning the first subset and said patterning the second subset comprise at least two separate patterning operations.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: December 17, 2013
    Assignee: Marvell International Ltd.
    Inventors: Pantas Sutardja, Albert Wu, Winston Lee, Peter Lee, Chien-Chuan Wei, Runzi Chang
  • Publication number: 20130316528
    Abstract: A system and method for forming through substrate vias is provided. An embodiment comprises forming an opening in a substrate and lining the opening with a first barrier layer. The opening is filled with a conductive material and a second barrier layer is formed in contact with the conductive material. The first barrier layer is formed with different materials and different methods of formation than the second barrier layer so that the materials and methods may be tuned to maximize their effectiveness within the device.
    Type: Application
    Filed: August 2, 2013
    Publication date: November 28, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, I, Wen-Chih Chiou, Tsang-Jiuh Wu
  • Patent number: 8541307
    Abstract: A treatment method for reducing particles in a Dual Damascene Silicon Nitride (DDSN) process, including the following steps: forming a seed layer of copper on a silicon wafer; depositing a deposition layer of copper to cover the seed layer of copper; planarizing the deposition layer of copper; providing the silicon wafer into a reaction chamber and performing a pre-treatment on a surface of the deposition layer of copper using NH3 gas under a plasma condition so as to reduce copper oxide (CuO) to copper (Cu) formed on the deposition layer of copper; in the reaction chamber, generating an etching block layer on the deposition layer of copper using a DDSN deposition process; cleaning the reaction chamber using NF3 gas; and directing N2O gas into the reaction chamber and removing the remaining hydrogen (H) and fluorine (F) in the reaction chamber using the N2O gas under the plasma condition.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: September 24, 2013
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Meimei Gu, Duoyuan Hou, Jun Xu, Ke Wang
  • Patent number: 8524587
    Abstract: Provided is a method of planarizing a semiconductor device. The method includes providing a substrate. The method includes forming a first layer over the substrate. The method includes forming a second layer over the first layer. The first and second layers have different material compositions. The method includes forming a third layer over the second layer. The method includes performing a polishing process on the third layer until the third layer is substantially removed. The method includes performing an etch back process to remove the second layer and a portion of the first layer. Wherein an etching selectivity of the etch back process with respect to the first and second layers is approximately 1:1.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: September 3, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Neng-Kuo Chen, Jeff J. Xu
  • Patent number: 8518818
    Abstract: The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: August 27, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: You-Hua Chou, Min Hao Hong, Jian-Shin Tsai, Miao-Cheng Liao, Hsiang Hsiang Ko