Abstract: Methods and compositions are disclosed for modifying a semiconductor interconnect layer to reduce migration problems while minimizing resistance increases induced by the modifications. One method features creating trenches in the interconnect layer and filling these trenches with compositions that are less susceptible to migration problems. The trenches may be filled using traditional vapor deposition methods, or electroplating, or alternately by using electroless plating methods. Ion implantation may also be used as another method in modifying the interconnect layer. The methods and compositions for modifying interconnect layers may also be limited to the via/interconnect interface for improved performance. A thin seed layer may also be placed on the semiconductor substrate prior to applying the interconnect layer. This seed layer may also incorporate similar dopant and alloying materials in the otherwise pure metal.

Abstract: A method includes steps of: (a) providing a wafer on which a film has been deposited; (b) exposing an annular area in an edge exclusion zone of the wafer to radiation having a wavelength suitable for patterning the film in the annular area; and (c) modulating the radiation while exposing the annular area to form a pattern in the film in the annular area.

Abstract: Methods of forming different back-end-of-line (BEOL) wiring for different circuits on the same semiconductor product, i.e., wafer or chip, are disclosed. In one embodiment, the method includes simultaneously generating BEOL wiring over a first circuit using a dual damascene structure in a first dielectric layer, and BEOL wiring over a second circuit using a single damascene via structure in the first dielectric layer. Then, simultaneously generating BEOL wiring over the first circuit using a dual damascene structure in a second dielectric layer, and BEOL wiring over the second circuit using a single damascene line wire structure in the second dielectric layer. The single damascene via structure has a width approximately twice that of a via portion of the dual damascene structures and the single damascene line wire structure has a width approximately twice that of a line wire portion of the dual damascene structures.

Abstract: Methods and apparatus for processing substrates to improve polishing uniformity, improve planarization, remove residual material and minimize defect formation are provided. In one aspect, a method is provided for processing a substrate having a conductive material and a low dielectric constant material disposed thereon including polishing a substrate at a polishing pressures of about 2 psi or less and at platen rotational speeds of about 200 cps or greater. The polishing process may use an abrasive-containing polishing composition having up to about 1 wt. % of abrasives. The polishing process may be integrated into a multi-step polishing process.

Abstract: Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of an applied barrier layer, on the recessed copper surfaces, is controlled to become essentially co-planar with the surrounding insulator surfaces. A thicker barrier layer eliminates the need for a capping layer. The elimination of a capping layer results in a reduction in the overall capacitive coupling, stress, and cost.

Abstract: A semiconductor device and a method of making it are described. During the formation of the semiconductor device, a hard mask is formed of an etch-resistant material. The mask prevents etchant from etching an area within a dielectric material near a conductive plug. The mask may be formed of a nitride. Conductive material is then deposited within an etched via and is contacted with the conductive plug.

Abstract: A parasitic capacitance-preventing dummy solder bump structure on a substrate has at least one conductive layer formed on the substrate, a dielectric layer employed to cover the conductive layer, an under bump metallurgy layer (UBM layer) formed on the dielectric layer, and a solder bump formed on the UBM layer.

Abstract: A method for forming a dual damascene interconnect structure provides an intermetal dielectric that includes a spin-on low-k dielectric material formed over a CVD low-k dielectric material. A via opening is formed by etching through the spin-on low-k dielectric material and the CVD low-k dielectric material and a plug material is introduced to fill the via opening. A highly selective trench etching operation etches a trench in the upper, spin-on low-k dielectric material and removes the plug material from the via without attacking the lower CVD low-k dielectric material to form the dual damascene opening which is then filled with a conductive interconnect material. The intermetal dielectric formed of multiple low-k dielectric layers provides advantageous electrical and mechanical properties.

Abstract: A wiring of a semiconductor device and a method of manufacturing the same are disclosed. A first conductive layer is formed on a semiconductor substrate followed by a first insulation material which is deposited on the first conductive layer to form a first insulation layer. Then, a CMP process is implemented to form the first insulation layer. A second insulation layer is formed by depositing a second insulation material on the first insulation layer in order to cover a scratch formed on the first insulation layer after implementing the CMP process. A first etching pattern is formed by etching the second insulation layer to a thickness less than a thickness of the second insulation layer. Thereafter, a conductive material is deposited on the etching pattern and then a planarizing process is implemented to form a conductive pattern having a damascene shape.

Abstract: A structure applied to a photolithographic process is provided. The structure comprises at least a film layer, an optical isolation layer, an anti-reflection coating and a photoresist layer sequentially formed over a substrate. In the photolithographic process, the optical isolation layer stops light from penetrating down to the film layer. Since the optical isolation layer is set up underneath the photoresist layer, light emitted from a light source during photo-exposure is prevented from reflecting from the substrate surface after passing through the film layer. Thus, the critical dimensions of the photolithographic process are unaffected by any change in the thickness of the film layer.

Abstract: Nanolithographic deposition of metallic nanostructures using coated tips for use in microelectronics, catalysis, and diagnostics. AFM tips can be coated with metallic precursors and the precursors patterned on substrates. The patterned precursors can be converted to the metallic state with application of heat. High resolution and excellent alignment can be achieved.

Abstract: The invention relates to a process for producing a semiconductor wafer by simultaneous polishing of a front surface and a back surface of the semiconductor wafer with a polishing fluid between rotating polishing plates during a polishing run which lasts for a polishing time, the semiconductor wafer being located in a cutout in a carrier having a defined carrier thickness and being held on a defined geometric path, the semiconductor wafer having a starting thickness prior to polishing and a final thickness after polishing. The polishing time for the polishing run is calculated from data which include the starting thickness of the semiconductor wafer and the carrier thickness as well as the starting thickness and final thickness and the flatness of a semiconductor wafer which was polished during a polishing run preceding the present polishing run.

Abstract: A method of filling a plurality of trenches etched in a substrate. In one embodiment the method includes depositing a layer of spin-on glass material over the substrate and into the plurality of trenches; exposing the layer of spin-on glass material to a solvent; curing the layer of spin-on glass material; and depositing a layer of silica glass over the cured spin-on glass layer using a chemical vapor deposition technique.

Abstract: A method of fabricating a microelectronic die is provided. Transistors are formed in and on a semiconductor substrate. A channel of each transistor is stressed after the transistors are manufactured by first forming a diamond intermediate substrate at an elevated temperature on a handle substrate, allowing the intermediate substrate and the handle substrate to cool, and then removing the handle substrate. The intermediate substrate has a lower coefficient of thermal expansion than the handle substrate, so that the intermediate substrate tends to bow when the handle substrate is removed. Such bowing creates a tensile stress, which translates into a biaxial strain in channels of the transistors. Excessive bowing is counteracted with a compensating polysilicon layer formed at an elevated temperature and having a higher CTE on a side of the diamond intermediate substrate.

Abstract: Highly porous, low-k dielectric materials are mechanically reinforced to enable the use of these low-k materials as interlayer dielectrics in advanced integrated circuits such as those which incorporate highly porous ILD materials in a Cu damascene interconnect technology. An integrated circuit, embodying such a mechanically reinforced ILD generally includes a substrate having interconnected electrical elements therein, a first dielectric layer disposed over the substrate, a plurality of electrically insulating structures disposed on the first dielectric layer, and a second dielectric layer disposed on the first dielectric layer such that the second dielectric surrounds the plurality of structures.

Abstract: A method and resulting structure of forming a metal on metal capacitor structure for an integrated circuit device, e.g., mixed signal. The method includes forming a dual damascene structure, where the structure has a first conductive portion comprising copper material that is separated by a dielectric material from a second conductive portion. The second conductive portion is coupled to the first conductive portion underlying the dielectric material through a third conductive portion. The first conductive portion, the dielectric material, and the second conductive portion form a substantially planar surface region opposing the third conductive portion. The first conductive portion and the second conductive portion is coupled through the third conductive portion define a first electrode. The method selectively removing the dielectric material between the first conductive portion and the second conductive portion to form an opening defined by the first conductive portion and the second conductive portion.

Abstract: A new method and structure is provided for the creation of a copper dual damascene interconnect. A dual damascene structure is created in the layer of dielectric, optionally a metal barrier layer is deposited over exposed surfaces of the dual damascene structure. A copper seed layer is deposited, the dual damascene structure is filled with copper. An anneal is applied to the created copper interconnect after which excess copper is removed from the dielectric. Of critical importance to the invention, a thin layer of oxide is then deposited as a cap layer over the copper dual damascene interconnect, an etch stop layer is then deposited over the thin layer of oxide for continued upper-level metallization.

Abstract: The present invention discloses a method including providing a substrate; forming a dielectric over the substrate, the dielectric having a k value of about 2.5 or lower, the dielectric having a Young's modulus of elasticity of about 15 GigaPascals or higher; forming an opening in the dielectric; and forming a conductor in the opening. The present invention further discloses a structure including a substrate; a dielectric located over the substrate, the dielectric having a k value of 2.5 or lower, the dielectric having a Young's modulus of elasticity of about 15 GigaPascals or higher; an opening located in the dielectric; and a conductor located in the opening.

Abstract: A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.

Abstract: A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating layer, each having an upper metal silicide layer; and a plurality of source/drain regions formed on the substrate between said gate lines solely by carrying out impurity implantation processes.

Abstract: A method for restoring an eroded portion in an exposed upper surface cavity of a metallic element in a microelectronic device, where the metallic element has a hardness, and the metallic element is laterally surrounded by lateral elements, where at least one structure within the lateral elements has a hardness that is greater than the hardness of the metallic element. A precursor material is deposited in at least the cavity of the upper surface of the metallic element. The precursor material is deposited to a thickness that at least fills the cavity of the upper surface of the metallic element. The precursor material has a hardness that is less than the hardness of the at least one structure within the lateral elements. The precursor material is removed as necessary from the lateral elements, and the precursor material is planarized. Only the precursor material within the cavity of the upper surface of the metallic element is selectively replaced with a desired material.

Abstract: A semiconductor device comprises a semiconductor substrate, an interlayer insulating layer formed above the semiconductor substrate, a first metal interconnection embedded in the interlayer insulating layer with a surface thereof exposed to the same plane as a surface of the interlayer insulating layer, a diffusion preventive layer formed on at least the first metal interconnection to prevent diffusion of a metal included in the first metal interconnection, a nitrogen-doped silicon oxide layer formed on the diffusion preventive layer, a fluorine-doped silicon oxide layer formed on the nitrogen-doped silicon oxide layer, and a second metal interconnection embedded in the fluorine-doped silicon oxide layer with a surface thereof exposed to the same plane as a surface of the fluorine-doped silicon oxide layer, and electrically connected to the first metal interconnection.

Abstract: Disclosed is a method for depositing a silicon nitride layer of a semiconductor device. The method includes the steps of providing Al-based compound as a catalyst, and reacting DCS with NH3 by using the Al catalyst, thereby depositing the silicon nitride layer. DCS is reacted with NH3 by using the Al catalyst when depositing the silicon nitride layer, so dissolution of DCS is promoted by means of the Al catalyst, so that the silicon nitride layer is deposited at a high speed, thereby improving productivity of semiconductor devices. The silicon nitride layer is deposited by using DCS under a low-temperature condition of about 500 to 800° C., without deteriorating device characteristics.

Abstract: Numerous embodiments of a stacked device underfill and a method of formation are disclosed. In one embodiment, a method of forming stacked semiconductor device with an underfill comprises forming one or more layers of compliant material on at least a portion of the top surface of a substrate, said substrate, curing at least a portion of the semiconductor device, selectively removing a portion of the one or more layer of complaint material, and assembling the substrate into a stacked semiconductor device.

Abstract: The invention describes a method for the selective dry etching of tantalum and tantalum nitride films. Tantalum nitride layers (30) are often used in semiconductor manufacturing. The semiconductor substrate is exposed to a reducing plasma chemistry which passivates any exposed copper (40). The tantalum nitride films are selectively removed using an oxidizing plasma chemistry.

Abstract: A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion having a localized non-uniformity. A bulk portion of the overburden portion is removed to planarize the overburden portion. The substantially locally planarized overburden portion is mapped to determine a global non-uniformity. The substantially locally planarized overburden portion is etched to substantially remove the global non-uniformity.

Abstract: A method for the post-etch cleaning of multi-level, damascene structures which minimizes, or substantially prevents, localized corrosion of underlying copper metallization comprises subjecting an intermediate structure in the fabrication of a multi-level, damascene structure, which structure includes an underlying copper metallization layer and an opening etched therein which exposes at least a portion of the underlying copper metallization layer, to an aqueous or acidic wash solution, in an environment substantially shielded from ambient light, to substantially remove any post-etch residues which may be present on the structure. In one embodiment, the aqueous or acidic wash solution has a nonzero static etch rate when applied to both the copper and conventional dielectric materials, e.g., silicon dioxide.

Abstract: An electrically conductive contact can be used to connect an integrated component to an interconnect. A sacrificial layer is deposited on a liner and planarized until a surface of the integrated component is uncovered. The sacrificial layer is patterned to define the later contacts. The layer is covered in a partial region above contact connection regions. An interlevel insulator is deposited and patterned, so that the sacrificial layer can then be stripped out from the partial region. After the removal of the liner, a conductive layer is deposited into the cavity formed as a result of the stripping-out process on the uncovered contact connection regions and optionally into trenches formed at the outset within the interlevel insulator.

Abstract: After a plurality of grooves are formed in an insulating film and in an anti-reflection film on the insulating film, a barrier metal film and a conductive film are deposited on the anti-reflection film such that each of the grooves is filled therewith. Subsequently, the portions of the conductive film outside the grooves are removed by polishing and then the portions of the barrier metal film outside the grooves are removed by polishing. Thereafter, respective foreign matters adhered to a polishing pad and to a surface to be polished during polishing are removed and then a surface of the anti-reflection film is polished.

Abstract: A copper damascene structure formed by direct patterning of a low-dielectric constant material is disclosed. The copper damascene structure includes a tungsten nitride barrier layer formed by atomic layer deposition using sequential deposition reactions. Copper is selectively deposited by a CVD process and/or by an electroless deposition technique.

Abstract: Methods of manufacturing semiconductor devices are disclosed. In an illustrated method, a contact hole in an insulating layer is filled with a copper layer and the copper layer is planarized. During the planarzing, a CuO layer is parasitically formed on the surface of the copper layer. The CuO layer is removed by plasma processing using ammonia or nitrogen. A conductive CuN layer is formed on the surface of the copper layer. Stability of the removal process of CuO layer is secured.

Abstract: In a feature layer of a semiconductor wafer, dummy tiles which overcome the tendency of dishing and erosion to occur during a CMP process are placed with various sizes and in various positions. An isolation zone is provided around active features. A scanning process of the feature layout surveys oxide density and nitride density over the wafer layer outside of said isolation zone. Values of the ratios of oxide/nitride density for two or more length scales which define tiling zones, are calculated. Tile placement and sizing in the zones is dependent upon the oxide/nitride density ratio values; and further upon an oxide deposition model specific to the oxide used in the fabrication process and upon a polishing model of the CMP process being employed.

Abstract: A low K dielectric layer and a cap for the low K dielectric layer are formed in situ using the same silicon precursors but at different precursor ratios. The low K dielectric is deposited with precursors that are useful for making a low K dielectric. Trenches are formed in the low K dielectric and are filled by a metal layer. Chemical mechanical processing (CMP) is utilized to remove the metal outside the trench while the cap aids planarity outside the trench.

Abstract: A method of forming buried wiring, includes the steps of forming an insulating layer having a trench on a semiconductor substrate; forming a conductive layer mainly composed of copper on the insulating layer in such a manner that the trench is filled with the conductive layer; removing an oxide layer generated in a surface of the conductive layer by oxidation; forming a cap layer made of a material having less mechanical strength than the oxide layer, on the conductive layer; and removing the cap layer and a part of the conductive layer by chemical mechanical polishing in such a manner that the conductive layer is left in the trench.

Abstract: A method of forming a cap film comprises a first polishing step of performing a polishing operation at selectivity of R1 (=removal rate for the cap film/removal rate for the insulating film), and a second polishing step of performing a polishing operation at selectivity of R2 (=removal rate for the cap film/removal rate for the insulating film). Each of the polishing operations is performed by using a slurry having the condition of R1>R2. By performing the polishing operations at different selectivity, the cap film free from problems such as dishing of the cap film and the residual cap film on side walls of a recess is formed. Consequently, a semiconductor device having an excellent RC characteristic can be provided.

Abstract: A semiconductor device of this invention includes a first interconnect pattern formed on a semiconductor substrate and a second interconnect pattern formed above the first interconnect pattern with an interlayer insulating film sandwiched therebetween. The first interconnect pattern includes a dummy pattern insulated from the first interconnect pattern, and the dummy pattern includes a plurality of fine patterns adjacent to each other and air gaps formed between the adjacent fine patterns.

Abstract: Methods are provided for forming a transistor for use in an active matrix liquid crystal display (AMLCD). In one aspect a method is provided for processing a substrate including providing a glass substrate, depositing a conductive seed layer on a surface of the glass substrate, depositing a resist material on the conductive seed layer, patterning the resist layer to expose portions of the conductive seed layer, and depositing a metal layer on the exposed portions of the conductive seed layer by an electrochemical technique.

Abstract: Methods for forming metal line of semiconductor device wherein via contact plug is formed without the deposition process of Ti/TiN liner layer and conductive layer filling a via contact hole so that the formation processes of a conductive layer for lower metal line and a conductive layer for via contact plug can be performed successively without interruption is disclosed.

Abstract: After a plurality of grooves are formed in an insulating film, a barrier metal film and a conductive film are deposited successively on the insulating film such that each of the grooves is filled completely therewith. Subsequently, the portions of the conductive film outside the grooves are removed by polishing and then the portions of the barrier metal film outside the grooves are removed by polishing. Thereafter, a foreign matter adhered to the surface to be polished during polishing is removed and then a surface of the insulating film is polished.

Abstract: The present invention discloses a semiconductor memory device having a bit line and a metal contact stud, wherein the metal contact stud is formed on a different layer from a layer on which the bit lines are formed.

Abstract: Provided are methods and composition for forming diamond metal-filled patterns above an integrated circuit substrate. A metal layer is formed above the integrated circuit substrate, which is then patterned such that a metal line is created. A plurality of diamond-shaped metal regions are then formed at least one of above and adjacent to the metal line formed on the integrated circuit substrate such that the density of metal on the integrated circuit substrate is greater than a specified density, thereby ensuring that a surface of dielectric formed above the metal line remains substantially planar after application of CMP to the dielectric layer.

Abstract: A wiring layer is covered with a first organic SOG layer, a reinforcement insulating layer consisting of a silicon oxide film or a silicon nitride film formed by means of a plasma CVD method, and a second organic SOG layer, in this order. A via hole is formed in the first organic SOG layer and the reinforcement insulating layer, and a trench is formed in the second organic SOG layer to correspond to the via hole. A conductive via plug and an electrode pad are embedded in the via hole and the trench, respectively. The second SOG layer is covered with a passivation layer in which a through hole is formed to expose the electrode pad. A wire is connected to the exposed electrode pad in the through hole.

Abstract: A low-k dielectric layer (104) is treated with a dry-wet (D-W) or dry-wet-dry (D-W-D) process to improve patterning Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130). The D-W or D-W-D treatment is performed to either pretreat a low-k dielectric (104) before forming the pattern (130) or during a rework of the pattern (130).

Abstract: After a plurality of grooves are formed in an insulating film and in an antireflection film on the insulating film, a barrier metal film and a conductive film are deposited on the anti-reflection film such that each of the grooves is filled. Subsequently, the portions of the conductive film outside the grooves are removed by a first polishing step and then the portions of the barrier metal film outside the grooves are removed by polishing. Thereafter, foreign matter adhered to the surface of the anti-reflection film is removed and a third polishing step is conducted on the surface of the anti-reflection film using an abrasive agent of the same type as used in the first polishing step of the conductive film.

Abstract: A method for isolating SAC pads of a semiconductor device, including determining a chemical mechanical polishing process time necessary to isolate the SAC pads a desired amount by referring to a relationship equation between the extent of isolation of the self-aligned contact pads and the chemical-mechanical polishing process time. The chemical mechanical polishing process is performed for the determined process time on the semiconductor device to isolate the self-aligned contact pads the desired amount. The relationship equation is determined using a test semiconductor device.

Abstract: The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components.

Abstract: An interconnect line that is enclosed within electrically conductive material is disclosed. The interconnect line, which is useful for electrically connecting devices in an integrated circuit, is defined by an aluminum layer having a bottom surface covered by a titanium layer, a top surface covered by a titanium layer, and opposing side surfaces covered by discrete titanium layers. The encapsulation of the aluminum layer within the titanium layers substantially precludes void formation within the aluminum layer. The interconnect line also may be upon a contact plug that is in electrical communication with an active area in an underlying semiconductor substrate.

Abstract: Disclosed is a semiconductor device, comprising a first wiring structure formed on a semiconductor substrate and including a first plug and a first wiring formed on the first plug, and a second wiring structure formed on the semiconductor substrate belonging to the wiring layer equal to the first wiring structure and including a second plug and a second wiring formed on the second plug, wherein the upper surface of the first wiring is positioned higher than the upper surface of the second wiring, and the lower surface of the first wiring is positioned flush with or lower than the upper surface of the second wiring. The present invention also provides a method of manufacturing the particular semiconductor device.

Abstract: A low dielectric constant material having a first fluorine concentration in a near-surface portion and a second fluorine concentration in an interior portion provides an insulator suitable for use in integrated circuits. In a further aspect of the present invention, fluorine is depleted from a near-surface portion of a fluorine containing dielectric material by a reducing plasma. Fluorine in fluorinated low-k dielectric materials, such as SiOF, amorphous fluorinated carbon (a-F:C) and parylene-AF4, can react with surrounding materials such as metals and Si3N4, causing blisters and delamination. Treatment of these fluorinated low-k dielectric materials in a reducing plasma, which may be produced from precursor gases such as H2 or NH3, depletes the surface region of fluorine and hence reduces reaction with surrounding materials and F outgassing. By selecting an appropriate point in the integration flow, specific interfaces which are most susceptible to F-attack can be targeted for depletion.

Abstract: A method of forming a more uniform copper interconnect layer is described. A dielectric layer, electroconductive (EC) layer, and a photoresist layer are sequentially deposited on a substrate. An opening in the photoresist is etched through the dielectric layer while the EC layer serves as a hard mask. Following deposition of a diffusion barrier layer and copper seed layer on the EC layer and in the opening, the copper seed layer is removed above the EC layer by a first CMP step. The EC layer serves as a CMP stop to protect the dielectric layer and provides a more uniform surface for subsequent steps. Copper is selectively deposited on the seed layer within the opening. A second CMP step lowers the copper layer to be coplanar with the dielectric layer and removes the EC layer. The resulting copper interconnect layer has a more uniform thickness and surface for improved performance.