Abstract: Interconnects in porous dielectric materials are coated with a SiC-containing material to inhibit moisture penetration and retention within the dielectric material. Specifically, SiC coatings doped with boron such as SiC(BN) show particularly good results as barrier layers for dielectric interconnects.

Abstract: A TiN.sub.x layer is formed by disposing a substrate (18) in a chamber (12). A first reactant gas (40) comprising Ti, a second reactant gas (42) and a third reactant gas (44) comprising N are introduced into the chamber (12). By controlling the ratio of the first, second and third reactant gasses (40, 42, 44), TiN.sub.x is deposited onto a surface (28) of the substrate (18), where x is between zero and one.

Abstract: A metal layer is formed at high deposition rate over severe topography by a two step process including formation of a seed layer by cold deposition followed by a second portion of the metal layer deposited at a temperature approximating but below a temperature at which metal from a lower metal layer can extrude through vias reaching thereto. The seed layer is preferably limited to a thickness at which the conformality of the cold-deposited metal will not significantly increase severity of surface topography, generally about one-fourth the thickness of the hot-deposited layer. Via connections are formed without voids and a more planar metal layer surface is formed which allows formation of a protective/anti-reflective layer with good integrity while enhancing subsequent lithographic patterning, thereby eliminating alteration of metal surface chemistry by resist developers and resultant residual metal included within the severe topography.

Abstract: A method and substrate structure for fabricating highly conductive components on microelectronic devices. In one embodiment in accordance with the principles of the present invention, a first dielectric layer is formed over a base layer of a substrate, a second dielectric layer is deposited onto the first dielectric layer, and a third dielectric layer is deposited onto the second dielectric layer. The first, second and third dielectric layers define a dielectric stratum in which the first and second dielectric layers may be selectively etchable from one another so that the second dielectric layer etches at a faster rate than the first layer in the presence of a selective etchant. After the dielectric layers are deposited onto the substrate, a void is etched through the second and third dielectric layers.

Abstract: A process for fabrication of a multilevel interconnect structure includes the formation of an inlaid interconnect (42) overlying an aluminum layer (34). The inlaid interconnect (42) is formed within an interlevel dielectric layer that is processed to contain an interconnect channel (24) and a via opening (14) residing at the bottom of the interconnect channel (24). The aluminum layer (34) is selectively deposited to fill the via opening (14) at the bottom of an interconnect channel (24). Selective deposition is enhanced by the use of a nucleation layer (20) which is formed on the bottom of the via opening, without being formed on the sidewalls, by use of directional deposition technique such as inductively coupled plasma (ICP) deposition. Nucleation layer (20) eases requirements of a cleaning operation prior to selective deposition and provides a surface from which void-free selective growth can occur.

Abstract: A semiconductor device including an interlayer insulation film is obtained, superior in planarization, insulation characteristics, and adhesion, suitable for microminiaturization of an element, and without inducing the problem of signal delay. In the fabrication method of this semiconductor device, an interconnection is formed on semiconductor substrate. Then, a first insulation film is formed so as to be in contact on the interconnection. Impurities are introduced into the first insulation film under a condition where the impurities arrive at least at the interconnection. As a result, the first insulation film is reduced in moisture and becomes less hygroscopic. Therefore, the insulation characteristics of the first insulation film is improved. When an SOG film superior in planarization is employed as the first insulation film, it is possible to directly form that SOG film on an underlying interconnection.

Abstract: A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is deposited by chemical vapor deposition, or by physical vapor deposition in a layer less than about 800 angstroms.

Abstract: A three elemental compound for diffusion barrier layer having a superior diffusion barrier characteristics manufactured by forming the compound between the silicon diffused into the diffusion barrier layer and the two elemental compound for diffusion barrier layer before the metal wire layer penetrates into the diffusion barrier layer to reach the underlying silicon layer, using the different characteristics of the diffusion rate as above, is disclosed. A method of forming three elemental compound for diffusion barrier layer according to the present invention comprises a silicon substrate. A silicide layer is deposited on the silicon substrate. A refractory metal nitride layer is then deposited on the silicide layer. A metal wire layer is deposited on the refractory metal nitride layer.

Abstract: The present invention discloses a method for simultaneously manufacturing a poly gate and a polycide gate which requires only one gate oxide layer deposition and one polysilicon layer deposition steps by incorporating a protective layer, primarily an oxide layer, which acts as a mask of a silicide. The present invention not only simplifies the process but also avoids a residual spacer in the gate. The advantages also includes widening the process window, controlling the gate channel and avoiding the gate top loss.

Abstract: The present invention relates to a method of forming an interconnection for a semiconductor device using copper. The method of the invention, including the steps of forming an insulating layer having a groove on a semiconductor substrate containing active elements; forming and depositing a copper thin film on the insulating layer including the groove; and reflowing the copper thin film, may reflow the copper thin film deposited on the semiconductor substrate having a high-step surface for less than 30 min. below 450.degree. C., which show improved annealing conditions as compared with the conventional art. In addition, by reducing consumption of thermal energy in accordance with a low-temperature process, copper is restrained from being rapidly diffused through a silicon substrate, electrodes, etc. when forming the interconnection for the semiconductor device, thus improving productivity of the semiconductor devices.

Abstract: A method is provided for improving the texture of a metal interconnect (32) in a semiconductor device (10). A first layer of titanium (24), a layer of titanium nitride (26), a second layer of titanium (28), and a metal film (30) are sequentially formed over an oxide layer (12). The second titanium layer (28) is preferably out 10-20 nm thick. Because the metal film (30) is formed over the second titanium layer (28), any metal interconnect (32) that is formed as a part of the metal film (30) has a strong (111) crystalline orientation. Furthermore, because the second titanium layer (28) is relatively thin, the metal film (30) and metal interconnect (32) are not completely transformed into a metal compound having a high electrical resistance.

Abstract: A method of forming a metal plug. A contact window is formed to penetrate through a dielectric layer on a substrate having a MOS formed thereon. A titanium glue layer is formed on the dielectric layer and the circumference of the contact window. A titanium barrier layer is formed on the titanium nitride layer. Using nitrogen plasma bombardment on the titanium nitride layer, the structure of the titanium nitride layer is transformed. The number of the nucleation seeds is increased, and the size of grains is reduced. A metal layer is formed on the titanium nitride layer and fills the contact window. A part of the metal layer is removed and a metal plug within the contact window is formed.

Abstract: A method of fabricating a metal plug. On a semiconductor substrate comprising a MOS device, a dielectric layer, and a via hole penetrating though the dielectric layer, a conformal titanium layer is formed on the dielectric layer and the via hole. A low temperature annealing is formed in a nitrogen environment, so that a surface of the titanium layer is transformed into a first thin titanium nitride layer. A conformal second titanium nitride layer is formed on the first thin titanium nitride layer by using collimator sputtering. A metal layer is formed and etched back on the second titanium nitride layer to form a metal plug.

Abstract: The invention provides a semiconductor device in which interlayer insulative layers are composed of amorphous carbon film. The amorphous carbon film may include fluorine (F) therein. The invention further provides a method of fabricating a semiconductor device including an interlayer insulative layer composed of amorphous carbon film including fluorine (F), the method having the step of carrying out plasma-enhanced chemical vapor deposition (PCVD) using a mixture gas including (a) at least one of CF.sub.4, C.sub.2 F.sub.6, C.sub.3 F.sub.8, C.sub.4 F.sub.8 and CHF.sub.3, and (b) at least one of N.sub.2, NO, NO.sub.2, NH.sub.3 and NF.sub.3. The method provides amorphous carbon film having superior heat resistance and etching characteristics. By composing interlayer insulative layers of a semiconductor device of the amorphous carbon film, the semiconductor device can operate at higher speed.

Abstract: A method to fabricate a dual damascene structure in a substrate is disclosed in the present invention. A first silicon oxide layer is deposited over the substrate and a silicon nitride layer is formed on the first silicon oxide layer. The first silicon oxide layer and the silicon nitride layer are etched in order to form a via hole on the substrate. Afterwards, a second silicon oxide layer is deposited to refill into the via hole and to cover the silicon nitride layer. A dry etching process is performed to remove the second silicon oxide layer in the via hole and to form a metal trench in the second silicon oxide layer on the silicon nitride layer and a metal trench in the second silicon oxide layer above the via hole. After the formation of the metal trenches, a portion of the second silicon oxide layer is remained on the sidewalls and the bottom of the via hole. A dry etching process is performed to remove the remaining portion of the second silicon oxide layer.

Abstract: A dual damascene process is disclosed for forming contact and via interconnects without borders. A nitride layer is first formed on a dielectric layer to function as a hard-mask. Metal line trench is first etched into the nitride layer and then into the dielectric layer. Then, a second photoresist layer is used to pattern contact or via hole over line trench opening and the dielectric layer is further etched through the line trench into the dielectric layer until the substructure of the substrate is reached. It is disclosed that by using the nitride layer as a hard-mask, the registration or alignment tolerance between the contact/via hole pattern and the metal line pattern can be relaxed substantially and not use a border as is conventionally practiced in order to assure proper registration between the patterns. The borderless interconnect is achieved by filling the composite line opening and the hole opening with metal and chemical mechanical polishing.

Abstract: A method of fabricating a dual damascene structure. A low k dielectric layer and a cap layer are successively formed on a substrate having an active region. A first photoresist layer is formed on the cap layer and the cap layer is then patterned to expose a portion of the low k dielectric layer. The first photoresist layer and a portion of the low k dielectric layer are simultaneously removed to form a wiring line opening. A second photoresist layer is formed on the cap layer to cover a portion of the wiring line opening. When the step of removing the second photoresist layer is performed, a via hole is formed to expose the active region by simultaneously removing the exposed low k dielectric layer. The via hole and the wiring line opening are filled with a metal layer to form a wiring line and a via.

Abstract: A method for fabricating a copper interconnect structure, using a Cu.sub.3 Ge intermetallic layer, as an adhesive layer, has been developed. Following the deposition of a copper seed layer, an ion implantation procedure is performed, placing germanium ions in a copper seed layer. After deposition of a thick copper layer, an anneal cycle, performed before or after deposition of the thick copper layer, is used to create a Cu.sub.3 Ge intermetallic layer at the interface between a copper seed layer and a titanium nitride barrier layer. A second embodiment of this invention uses a tilted, germanium ion implantation procedure, used to avoid the placement of germanium ions in a copper seed layer, at the bottom of a contact hole, thus avoiding possible implantation damage, to active device regions, exposed in the bottom of the contact hole.

Abstract: A process for forming via openings (24) between two aluminum-containing interconnects (15) which includes removing a veil material (22) formed during etching of an insulating layer (12), where the veil material (22) is then removed by a combination process of a first dry etch followed by an aqueous organic solvent exposure. The first dry etch uses oxygen containing and fluorine-containing gases, and is performed during the resist removal. This combination process effectively removes the veil (22), even for the heaviest of veil formation, without adversely affecting the insulating layer (12) or the underlying interconnect (15) that includes aluminum. The temperature of the aqueous organic solvent may be reduced, decreasing the amount of volatile organic compound emissions from the solvent while maintaining solvent strength.

Abstract: The present invention describes a method for forming an interconnect to a region of an electronic device. The method comprises the steps of: forming a conductive material layer, wherein the conductive material layer fills an opening in a first dielectric layer and is disposed over the first dielectric layer; applying a patterning layer over the conductive material layer, wherein the patterning layer exposes a portion of the conductive material layer; etching the conductive material layer to remove the portion of the conductive material layer in order to provide an exposed conductive material structure that protrudes above the dielectric layer; forming a second dielectric layer; and planarizing the second dielectric layer to expose a portion of the exposed conductive material structure.

Abstract: The present disclosure pertains to our discovery that depositing various film layers in a particular order using a combination of Ion Metal Plasma (IMP) and traditional sputter deposition techniques with specific process conditions results in a barrier layer structure which provides excellent barrier properties and allows for metal/conductor filling of contact sizes down to 0.25 micron and smaller without junction spiking. Specifically, the film layers are deposited on a substrate in the following order: (a) a first layer of a barrier metal (M), deposited by IMP sputter deposition; (b) a second layer of an oxygen-stuffed barrier metal (MOx), an oxygen-stuffed nitride of a barrier metal (MNOx), or a combination thereof; (c) a third layer of a nitride of a barrier metal (MN.sub.x), deposited by IMP sputter deposition of the barrier metal in the presence of nitrogen; and (d) a fourth, wetting layer of a barrier metal, deposited by traditional sputter deposition.

Abstract: A process of polishing two dissimilar conductive materials deposited on semiconductor device substrate optimizes the polishing of each of the conductive material independently, while utilizing the same polishing equipment for manufacturing efficiency. A tungsten layer (258) and a titanium layer (256) of a semiconductor device substrate (250) are polished using one polisher (10) but two different slurry formulations. The two slurries can be dispensed sequentially onto the same polishing platen (132) from two different source containers (111 and 112), wherein the first slurry is dispensed until the tungsten is removed and then the slurry dispense is switched to the second slurry for removal of the titanium. In a preferred embodiment, the first slurry composition is a ferric nitrate slurry while the second slurry composition is an oxalic acid slurry.

Abstract: A method for forming interconnection plugs comprising the steps of providing a substrate, then forming a dielectric layer having an opening that exposes a pad area for connection with other structures. Next, a glue layer is formed lining the opening and the dielectric layer. Subsequently, plug material is deposited into the opening to form a plug layer. This is followed by etching back the plug layer to a level higher than the glue layer that formed on the top of the dielectric layer. Thereafter, a metallic layer is formed over the plug layer, and a photoresist layer is then coated over the metallic layer. The metallic layer and the plug layer are then patterned by etching such that the plug layer is turned a plug. The characteristic of this invention lies in retaining a portion of the plug layer after the first etching such that the etched plug layer is at a level higher than the glue layer.

Abstract: A semiconductor structure (10)includes a semiconductor substrate (12), a silicon layer (18)overlying the semiconductor substrate, a dielectric layer (16)overlying the silicon layer and having a contact opening to expose a portion of the silicon layer, and a metal layer stack (20)overlying the dielectric layer and having a portion in contact with the silicon layer through the contact opening. The metal layer stack comprises a barrier layer (24)of titanium with incorporated oxygen (of greater than about 11 atomic percent) to provide diffusion resistance against, for example, platinum, oxygen, and silicon.

Abstract: A method for forming semiconductor device (1) that includes providing a substrate (10) having a metal interconnect (12), depositing a via interlevel dielectric (ILD) layer (20) over the substrate (10) and the metal interconnect (12), etching the via ILD layer (20) to form a via (30) over the metal interconnect (12), depositing a trench ILD layer (32) over the via ILD layer (12) and the via (30), etching the trench ILD layer (32) to form a trench (40), the trench (40) being contiguous with the via (12), and depositing a metal (44) so as to fill the via (30) and the trench (40), and provide electrical connection with the metal interconnect (12).

Abstract: Disclosed is an aluminum filled via hole for use in a semiconductor interconnect structure. The aluminum filled via hole of the semiconductor interconnect structure includes a first patterned metallization layer lying over a first dielectric layer. A second dielectric layer overlying the first patterned metallization layer and the first dielectric layer. An aluminum filled via hole defined through the second dielectric layer and in contact with the first patterned metallization layer. The aluminum filled via hole has an electromigration barrier cap over a topmost portion of the aluminum filled via hole that is substantially level with the second dielectric layer. The electromigration barrier cap having a thickness of between about 500 angstroms and about 2,500 angstroms.

Abstract: A semiconductor device comprises a substrate (100), first conductive film (22 and 32) over the substrate (100), and a second conductive film (54 and 64) over the first conductive film (22 and 32). The first conductive film includes a refractory metal and nitrogen. The first conductive film has a first portion (22) that lies closer to the substrate and a second portion (32) that lies further from the substrate. The nitrogen percentage for the second portion (32) is lower than the nitrogen atomic percentage for the first portion (22). The second conductive film (54 and 64) includes mostly copper. The combination of portions (22 and 32) within the first conductive film provides a good diffusion barrier (first portion) and has good adhesion (second portion) with the second conductive film (54 and 64).

Abstract: In a method for forming a tungsten plug interconnecting an upper level wiring conductor and a lower level wiring conductor insulated from each other by an interlayer insulator film, an adhesion layer is formed on the interlayer insulator film formed on the lower level wiring conductor. A photoresist layer is deposited on the adhesion layer, and an opening is formed in the photoresist layer. The adhesion layer is selectively removed by an isotropic etching using, as a mask, the photoresist layer having the opening formed therein, so that an opening retracted outwardly from the edge of the opening formed in the photoresist layer is formed in the adhesion layer. A hole is formed through the interlayer insulator film so that the lower level wiring conductor is exposed at a bottom of the hole, and a tungsten layer is formed in the hole of the interlayer insulator film so as to form a tungsten filling for the hole of the interlayer insulator film.

Abstract: A thin film (at least one atomic layer to about 400 .ANG.) of nickel is electrolytically plated on top of electrolytically-plated gold electrodes in GaAs monolithic microwave integrated circuits (MMICs) without any additional photoresist masking step. The thin electrolytically-plated nickel film improves adhesion of a passivating dielectric layer (e.g., silicon dioxide, silicon nitride, and silicon oxynitride) formed on the electrolytically-plated gold electrodes. The electrolytically-plated nickel film can be removed locally to facilitate the fabrication of plated silver bumps (for off-chip electrical connections and thermal paths) on passivated flip chip MMICs.

Abstract: An integrated circuit, a contact and a method of manufacture therefor. The integrated circuit has a silicon substrate with a recess formed therein that provides an environment within which the contact is formed. The contact includes: (1) an adhesion layer deposited on an inner surface of the recess, (2) an amorphous layer, deposited over the adhesion layer within the recess and (3) a central plug, composed of a conductive material, deposited at least partially within the recess, the silicide layer being amorphous to prevent the conductive material from passing through the amorphous silicide layer to contact the adhesion layer thereby to prevent junction leakage.

Abstract: A contact hole burying method is provided including the steps of: coating an oxide layer on a substrate and removing the oxide layer except for a portion thereof to form a contact hole extending through the oxide layer in electrical contact with the oxide layer; sequentially forming a metal barrier layer and wet layer on the oxide layer and inside the contact hole to form an electrical connection to the substrate; forming a conductive metal layer on the wet layer; removing impurity ions and oxide material, which remain in the conductive metal layer which decrease mobility of metal atoms on a surface of said conductive layer due to absorption and oxidation, by a cleaning-etching process using a plasma; and reflowing the conductive metal layer at a relatively low temperature in a reactive furnace where the cleaning-etching process is performed to completely fill the contact hole.

Abstract: A process for forming a semiconductor device (68) in which an insulating layer (52) is nitrided and then covered by a thin adhesion layer (58) before depositing a composite copper layer (62). This process does not require a separate diffusion barrier as a portion of the insulating layer (52) has been converted to form a diffusion barrier film (56). Additionally, the adhesion layer (58) is formed such that it can react with the interconnect material resulting in strong adhesion between the composite copper layer (62) and the diffusion barrier film (56) as well as allow a more continuous interconnect and via structure that is more resistant to electromigration.

Abstract: A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center, an edge, and a direction normal to the surface; and (B) sputter depositing a glue layer over the surface of the substrate such that an edge thickness of the glue layer measured in the direction normal to the surface at the edge of the substrate is at least 105% of a center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate.

Abstract: A plug contact process wherein, after contact holes are etched, an adhesion layer (such as Ti/TiN) and a filler metal (such as tungsten) are deposited overall. A two-stage etch is then used: First, the filler metal is etched preferentially with respect to the adhesion layer, until an endpoint signal first indicates that said adhesion layer is exposed. No overetch is used at this stage. Thereafter a nonpreferential etch is used to clear residues of the filler metal, while also uniformly reducing the height of the adhesion layer. This prevents the tops of the plugs in the contact holes from being recessed. Aluminum (or other metal) is then deposited and patterned (using a stack etch to remove the undesired portions of the adhesion layer too) to implement the desired wiring pattern. This process thereby reduces voids, and resulting metallization defects, in a process with high-aspect-ratio contacts. In addition, the residual adhesion layer helps to reduce electromigration.

Abstract: An integrated circuit fabrication process is provided in which copper is used as the contact plug material for a via. The via is a hole etched through an interlevel dielectric which is disposed upon a semiconductor topography, e.g., a silicon-based substrate having junctions therein. An inert implant may form an implant region within the semiconductor topography lying underneath the via. The process for forming the copper plug involves depositing a diffusion barrier upon the interlevel dielectric and within the via. Copper is then deposited via chemical vapor deposition upon the diffusion barrier such that the copper fills the entire via and forms a layer above the via. The copper is etched from all areas except from within the via, thereby forming a copper plug in the via. The resulting surface is then subjected to chemical-mechanical polishing before the diffusion barrier is removed from areas exclusive of the via.

Abstract: An electrical interconnect structure comprising a diffusion barrier and a method of forming the structure over a semiconductor substrate. A bi-layer diffusion barrier is formed over the substrate. The barrier comprises a capturing layer beneath a blocking layer. The blocking layer is both thicker than the capturing layer and is unreactive with the capturing layer. A conductive layer, thicker than the blocking layer, is then formed over the barrier. While the conductive layer is unreactive with the blocking layer of the barrier, the conductive layer is reactive with the capturing layer of the barrier.

Abstract: A process for forming aluminum interconnect structures has been developed, that concentrates on alleviating the effects of the poor step coverage of the interconnect metallization, that develops in areas where aluminum overlies tungsten filled contact holes. A high pressure treatment of the aluminum based metallization layer is performed at pressures in the range of 50 to 120 Mega-pascal, to improve the coverage of the aluminum based layer, specifically in seams or voids in the underlying tungsten plugs.

Abstract: A method for fabricating a tungsten plug in a contact hole by depositing a tungsten film of a predetermined thickness several times to form a multilayer structure, thereby increasing the density of the tungsten plug.

Abstract: A method to produce a contact or via opening and filled metallurgy for CMOS or other integrated circuits is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer structure is formed thereover comprising a first layer of tetraethoxysilane (TEOS), a second layer of borophospho-TEOS (BPTEOS), and a third layer of TEOS. A contact opening is etched through the insulating layer structure not covered by a mask to the semiconductor device structures to be electrically contacted wherein the profile of the contact opening is not vertical because the BPTEOS layer is etched. horizontally more than the first and third TEOS layers and wherein native oxide builds up on the sidewalls of the contact opening.

Abstract: A method for forming planarized tungsten plugs, for small diameter contact holes, using a RIE etchback process, has been developed. An objective of reducing a seam, inherent when filling holes with chemically vapor deposited materials, was realized by use of a minimum thickness of tungsten, just sufficient to fill the narrow contact hole. The attainment of the reduced tungsten seam was also aided via use of a low temperature deposition, as well as a slow deposition rate.

Abstract: A method of forming a via plug in a semiconductor device is disclosed. Metal nuclei are formed on the surface of the metal layer underlying the via hole. The metal layer, which is partially exposed between metal nuclei, is etched by means of a wet etching method, and accordingly, a plurality of etching grooves is formed on the partially exposed surface of the metal layer. As a result, the formation of such grooves has the effect of increasing the bottom surface area of the via hall, thereby increasing the adhesive strength to a contact surface of the via hall and decreasing the via resistance.