Abstract: A method for capping copper or copper alloy interconnects. A dielectric layer is formed overlaying a semiconductor substrate. An opening is formed in the dielectric layer and subsequently embedded copper or copper alloy form an interconnect structure. A silicon layer is formed on the copper or copper alloy by sputtering or chemical vapor deposition. A copper silicide layer is formed by reacting the silicon layer with the underlying copper or copper alloy as a capping layer.

Abstract: A process for enhancing the adhesion of directly plateable materials to an underlying dielectric is demonstrated, so as to withstand damascene processing. Using diffusion barriers onto which copper can be deposited facilitates conventional electrolytic processing. An ultra-thin adhesion layer is applied to a degassed, pre-cleaned substrate. The degassed and pre-cleaned substrate is exposed to a precursor gas containing the adhesion layer, optionally deposited by a plasma-assisted CVD process, resulting in the deposition of an adhesion layer inside the exposed feature. The treated wafer is then coated with a diffusion barrier material, such as ruthenium, so that the adhesion layer reacts with incoming diffusion barrier atoms. The adhesion layer may be selectively bias-sputter etched prior to the deposition of the diffusion barrier layer. A copper layer is then deposited on the diffusion barrier layer.

Abstract: An integrated circuit including a composite polymer dielectric layer formed on a substrate is disclosed, wherein the composite polymer dielectric layer includes a first silane-containing layer formed on the substrate, wherein the first silane-containing layer is formed at least partially from an organosilane material, a polymer dielectric layer formed on the first silane-containing layer, and a second silane-containing layer formed on the polymer dielectric layer. In some embodiments, the first silane-containing layer and second silane-containing layer may be formed from organosilane materials having at least one unsaturated bond capable of free radical polymerization. Systems and methods for making the disclosed integrated circuits are also provided.

Abstract: A method for fabricating an interconnect on a surface of a passivated substrate includes applying a diffusion barrier to the surface of the passivated substrate and applying a mask to the diffusion barrier. The mask is then patterned to provide an opening for the interconnect. The interconnect is deposited in the opening and the mask is removed. Those portions of the diffusion barrier that are not covered by the interconnect are also removed. The interconnect and what is left of the diffusion barrier are then encapsulated by metal-selective wet-chemical dip coating.

Abstract: A semiconductor device connecting structure for connecting a semiconductor IC 7 onto a substrate 13. A bonding layer 31 is placed between the substrate 13 and the semiconductor IC 7 to accomplish adhesion therein. This bonding layer includes an ACF 32 as a bonding material for joining said semiconductor IC 7 onto said substrate 13 and a space 33 formed within the ACF 32. Even if the IC 7 deforms due to heat or the like, the deformation is absorbed by the space a 33, whereupon the connecting conditions of bumps 28, 29 can not be unstable.

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.

Abstract: According to one embodiment of the invention, a method for providing improved layer adhesion in a semiconductor is provided. The method includes forming a dielectric layer. The method also includes forming a layer of metal in direct contact with the dielectric layer. The method also includes directly exposing the layer of metal, after forming the layer of metal, to plasma at a power level sufficient to penetrate through the layer of metal and reach the dielectric layer.

Abstract: One embodiment of the present invention is a method for making metallic interconnects, which method is utilized at a stage of processing a substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one opening, the field and the at least one opening being ready for depositing of one or more seed layers, which method includes steps of: (a) depositing a substantially conformal seed layer over the field and inside surfaces of the at least one opening; (b) depositing a substantially non-conformal seed layer over the substantially conformal seed layer, said substantially non-conformal seed layer being thicker than said substantially conformal seed layer over the field, wherein the substantially conformal and the substantially non-conformal seed layers do not seal the at least one opening; and (c) electroplating a metallic layer over the substantially non-conformal seed layer, wherein the electroplated metallic layer comprises a material selected from a gr

Abstract: Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.

Abstract: In a method of forming a contact in a semiconductor device, an insulating layer is formed on the semiconductor substrate. Then, a contact hole is formed by selectively etching the insulating layer. A barrier metal layer is deposited on side and bottom surfaces of the contact hole and on a top surface of the insulating layer to a uniform thickness. A wetting layer of an oxidation-resistive metal material is deposited on the barrier metal layer. A metal layer is formed on the wetting layer and fills the contact hole to thereby form a contact in the semiconductor device.

Abstract: A low K dielectric layer and a cap for the low K dielectric layer are formed in situ using the same silicon precursors but at different precursor ratios. The low K dielectric is deposited with precursors that are useful for making a low K dielectric. Trenches are formed in the low K dielectric and are filled by a metal layer. Chemical mechanical processing (CMP) is utilized to remove the metal outside the trench while the cap aids planarity outside the trench.

Abstract: Electronic components such as semiconductor wafer VLSI and ULSI integrated circuit devices are provided having a robust barrier layer in the device interconnects. The robust barrier layer provides excellent step coverage, low resistance and enhanced adhesion to CVD copper and the interconnect has a double structure of a layer of a barrier material and a metal layer thereon. The metal layer is preferably tungsten and is formed by replacing silicon or other such atoms on the surface of the barrier layer with tungsten metal. A layer of silicon can be formed on the barrier layer, silicon atoms can be formed on the surface by reacting the barrier layer with a silicon containing reactant or a silicon containing barrier layer can be used.

Abstract: Techniques are given for determining the data transmission or sending rates in a router or switch of two or more input queues in one or more input ports sharing an output port, which may optionally include an output queue. The output port receives desired or requested data from each input queue sharing the output port. The output port analyzes this data and sends feedback to each input port so that, if needed, the input port can adjust its transmission or sending rate.

Abstract: The electrode structure of this invention includes a silicon-containing film containing silicon as a principal constituent; a barrier metal layer of titanium nitride rich in titanium as compared with a stoichiometric ratio formed on the silicon-containing film; and a metal film with a high melting point formed on the barrier metal layer.

Abstract: Copper seed layers for use in damascene structures are commonly deposited by CVD because of their superior step coverage. However, these films have poor adhesion to the barrier layer. This problem has been overcome by preceding the deposition of the CVD copper layer with a metal plasma treatment that lays down a very thin layer of copper while the structure receiving it is maintained at a temperature below about ?40 C. This is followed by a short exposure to a nitrogen bearing plasma. The results is a seed layer having excellent step coverage as well as very good adhesion to the underlying barrier layer.

Abstract: Provided is a method of forming a metal line in a semiconductor device. According to the present invention, a barrier metal layer, a Zr film, and a Cu thin film is sequentially formed in insides of a dual damascene pattern comprising via holes and trenches. Then, a Zr film is formed on the Cu thin film, and Zr is allowed to be diffused into crystal particles of Cu and interfaces between the crystal particles by carrying out a heat treatment process thereto, so that uniform Cu (Zr) bonds are formed regardless of a depth. As a result, an EM resistance characteristic of the Cu thin film even in narrower and deeper via holes can be improved, and thus reliability of process and an electrical characteristic of a device can be also improved.

Abstract: A contact structure is provided incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe2)4, as the precursor. The contact structure is fabricated by etching a contact opening through a dielectric layer down to a diffusion region to which electrical contact is to be made. Titanium metal is deposited over the surface of the wafer so that the exposed surface of the diffusion region is completely covered by a layer of the metal. At least a portion of the titanium metal layer is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited using the LPCVD process, coating the walls and floor of the contact opening. Chemical vapor deposition of polycrystalline silicon or of a metal follows.

Abstract: A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a first alloy element into an interfacial layer over the barrier material layer, depositing an alloy layer over the interfacial layer. The implanted first alloy element is reactive with the barrier material layer to increase resistance to copper diffusion.

Abstract: Methods and solutions for forming self assembled organic monolayers that are covalently bound to metal interfaces are presented along with a device containing a self assembled organic monolayer. Embodiments of the present invention utilize self assembled thiolate monolayers to prevent the electromigration and surface diffusion of copper atoms while minimizing the resistance of the interconnect lines. Self assembled thiolate monolayers are used to cap the copper interconnect lines and chemically hold the copper atoms at the top of the lines in place, thus preventing surface diffusion. The use of self assembled thiolate monolayers minimizes the resistance of copper interconnect lines because only a single monolayer of approximately 10 ? and 20 ? in thickness is used.

Abstract: A Cu thin film deposition equipment of a semiconductor device is disclosed for improving deposition speed of a Cu thin film and lowering its corresponding cost. This equipment includes a load lock carrying out the steps before and after wafer processes, an aligner carrying out alignment so that a wafer reaches a desired position, a de-gas chamber removing residue such as gas produced on a surface of a wafer, and a feeding chamber provided with a robot placing the wafer in/out of each chamber. A pre-cleaning chamber cleaning the inside and the outside of a pattern using plasma on a wafer fed by the feeding chamber, a barrier metal deposition chamber, an adhesion glue layer (AGL) flash Cu deposition chamber, a CECVD deposition chamber, and a plasma treatment chamber are also provided with the equipment.

Abstract: Methods and apparatus for forming conductive interconnect layers useful in articles such as semiconductor chips, memory devices, semiconductor dies, circuit modules, and electronic systems. The number of necessary processing steps to form conductive interconnects are reduced by removing the need to employ a seed layer interposed between the barrier layer and the conductive interconnect layer. This is accomplished in part through the electrochemical reduction of oxides on a dual-purpose layer. The present invention can be advantageously utilized to deposit copper interconnects onto tungsten.

Abstract: An electrical interconnect structure on a substrate, includes a first porous dielectric layer with surface region from which a porogen has been removed; and an etch stop layer disposed upon the first porous dielectric layer so that the etch stop layer extends to partially fill pores in the surface region of the first porous dielectric layer from which the porogen has been removed, thus improving adhesion during subsequent processing. The porogen may be removed from the surface region by heating, and in particular by hot plate baking. A second porous dielectric layer, which may have the same composition as the first porous dielectric layer, may be formed over the etch stop layer. Electrical vias and lines may be formed in the first and second porous dielectric layer, respectively. The layers may be part of a multilayer stack, wherein all of the layers are cured simultaneously in a spin application tool porous dielectric layer.

Abstract: The adhesion properties of a metal interconnect structure are enhanced by selectively depositing a barrier layer component having good adhesion to an underlying metal on the bottom surface of a via. Then, a further barrier layer having superior adhesion characteristics for the dielectric is formed on the dielectric sidewalls of the via, so that excellent adhesion to the dielectric and the underlying metal is achieved. The selectivity of the deposition may be accomplished by exploiting the capabilities of modem IPVD tools.

Abstract: A semiconductor device comprising: a base substrate including a semiconductor substrate 10 and a semiconductor element formed on the semiconductor substrate 10; an insulation film 22, 24, 26 formed on the base substrate having an opening 30, 32; and a metal interconnection 42 formed buried in the opening 30, 32 including: a barrier layer 34 formed on an inside wall and a bottom of the opening 30, 32; an adhesion layer 36 containing zirconium formed on the barrier layer 34; and a metal interconnection material 38, 40 containing copper as a main component formed on the barrier layer 36. Whereby the peeling of the copper interconnection in the fabrication process can be prevented. The electro migration resistance and stress migration resistance of the copper interconnection can be further improved.

Abstract: Conductive material is deposited by ionized physical vapor deposition on an insulator, possibly to contact a conductive layer exposed by an opening in the insulator. At the beginning of the deposition, the wafer bias is low (possibly zero), to prevent the insulator re-sputtering by the ionized conductive material as this material is being deposited. The contact resistance is improved (reduced) as a result.

Abstract: A via hole 18 is opened in an interlayer insulating film 17, which covers a lower layer interconnect 12, a protective film 19 is embedded on the base portion of the via hole 18, and a soluble resin 20, which dissolves in a resist developing fluid under unexposed conditions, is further embedded thereupon. On this basis, a photoresist 21 is applied, and this photoresist 21 is subjected to an exposure and a development process so as to form a resist pattern 21a, which has an aperture window in a region including the via hole. Upon formation of an interconnective trench in the interlayer insulating film 17 utilizing the resist pattern 21a, a dual damascene structure is formed by embedding a metallic material into the vial hole and interconnective trench.

Abstract: A method for preventing peeling of a metal layer formed over a semiconductor wafer process surface during a chemical mechanical polishing (CMP) process including providing a semiconductor wafer having a process surface comprising a periphery portion and a central portion said central portion including active areas having semiconductor devices features formed therein the process surface including a dielectric insulating layer; forming a plurality of openings in the periphery portion to form closed communication with the dielectric insulating layer the plurality of openings having an aspect ratio of at least 2; blanket depositing a metal layer to cover the process surface including the periphery portion to include filling the plurality of openings to anchor the metal layer; and, performing a CMP process to remove at least a portion of the metal layer from the process surface.

Abstract: A method of forming a boride layer for integrated circuit fabrication is disclosed. In one embodiment, the boride layer is formed by chemisorbing monolayers of a boron-containing compound and one refractory metal compound onto a substrate. In an alternate embodiment, the boride layer has a composite structure. The composite boride layer structure comprises two or more refractory metals. The composite boride layer is formed by sequentially chemisorbing monolayers of a boron compound and two or more refractory metal compounds on a substrate.

Abstract: According to one embodiment of the invention, a method for providing improved layer adhesion in a semiconductor is provided. The method includes forming a dielectric layer. The method also includes forming a layer of metal in direct contact with the dielectric layer. The method also includes directly exposing the layer of metal, after forming the layer of metal, to plasma at a power level sufficient to penetrate through the layer of metal and reach the dielectric layer.

Abstract: Poorly adherent layers such as silicon nitride and silicon dioxide exhibit improved adhesion to copper member by providing an intervening germanium-containing layer. The germanium-containing layer is copper germanide, germanium oxide, germanium nitride or combinations thereof. The germanium-containing layer enhances the adhesion such that the poorly adherent layer is less susceptible to delamination from the copper member.

Abstract: The present invention relates to an electroless-plating liquid useful for forming a protective film for selectively protecting surface of exposed interconnects of a semiconductor device which has an embedded interconnect structure formed by an electric conductor, such as copper or silver, embedded in fine recesses for interconnects formed in a surface of a semiconductor substrate, and also to a semiconductor device in which surfaces of exposed interconnects are selectively protected with a protective film. The electroless-plating liquid contains cobalt ions, a complexing agent and a reducing agent containing no alkali metal.

Abstract: A new method is provided for the creation of an adhesion/barrier layer over which a tungsten interconnect is created. The invention reduces metal extrusion and effects of pin-holes by dividing the process of barrier material of TiN deposition into phases, whereby after about half the thickness of the required layer of TiN has been deposited, an intermediate and very thin layer of Ti is deposited. After the thin layer of Ti has been deposited, the deposition of the barrier layer of TiN is continued to the point where the required thickness for the layer of TiN has been reached.

Abstract: A method for forming a semiconductor structure includes supplying a structure having an exposed last metalization layer, cleaning the last metalization layer, forming a silicide in a top portion of the last metalization layer and forming a terminal over the silicide.

Abstract: A method for a metal etchback process to form a metal filled semiconductor feature having improved planarity and electrical resistance including a semiconductor wafer having an etched opening lined with a refractory metal containing layer and a blanket deposited metal layer filling the etched opening; spin coating a spin on layer selected from the group consisting of an organic resinous layer and a spin-on glass layer over the metal layer; dry etching in a first etchback process to remove a first portion of the SOL layer to reveal a portion of the metal layer leaving a second portion of the SOL layer overlying the etched opening; dry etching in a second etchback process to remove the metal layer to reveal a portion of the refractory metal containing layer; and, removing the second portion of the SOL layer to form a substantially planar metal filled etched opening.

Abstract: A method for manufacturing a semiconductor device is provided including: a step of forming a solid barrier metal layer on an interlayer insulating film; a removing step of removing at least a part of the solid barrier metal layer located at a place at which a pad opening portion is to be formed; a step of forming a solid second Al alloy film on the interlayer insulating film exposed in the removing step described above and the solid barrier metal layer; a step of patterning the solid second Al alloy film and the solid barrier metal layer so as to form a bonding pad portion on the interlayer insulating film; a step of forming a passivation film on the bonding pad portion and the interlayer insulating film; and a step of forming the pad opening portion in the passivation film at a position located on the bonding pad portion.

Abstract: A process for reducing the risk of removing metal from an underlying metal structure during a dry etch procedure used to define a borderless, overlying metal line structure, has been developed. After formation of a damascene type, underlying metal structure, deposition of an metal layer and of an overlying silicon oxide layer, is performed. A photoresist shape is used as an etch mask to allow formation of a partially etched metal line structure to be accomplished in the silicon oxide layer, and in a top portion of the metal layer. Insulator spacers are then formed on the sides of the partially etched metal line structure, resulting in a wider, partially etched metal line structure. The hard mask now presented by the defined silicon oxide component of the partially etched metal line structure, is then used as an etch mask allowing a final metal line structure, wider than the partially etched metal line structure, to be obtained.

Abstract: A method of adhering a silicate layer to dielectric layer comprising the following steps. A structure having an overlying dielectric layer formed thereover is provided. An adhesion promoter layer is formed upon the dielectric layer. The adhesion promoter layer including adhesion promotion molecules. The dielectric layer and the adhesion promoter layer are treated to a low-temperature treatment to bind at least some of the adhesion promotion molecules to the dielectric layer. A silicate layer is formed upon the low-temperature treated adhesion promoter layer. The silicate layer and the low-temperature treated adhesion promoter layer are treated to a high-temperature treatment to bind at least some of the adhesion promotion molecules to the silicate layer whereby the silicate layer is adhered to the dielectric layer.

Abstract: Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces via resistance problems during thermal cycles of semiconductor wafers embodying multiple levels of metal and organic interlevel dielectrics.

Abstract: In a semiconductor device with a via contact including a barrier metal layer and a method for fabricating the same, a lower metal interconnection is formed over a substrate. An ILD is formed on the lower metal interconnection and has a lower barrier layer and an upper barrier layer that have an etch selectivity with respect to each other. An upper metal interconnection is formed over the ILD and is separated from the lower metal interconnection by the ILD. A via contact plug penetrates the ILD to connect the lower and upper metal interconnections. The via contact plug is formed such that a portion crossing the lower barrier layer is formed to have a greater width as compared to a portion crossing the upper barrier layer. The barrier metal layer, which is formed to encompass sidewalls and a bottom of an inner metal layer of the via contact plug, forms a discontinuous part which does not exist at the portion crossing the lower barrier layer.

Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.

Abstract: A method of manufacturing a semiconductor device comprising forming a protective film on a surface of a lower-layer interconnection, and forming a multilayer-structured film by stacking a first porous film, a first non-porous film, a second porous film, and a second non-porous film on a surface of the protective film in this order, and forming a via hole and an interconnect trench. After a resist mask is removed, protective film exposed at a bottom of the via hole is removed. An upper-layer interconnection of dual damascene structure is formed by embedding an interconnect material in the via hole and the interconnect trench.

Abstract: Methods are provided for processing a substrate for depositing an adhesion layer having a low dielectric constant between two low k dielectric layers. In one aspect, the invention provides a method for processing a substrate including depositing a barrier layer on the substrate, wherein the barrier layer comprises silicon and carbon and has a dielectric constant less than 4, depositing a dielectric initiation layer adjacent the barrier layer, and depositing a first dielectric layer adjacent the dielectric initiation layer, wherein the dielectric layer comprises silicon, oxygen, and carbon and has a dielectric constant of about 3 or less.

Abstract: A barrier material that is particularly suited as a barrier layer in copper interconnects structures found in semiconductor structures. The barrier layer contains one or more regions with one region containing at least 50 atom percent of a copper interface metal. The copper interface metal is selected from ruthenium, rhodium, palladium, silver, gold, platinum, iridium, selenium, tellurium, or alloys thereof. The barrier layer also contains a dielectric interface material.

Abstract: In a semiconductor device using a polysilicon contact, such as a poly plug between a transistor and a capacitor in a container cell, an interface is provided where the poly plug would otherwise contact the bottom plate of the capacitor. The interface bars silicon from the plug from diffusing into the capacitor's dielectric. The interface can also include an oxygen barrier to prevent the poly plug from oxidizing during processing. Below the interface is a silicide layer to help enhance electrical contact with the poly plug. In a preferred method, the interface is created by selectively depositing a layer of titanium over a recessed poly plug to the exclusion of the surrounding oxide. The deposition process allows for silicidation of the titanium. The top half of the titanium silicide is then nitridized. A conformal ruthenium or ruthenium oxide layer is subsequently deposited, covering the titanium nitride and lining the sides and bottom of the container cell.

Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate, forming an insulating film having a opening, forming a titanium film so as to extend from the semiconductor substrate in the opening to the insulating film surface, plasma treating the titanium film with a mixed gas of hydrogen and nitrogen; and forming a titanium nitride on the titanium film. Accordingly, the method can decrease a contact resistance of the tungsten interconnection in a contact hole.

Abstract: A multi-layered dielectric layer wherein the adhesion characteristic of an insulating layer including a Si—CH3 bond is improved, and a method of forming the same are provided. The multi-layered dielectric layer is formed on conductive patterns and includes a first insulating layer formed of a layer having a low dielectric constant including the Si—CH3 bond. In order to improve the adhesion characteristic of the first insulating layer, an adhesion surface is formed on the surface of the first insulating layer by treating the first insulating layer with plasma. In an alternative, the adhesion characteristics of the first insulating layer is improved by forming a buffer layer on the first insulating layer so that dipole—dipole interaction occurs between the first insulating layer and the buffer layer.

Abstract: The electromigration resistance of nitride capped Cu lines is significantly improved by treating the exposed planarized surface of inlaid Cu with a plasma containing NH3, depositing a silicon nitride capping layer at reduced temperatures, and then laser thermal annealing in N2 to densify the silicon nitride capping layer. The resulting silicon nitride capping layer also exhibits improved barrier resistance to Cu migration and improved etch stop properties. Embodiments include Cu dual damascene structures formed in dielectric material dielectric constant (k) less than about 3.9.

Abstract: A semiconductor device structure and method for manufacture includes a substrate having a top first layer of dielectric material; a second layer of material selected from the group including: amorphous Silicon (a-Si), amorphous Ge (a-Ge) or alloys thereof, located on top of the first layer; and, a third layer located on top of the a-Si, a-Ge, or alloys thereof layer, wherein the second layer provides adhesion between the first and third layers of the structure. Additionally, a semiconductor device structure and method for manufacture includes an insulating structure comprising a multitude of dielectric and conductive layers with respective a-Si, a-Ge, or alloys thereof bonding layers disposed to enhance adhesion between the different layers.

Abstract: Structures and processes are disclosed for reducing electrical contact resistance between two metal layers. Specifically, a resistive aluminum oxide layer forms spontaneously on metal lines including aluminum, within a V-shaped contact via which is opened in an insulating layer through a mask. The mask includes an opening with a width of less than about 0.75 &mgr;m. After removing the mask, the via is treated with an RF etch. The resultant contact has a width at the bottom of less than 0.9 &mgr;m. A titanium layer of 300 Å to 400 Å is deposited into the via, with about 60 Å to 300 Å reaching the via bottom and reacted with the underlying aluminum. The reaction produces a titanium-aluminum complex (TiAlx) with a thickness of about 150 Å to 900 Å. Advantageously, this composite layer provides a low resistivity contact between the aluminum-containing layer and a subsequently deposited metal layer.

Abstract: A bond pad of a semiconductor device capable of restraining dishing and having improved conductivity by a damascene technique using a copper pattern, includes first and second copper patterns of irregular lattice models, first and second dielectric layer patterns to connect the first and second copper patterns in the vertical direction, a line connection structure horizontally connecting the first and second copper patterns, and a conductivity improving layer formed on the first and second copper patterns. Dishing generated in planarizing the first and second copper patterns by a damascene technique can be restrained due to the first and second copper patterns of the lattice models. Also, the conductivity property of the bond pad can be improved by connecting the first and second copper patterns horizontally and in the vertical direction and further forming the conductivity improving layer on the first and second copper patterns.