Having Adhesion Promoting Layer Patents (Class 438/628)
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Patent number: 6339025Abstract: A method of fabricating a copper capping layer. A silicon rich nitride layer is formed on an exposed copper layer. Since the silicon rich nitride layer has more dangling bonds inside, the silicon in the silicon rich nitride layer easily reacts with the copper and a copper silicide layer is formed between the copper and the silicon rich nitride layer. Therefore, adhesion of the copper and the silicon rich nitride layer can be improved.Type: GrantFiled: April 3, 1999Date of Patent: January 15, 2002Assignee: United Microelectronics Corp.Inventors: Chih-Chien Liu, Kun-Chih Wang, Wen-Yi Hsieh, Yimin Huang
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Patent number: 6333276Abstract: A semiconductor device according to the present invention includes insulating branches which are formed as an interlayer insulating film on a semiconductor substrate. The interlayer insulating film has holes (voids) between the branches to thereby reduce electrostatic capacitance between stacked layers within a semiconductor device.Type: GrantFiled: October 26, 2000Date of Patent: December 25, 2001Assignee: NEC CorporationInventor: Shirou Morinaga
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Patent number: 6326297Abstract: Tungsten nitride adhesion to an underlying dielectric is enhanced by forming a thin layer of silicon over the dielectric before depositing the tungsten nitride. A twenty angstrom layer of amorphous silicon is formed over a silicon oxide dielectric. Tungsten nitride is formed over the silicon layer using a plasma enhanced chemical vapor deposition with tungsten hexafluoride and nitrogen. As the tungsten nitride is formed, the tungsten hexafluorine and nitrogen reacts with the amorphous silicon to produce an adhesion layer that includes silicon nitride and tungsten silicide.Type: GrantFiled: September 30, 1999Date of Patent: December 4, 2001Assignee: Novellus Systems, Inc.Inventor: Anil Justin Vijayendran
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Patent number: 6323119Abstract: The present invention provides a method of depositing an amorphous fluorocarbon film using a high bias power applied to the substrate on which the material is deposited. The invention contemplates flowing a carbon precursor at rate and at a power level so that equal same molar ratios of a carbon source is available to bind the fragmented fluorine in the film thereby improving film quality while also enabling improved gap fill performance. The invention further provides for improved adhesion of the amorphous fluorocarbon film to metal surfaces by first depositing a metal or TiN adhesion layer on the metal surfaces and then stuffing the surface of the deposited adhesion layer with nitrogen. Adhesion is further improved by coating the chamber walls with silicon nitride or silicon oxynitride.Type: GrantFiled: October 10, 1997Date of Patent: November 27, 2001Assignee: Applied Materials, Inc.Inventors: Ming Xi, Turgut Sahin, Yaxin Wang
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Publication number: 20010035582Abstract: A hard mask, e.g., a silicon dioxide or silicon nitride film, is used to avoid organic polymer materials in copper plasma etch applications. The hard mask would be deposited as a blanket layer on the Cu metal layer and itself be patterned and etched with a conventional photolithographic resist pattern. The hard mask etch is stopped shortly before the Cu surface is exposed. Halting the hard mask etch before the Cu surface is exposed facilitates the use of conventional cleaning processes following the hard mask etch. The remaining thin layer of hard mask can be etched through during the beginning of the Cu metal etch process. Any remaining hard mask deposited on the Cu metal layer can form a part of a new dielectric layer.Type: ApplicationFiled: May 25, 1999Publication date: November 1, 2001Inventors: MARK RICHARD TESAURO, PETER D. NUNAN
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Patent number: 6306761Abstract: A hard Al oxide film having a high melting point, which grows on the surface of an Al—Cu film during a wafer is carried in atmospheric air, obstructs the burying of a viahole with the Al—Cu film by high pressure reflow, with a result that a void remains in the hole. The present invention is intended to remove such an Al oxide film grown on the Al—Cu film formed by sputtering, by Ar+ sputtering/etching directly before high pressure reflow. Moreover, when a Ti oxide film is present on the surface of a Ti based underlying film formed by CVD, an Al oxide film is possibly grown at the boundary between the Ti based underlying film and an Al—Cu film laminated thereon. In this case, the Ti oxide film is similarly removed directly before formation of the Al—Cu film, thereby preventing the growth of the Al oxide film.Type: GrantFiled: April 25, 1996Date of Patent: October 23, 2001Assignee: Sony CorporationInventor: Mitsuru Taguchi
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Publication number: 20010027012Abstract: A contact layer is used, for example, as a liner for the fabrication of electrical contacts in contact holes. The contact layer is fabricated in two steps, in a first step a first contact layer is deposited, in which only a small proportion of the particles to be sputtered is ionized. In a second sputtering step, a second contact layer is sputtered, in the course of whose fabrication a larger proportion of the particles to be sputtered is ionized. The procedure ensures that the first contact layer is disposed as a protective layer on the substrate by gentle sputtering before the second contact layer is sputtered.Type: ApplicationFiled: March 19, 2001Publication date: October 4, 2001Inventors: Sven Schmidbauer, Norbert Urbansky
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Patent number: 6297147Abstract: The present invention provides a method and apparatus for filling contacts, vias, trenches, and other patterns, in a substrate surface, particularly patterns having high aspect ratios. Generally, the present invention provides a method for removing oxygen from the surface of an oxidized metal layer prior to deposition of a subsequent metal. The oxidized metal is treated with a plasma consisting of nitrogen, hydrogen, or a mixture thereof. In one aspect of the invention, the metal layer is Ti, TiN, Ta, TaN, Ni, NiV, or V, and a subsequent wetting layer is deposited using either CVD techniques or electroplating, such as CVD aluminum (Al) or electroplating of copper (Cu). The metal layer can be exposed to oxygen or the atmosphere and then treated with a plasma of nitrogen and/or hydrogen in two or more cycles to remove or reduce oxidation of the surface of the metal layer and nucleate the growth of a subsequent metal layer thereon.Type: GrantFiled: June 5, 1998Date of Patent: October 2, 2001Assignee: Applied Materials, Inc.Inventors: Lisa Yang, Anish Tolia, Roderick Craig Mosely
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Patent number: 6297158Abstract: In the presently disclosed invention, a method is provided to avoid damage to a copper interconnect while subjecting the interconnect to chemical-mechanical polishing (CMP). First, a copper barrier layer is formed in a damascene structure. Then, prior to the deposition of copper metal into the damascene openings, a barrier layer is formed on the inside walls of the damascene structure. In a first embodiment, the copper barrier layer is deposited at high temperature. Then, it is cooled down in a prescribed manner. Subsequently, a copper seed layer is formed over the barrier, which is followed by the electro-chemical deposition (ECD) of copper, to form the copper damascene interconnect. Alternatively, in a second embodiment, the copper layer is formed at low temperature. Then it is annealed at a high temperature, followed by wafer cooling. Subsequently, copper seed layer is formed over the barrier layer. Next, ECD copper is formed in the damascene structure.Type: GrantFiled: May 31, 2000Date of Patent: October 2, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chung-Shi Liu, Shau-Lin Shue, Chen-Hua Yu
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Patent number: 6297146Abstract: A semiconductor, and manufacturing method therefor, is provided with a barrier/adhesion layer, having cobalt, nickel, or palladium for semiconductors having conductive materials of copper, silver or gold. The barrier/adhesion layer can be alloyed with between about 0.2% and 4% tantalum, molybdenum, or tungsten to increase barrier effectiveness and lower resistivity.Type: GrantFiled: September 5, 2000Date of Patent: October 2, 2001Assignee: Advanced Micro Devices, Inc.Inventor: Sergey D. Lopatin
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Publication number: 20010023987Abstract: Poorly adherent layers such as silicon nitride and silicon dioxide exhibit improved adhesion to copper member by providing an intervening germanium-containing layer. The germanium-containing layer is copper germanide, germanium oxide, germanium nitride or combinations thereof. The germanium-containing layer enhances the adhesion such that the poorly adherent layer is less susceptible to delamination from the copper member.Type: ApplicationFiled: May 7, 2001Publication date: September 27, 2001Inventors: Vincent J. Mcgahay, Thomas H. Ivers, Joyce Liu, Henry A. Nye
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Patent number: 6294458Abstract: The formation of an adhesion/interlayer region (410) of a semiconductor substrate device (404) before barrier layer (412) deposition provides improved adhesion of the barrier layer (412) to the underlying dielectric (404) and increases strength to the next interconnect layer without altering the function of the barrier layer (412) to limit Cu diffusion into the dielectric substrate (404). The adhesion/interlayer region (410) is formed in an inlaid structure (400, 500) of a semiconductor wafer. The inlaid structure (400, 500) is connected to upper or lower metal layers through vias in the dielectric layer (404) to a copper layer. The adhesion/interlayer region is formed by flowing a treating gas in a glow discharge process of the dielectric substrate in a chamber either attached or separated from the barrier deposition chamber (300). The barrier layer (412) and the adhesion/interlayer region (410) can be formed in this inlaid structure (400, 500) of a semiconductor wafer.Type: GrantFiled: January 31, 2000Date of Patent: September 25, 2001Assignee: Motorola, Inc.Inventors: Jiming Zhang, Dean J. Denning, Sam S. Garcia, Scott K. Pozder
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Publication number: 20010019125Abstract: First, a conductive material made of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer including a lower layer of Cr and an upper layer of aluminum-based material is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad, respectively. Next, an amorphous silicon layer is deposited, an annealing process is executed to form inter-layer reaction layers on the drain electrode, the gate pa and the data pad, which are exposed through the contact holes. Then, the amorphous silicon layer is removed.Type: ApplicationFiled: January 2, 2001Publication date: September 6, 2001Inventors: Mun-Pyo Hong, Sang-Gab Kim
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Patent number: 6284656Abstract: A typical integrated circuit interconnects millions of microscopic transistors and resistors with aluminum wires buried in silicon-dioxide insulation. Yet, aluminum wires and silicon-dioxide insulation are less attractive than copper wires and polymer-based insulation, which promise both lower electrical resistance and capacitance and thus faster, more efficient circuits. Unfortunately, current techniques cannot realize the promise because copper reacts with the polymer-based insulation to form copper dioxide within the polymer, reducing effectiveness of the copper-polymer combination. Accordingly, the inventor devised a method which uses a non-acid-precursor to form a polymeric layer and then cures, or bakes, it in a non-oxidizing atmosphere, thereby making the layer resistant to copper-dioxidizing reactions. Afterward, the method applies a copper-adhesion material, such as zirconium, to the layer to promote adhesion with a subsequent copper layer.Type: GrantFiled: August 4, 1998Date of Patent: September 4, 2001Assignee: Micron Technology, Inc.Inventor: Paul A. Farrar
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Patent number: 6271112Abstract: A method for reducing die loss in a semiconductor fabrication process which employs titanium nitride and HDP oxide is provided. In the fabrication of multilevel interconnect structures, there is a propensity for defect formation in a process in which titanium nitride and HDP oxide layers are in contact along the edge of a semiconductor substrate. A dielectric interlayer is provided which improves the interfacial properties between titanium nitride and HDP oxide and thereby reduces defects caused by delamination at the titanium nitride/HDP oxide interface.Type: GrantFiled: November 13, 1998Date of Patent: August 7, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Christopher L. Wooten, Craig W. Christian, Thomas E. Spikes, Jr., Allen L. Evans, Tim Z. Hossain
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Patent number: 6271121Abstract: A process for chemical vapor deposition of blanket tungsten thin films on titanium nitride proceeds by hydrogen reduction of tungsten hexafluoride at temperatures between 200° C. and 500° C. Tungsten film nucleation is preferably facilitated by a hydrogen plasma treatment of the titanium nitride surface of the substrate. The plasma treatment may be carried out in a separate etch chamber and transferred to a tungsten CVD chamber without intervening exposure to air, or, preferably, is carried out with a low energy etch performed with the substrate mounted on a susceptor in the chamber of the tungsten CVD reactor at which the tungsten film is to be applied.Type: GrantFiled: June 30, 1999Date of Patent: August 7, 2001Assignee: Tokyo Electron LimitedInventor: Douglas A. Webb
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Patent number: 6271122Abstract: There is provided a semiconductor device comprising, for example, a MOS structure having a low electrical resistance in contacts and local interconnects, and a method for fabricating the device. When openings are formed in a dielectric region of a MOS structure, the thin metal silicide layer on top of a drain/source region is diminished due to the limited selectivity of the etch process and the need to over-etch to obtain appropriate electrical contacts. Consequently, the contact resistance is increased resulting in an increased contact resistance. Therefore, a bilayer metal is deposited on the metal silicide layer and the surface of the openings, wherein the metal layer that is in contact with the metal silicide layer is preferably the same metal as the metal of the metal silicide layer. In a subsequent annealing process, the metal of the bilayer partially converts into metal silicide, thereby increasing the initial metal silicide layer and concurrently reducing the contact resistance.Type: GrantFiled: July 12, 1999Date of Patent: August 7, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Karsten Wieczorek, Michael Raab, Gert Burbach
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Patent number: 6265305Abstract: The present invention provides a method of preventing corrosion of a titanium layer in a semiconductor wafer. The semiconductor wafer comprises a dielectric layer, a column-shaped tungsten plug embedded in the dielectric layer and having its top surface cut to be at the same level as that of the dielectric layer, a titanium layer positioned on the top of the dielectric layer and covering a portion of the top surface of the tungsten plug, a main conductive layer positioned on the surface of the titanium layer, a photoresist layer positioned on the surface of the main conductive layer, and a polymer layer scattered on the surface of the semiconductor wafer. The method is first to utilize a dry cleaning process to strip off the photoresist layer and the polymer layer, then to perform a nitridizing process to make the surface of the titanium layer exposed on the surface of the semiconductor wafer generate a titanium nitride layer.Type: GrantFiled: October 1, 1999Date of Patent: July 24, 2001Assignee: United Microelectronics Corp.Inventors: Shih-Fang Tsou, Yu-Jen Chou, Cheng-Shun Hu
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Patent number: 6261943Abstract: Methods for fabricating a free-standing thin metal film are provided. In one method, a sacrificial silicon nitride membrane structure is provided comprising a silicon wafer having first and second surfaces, a first silicon nitride layer applied to the first surface of the silicon wafer and a second silicon nitride layer applied to the second surface of the silicon wafer. The second silicon nitride layer and the silicon wafer are etched to provide a window that exposes a predetermined area of the first silicon nitride layer, whereby the exposed predetermined area of the front silicon nitride layer comprises a sacrificial silicon nitride membrane unsupported by any auxiliary substrate over the predetermined area. A thin metal film is then deposited on the first silicon nitride layer. Finally, the sacrificial silicon nitride membrane is removed, whereby the portion of the thin metal film exposed by the removal of the silicon nitride membrane comprises the free-standing thin metal film.Type: GrantFiled: February 8, 2000Date of Patent: July 17, 2001Assignee: NEC Research Institute, Inc.Inventor: Daniel E. Grupp
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Patent number: 6258710Abstract: A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is deposited by chemical vapor deposition, or by physical vapor deposition in a layer less than about 800 angstroms.Type: GrantFiled: December 10, 1999Date of Patent: July 10, 2001Assignee: International Business Machines CorporationInventors: Hazara S. Rathore, Hormazdyar M. Dalal, Paul S. McLaughlin, Du B. Nguyen, Richard G. Smith, Alexander J. Swinton, Richard A. Wachnik
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Publication number: 20010006846Abstract: A structure and a method for providing structural stability at an interface between two poorly adhering layers in a semiconductor device involve providing anchoring channels in one of the poorly adhering layers through which the other poorly adhering layer can be anchored to a third layer. Specifically, the structure and method are applicable to a three-layer stack having a top layer of amorphous silicon, a middle layer of titanium nitride, and a bottom layer of oxide. In order to reduce susceptibility to delamination between the amorphous silicon layer and the titanium nitride layer, the anchoring channels are created in the titanium nitride layer to allow the amorphous silicon to attach to the oxide layer. Because the amorphous silicon layer and the oxide layer exhibit good adhesion between each other, delamination between the amorphous silicon layer and the titanium nitride layer is minimized.Type: ApplicationFiled: February 23, 2001Publication date: July 5, 2001Inventors: Min Cao, Jeremy A. Theil, Gary W. Ray, Dietrich W. Vook
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Patent number: 6251771Abstract: An embodiment of the instant invention is a method of forming an electronic device over a semiconductor substrate and having at least one level of metallic conductors, the method comprising the steps of: forming a dielectric layer over the semiconductor substrate, the dielectric layer having openings (step 102 of FIG. 1); forming a layer of the metallic conductor on the dielectric layer (step 104 of FIG. 1); removing a portion of the layer of the metallic conductor on the dielectric layer (step 106 of FIG. 1); and subjecting the exposed metallic conductor to a plasma which contains hydrogen or deuterium so as to passivate the metallic conductor (step 110 of FIG. 1). Preferably, the plasma contains a substance selected from the group consisting of: NH3, N2H2, H2S, and CH4, and the metallic conductors are comprised of a material selected from the group consisting of: copper, copper doped aluminum, Ag, Sn, Pb, Ti, Cr, Mg, Ta, and any combination thereof.Type: GrantFiled: February 22, 1999Date of Patent: June 26, 2001Assignee: Texas Instruments IncorporatedInventors: Patricia B. Smith, Girish A. Dixit, Eden Zielinski, Stephen W. Russell
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Patent number: 6251789Abstract: An embodiment of the instant invention is a method of fabricating a semiconductor device with a patterned dielectric layer having an upper surface and an opening with a bottom and sidewalls formed over a semiconductor substrate, the method comprising the steps of: forming a liner layer (layer 434 of FIGS. 1b-1d) on the upper surface of the patterned dielectric layer and on the bottom and the sidewalls of the opening in the patterned dielectric layer; forming a conductive layer (layer 436 of FIGS.Type: GrantFiled: December 16, 1999Date of Patent: June 26, 2001Assignee: Texas Instruments IncorporatedInventors: Arthur M. Wilson, Jody D. larsen
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Patent number: 6251772Abstract: A method for manufacturing an integrated circuit using damascene processes is provided in which dielectric surfaces subject to chemical-mechanical polishing are roughened after polishing to increase the surface area to provide more surface for chemical and mechanical bonding of subsequent layers.Type: GrantFiled: April 29, 1999Date of Patent: June 26, 2001Assignee: Advanced Micro Devicees, Inc.Inventor: Dirk Brown
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Patent number: 6245668Abstract: A method of forming inter-level contacts or vias between metal layers using a tungsten film deposited into the via using non-collimated sputter deposition. The sputter chamber is configured with a pressure of about 1 mTorr to about 10 mTorr with an inert gas flow of at least at least 25 cm3/min to about 150 cm3/min. Shielding inside the chamber is coated with a material, preferably, aluminum oxide, that promotes adhesion of tungsten to the shielding. An adhesion layer of titanium may be included prior to deposition of the tungsten film. Non-collimated sputter deposition increases the target to substrate distance inside the sputter chamber; reduces the heating effect associated with traditional collimated sputtering; and provides more robust diffusion barriers.Type: GrantFiled: September 18, 1998Date of Patent: June 12, 2001Assignee: International Business Machines CorporationInventors: Stephen B. Brodsky, William J. Murphy, Matthew J. Rutten, David C. Strippe, Daniel S. Vanslette
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Patent number: 6239021Abstract: An integrated circuit and a method for manufacturing therefor is provided in which a partial dual damascene deposition is performed to place a barrier, seed, and conductive layer in most of a via between two interconnect channels and then capping the via with a further barrier, seed, conductive layer to prevent electromigration between an interconnect channel and the via.Type: GrantFiled: September 5, 2000Date of Patent: May 29, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Shekhar Pramanick, Dirk Brown, John A. Iacoponi
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Patent number: 6239027Abstract: An improved method for photoresist residue is described. The method is used for preventing a material layer from being damaged by the photoresist residue. A semiconductor substrate is provided. An insulating layer is formed over the substrate. The patterned material layer is formed on the insulating layer. A thin dielectric layer is formed on the insulating layer and the material layer to protect the material layer. A patterned photoresist layer is formed on the dielectric layer. The insulating layer is defined. The photoresist layer is removed.Type: GrantFiled: February 24, 1999Date of Patent: May 29, 2001Assignee: United Microelectronics Corp.Inventors: Huang-Hui Wu, Tz-Ian Hung
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Patent number: 6211065Abstract: The present invention provides a method of depositing an amorphous fluorocarbon film using a high bias power applied to the substrate on which the material is deposited. The invention contemplates flowing a carbon precursor at rate and at a power level so that equal same molar ratios of a carbon source is available to bind the fragmented fluorine in the film thereby improving film quality while also enabling improved gap fill performance. The invention further provides for improved adhesion of the amorphous fluorocarbon film to metal surfaces by first depositing a metal or TiN adhesion layer on the metal surfaces and then stuffing the surface of the deposited adhesion layer with nitrogen. Adhesion is further improved by coating the chamber walls with silicon nitride or silicon oxynitride.Type: GrantFiled: October 10, 1997Date of Patent: April 3, 2001Assignee: Applied Materials, Inc.Inventors: Ming Xi, Eugene Tzou, Lie-Yea Cheng, Turgut Sahin, Yaxin Wang
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Patent number: 6207222Abstract: The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates a barrier layer deposited on all exposed surface of a dielectric layer which contains a dual damascene via and wire definition. A conductive metal is deposited on the barrier layer using two or more deposition methods to fill the via and wire definition prior to planarization. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.Type: GrantFiled: August 24, 1999Date of Patent: March 27, 2001Assignee: Applied Materials, Inc.Inventors: Liang-Yuh Chen, Rong Tao, Ted Guo, Roderick Craig Mosely
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Patent number: 6206269Abstract: The present invention relates to a method of soldering a semiconductor chip to a substrate, such as to a capsule in an RF-power transistor, for instance. The semiconductor chip is provided with an adhesion layer consisting of a first material composition. A solderable layer consisting of a second material composition is disposed on this adhesion layer. An antioxidation layer consisting of a third material composition is disposed on said solderable layer. The antioxidation layer is coated with a layer of gold-tin solder. The chip is placed on a solderable capsule surface, via said gold-tin solder. The capsule and chip are exposed to an inert environment to which a reducing gas is delivered and the capsule and chip are subjected to a pressure substantially beneath atmospheric pressure whilst the gold-tin solder is heated to a temperature above its melting point.Type: GrantFiled: October 1, 1999Date of Patent: March 27, 2001Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventor: Lars-Anders Olofsson
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Patent number: 6207554Abstract: It is the general object of the present invention to provide an improved method of fabricating semiconductor integrated circuit devices, specifically by describing an improved process of fabricating multilevel metal structures using low dielectric constant materials. The present invention relates to an improved processing methods for stable and planar intermetal dielectrics, with low dielectric constants. The first embodiment uses a stabilizing adhesion layer between the bottom, low dielectric constant layer and the top dielectric layer. The advantages are: (i) improved adhesion and stability of the low dielectric layer and the top dielectric oxide (ii) over all layer thickness of the dielectric layers can be reduced, hence lowering the parasitic capacitance of these layers. In the second embodiment, the method uses a multi-layered “hard mask” on metal interconnect lines with a silicon oxynitride DARC, dielectric anti-reflective coating on top of metal.Type: GrantFiled: July 12, 1999Date of Patent: March 27, 2001Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Yi Xu, Jia Zhen Zheng, Jane C. M. Hui, Charles Lin, Yih Shung Lin
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Patent number: 6204169Abstract: A process of polishing two dissimilar conductive materials deposited on semiconductor device substrate optimizes the polishing of each of the conductive material independently, while utilizing the same polishing equipment for manufacturing efficiency. A tungsten layer (258) and a titanium layer (256) of a semiconductor device substrate (250) are polished using one polisher (10) but two different slurry formulations. The two slurries can be dispensed sequentially onto the same polishing platen (132) from two different urce containers (111 and 112), wherein the first slurry is dispensed until e tungsten is removed and then the slurry dispense is switched to second slurry for removal of the titanium. In a preferred embodiment, the first slurry composition is a ferric nitrate slurry while the second slurry composition is an oxalic acid slurry.Type: GrantFiled: March 24, 1997Date of Patent: March 20, 2001Assignee: Motorola Inc.Inventors: Rajeev Bajaj, Janos Farkas, Sung C. Kim, Jaime Saravia
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Patent number: 6204179Abstract: Improved methods for filling openings in silicon substrates with copper and the metal interconnects so produced are provided. One method involves the use of a TixAlyNz barrier layer which is stable to the high temperatures required to reflow copper after PVD deposition. Another method involves the use of an aluminum wetting layer between a barrier layer and the copper which effectively lowers the temperature at which copper reflows and therefore allows the use of typical barrier layers.Type: GrantFiled: July 9, 1999Date of Patent: March 20, 2001Assignee: Micron Technology, Inc.Inventor: Allen McTeer
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Patent number: 6197681Abstract: A method for forming the copper interconnects is disclosed. The method includes, firstly, providing a semiconductor substrate is provided. Then, a first dielectric layer is formed. Sequentially, a second dielectric layer is formed and an anti-reflective layer is formed. Then, a hardmask layer is formed. Etching of the hardmask layer is carried out. The photoresist layer is removed and another photoresist is replaced. The anti-reflective layer, the second dielectric layer and the first dielectric layer are all etched. The hardmask layer, the anti-reflective layer and the second dielectric layer are all etched. The photoresist layer, the hardmask layer and the anti-reflective layer are all removed. A first barrier layer is conformably formed on the sidewalls and the exposed surfaces of the second dielectric layer and the first dielectric layer, and on the surface of the first copper layer. A seed layer is conformably formed on the barrier layer.Type: GrantFiled: December 31, 1999Date of Patent: March 6, 2001Assignee: United Microelectronics Corp.Inventors: Chih-Chien Liu, Cheng-Yuan Tsai, Ming-Sheng Yang
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Patent number: 6184130Abstract: A new method of tungsten plug metallization using a silicide glue layer is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer is provided covering the semiconductor device structures wherein a contact opening is made through the insulating layer to one of the semiconductor device structures. A silicide layer is deposited conformally over the surface of the insulating layer and within the contact opening as a combined ohmic contact and glue layer. In a first embodiment, a tungsten layer is deposited overlying the silicide layer. The tungsten layer not within the contact opening is removed to complete the formation of the tungsten plug metallization. In a second embodiment, the silicide layer not within the contact opening is selectively removed and a tungsten layer is selectively deposited overlying the silicide layer within the contact opening to complete formation of the tungsten plug metallization in the fabrication of an integrated circuit.Type: GrantFiled: November 6, 1997Date of Patent: February 6, 2001Assignee: Industrial Technology Research InstituteInventors: Tzu-Kun Ku, Hsueh-Chung Chen, Chine-Gie Lou
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Patent number: 6180509Abstract: A method is provided for forming planar multilevel metallization of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Multilevel metallization is achieved through a planar process at each layer to allow for minimum widths of lines and vias and minimal lateral spacing between lines. Conductive lines and contacts are formed before planarization to further achieve good step coverage. A first metallization layer is formed by depositing aluminum over the integrated circuit, patterning and etching to form metal interconnect lines. Regions of planar insulating material are then formed between the metal lines. Another layer of aluminum is deposited and etched to form metal vias over selected portions of the metal lines. This layer of aluminum is patterned with a reverse pattern of that used to pattern the metal lines. Again, regions of planar insulating material are formed between the metal vias.Type: GrantFiled: November 25, 1997Date of Patent: January 30, 2001Assignee: STMicroelectronics, Inc.Inventors: Kuei-Wu Huang, Tsiu C. Chan, Jamin Ling
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Patent number: 6177342Abstract: An multi-level interconnection uses a glue layer material as a via plug or contact plug. An method of forming the multi-level interconnection includes: forming a first opening and a wider second opening in a dielectric layer, whereas the first opening exposes the conductive layer and the second opening is above the first opening; and filling the first opening with titanium, titanium nitride or tungsten nitride.Type: GrantFiled: May 8, 1998Date of Patent: January 23, 2001Assignee: United Microelectronics CorpInventors: Tzung-Han Lee, Li-Chieh Chao
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Patent number: 6174804Abstract: A dual damascene process for forming interconnects such as contact plugs or vias. A first metal line is formed on a substrate structure. A first metal line is formed on the substrate structure. At least a stud is formed to cover a part of the first metal line. An insulation layer is formed to cover the substrate structure, the first metal line and the stud. A part of the insulation layer is removed to expose the stud. The expose stud is removed to form a contact window to expose the part of the first metal line. A metal layer is formed to fill the contact window.Type: GrantFiled: September 24, 1998Date of Patent: January 16, 2001Assignee: United Microelectronics Corp.Inventor: Chen-Chung Hsu
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Patent number: 6169024Abstract: A method of forming an interconnection that includes introducing a barrier material in a via of a dielectric to a circuit device on a substrate in such a manner to deposit the barrier material on the circuit device, introducing a seed material into the via in manner that leaves the barrier material overlying the circuit device substantially exposed, substantially removing the barrier material overlying the circuit device, and introducing a conductive material into the via to form the interconnection.Type: GrantFiled: September 30, 1998Date of Patent: January 2, 2001Assignee: Intel CorporationInventor: Makarem A. Hussein
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Patent number: 6165894Abstract: The adhesion of a diffusion barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member with an ammonia plasma followed by depositing the diffusion barrier layer on the treated surface. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, treating the exposed surface of the Cu/Cu alloy interconnect with an ammonia plasma, and depositing a silicon nitride diffusion barrier layer directly on the plasma treated surface.Type: GrantFiled: August 10, 1998Date of Patent: December 26, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Shekhar Pramanick, Takeshi Nogami, Minh Van Ngo
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Patent number: 6153523Abstract: The adhesion of a barrier or capping layer to a Cu or Cu alloy interconnect member is significantly enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member, after CMP, with an ammonia-containing plasma and then depositing the capping layer, e.g., silicon nitride, under high density plasma conditions at an elevated temperature, such as about 450.degree. C. to about 650.degree. C., e.g. about 450.degree. C. to about 550.degree. C. High density plasma deposition at such elevated temperatures increases the surface roughness of the exposed Cu metallization, thereby further increasing adhesion of the silicon nitride capping layer and increasing the density of the silicon nitride capping layer, thereby improving its etch stop characteristics.Type: GrantFiled: December 9, 1998Date of Patent: November 28, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Minh Van Ngo, Robin W. Cheung
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Patent number: 6150259Abstract: A method for forming a metal plug is provided. The method is used to form a metal plug without a hole on a glue/barrier layer within a trench when the glue/barrier layer has been formed for a while. A substrate with a trench therein and a glue/barrier layer formed conformal to the profile of the substrate is provided. A post-treatment is performed on the glue/barrier layer to prevent moisture absorption and to make the glue/barrier become dense. The post-treatment comprises a plasma treatment or a deep UV plus laser treatment. After performing the post-treatment step, a metal layer is formed on the glue/barrier layer at least to fill in the trench. The metal layer other than that filling the trench is removed to form a metal plug.Type: GrantFiled: November 13, 1998Date of Patent: November 21, 2000Assignee: United Microelectronics Corp.Inventors: Kun-Lin Wu, Horng-Bor Lu
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Patent number: 6140223Abstract: A thin conductive layer is formed on a contact hole bottom and on a contact hole sidewall in an insulating layer on an integrated circuit substrate, and then both chemical vapor deposition and physical vapor deposition are performed, to form a glue layer on the thin conductive layer. By performing both chemical vapor deposition and physical vapor deposition, the desirable characteristics of both processes may be obtained and the drawbacks in each of these processes may be compensated. Preferably, chemical vapor deposition of a material is performed, and physical vapor deposition of the same material is performed, to form the glue layer on the thin conductive layer. More particularly, chemical vapor deposition of titanium nitride, and physical vapor deposition of titanium nitride may be performed to form the glue layer on the thin conductive layer. As an alternative to titanium nitride, tungsten nitride may be used.Type: GrantFiled: October 20, 1998Date of Patent: October 31, 2000Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong-Seok Kim, Joo-Wook Park
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Patent number: 6140224Abstract: A dielectric layer and a polishing stop layer are respectively formed over a substrate. A glue layer composed of titanium (Ti) is formed along the surface of the dielectric layer. The Ti layer serves as adhension promotion to the subsequent TiN layer. A titanium-nitride (TiN) layer is next formed on the Ti layer to act as a barrier layer. A tungsten layer is deposited on the TiN layer. An etching back step is carried to etch the tungsten layer, therby leaving the tungsten in the contact holes to form the tungsten plug. Non-metal or oxide CMP is used to removes tungsten residues and TiN/Ti layers and the CMP will stop on the polishing stop layer.Type: GrantFiled: April 19, 1999Date of Patent: October 31, 2000Assignee: Worldiwide Semiconductor Manufacturing CorporationInventor: Ching-Fu Lin
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Patent number: 6140236Abstract: A metal interconnect layer that fills in a via hole formed by first depositing a first Al--Cu film on the sidewalls of the via hole at a low temperature and a low sputtering power and then depositing a second Al--Cu film on the first Al--Cu film at a high temperature and high sputtering power. Sputtering is performed in two steps at low and high temperatures within the same sputtering chamber. The deposition at low temperature and low sputtering power provides good coverage in the via hole, and the deposition at high temperature and high sputtering power reduces the process time.Type: GrantFiled: April 21, 1998Date of Patent: October 31, 2000Assignees: Kabushiki Kaisha Toshiba, Siemens Microelectronics, Inc., International Business Machines CorporationInventors: Darryl Restaino, Chi-Hua Yang, Hans W. Poetzlberger, Tomio Katata, Hideaki Aochi
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Patent number: 6133136Abstract: A structure comprising a layer of copper, a barrier layer, a layer of AlCu, and a pad-limiting layer, wherein the layer of AlCu and barrier layer are interposed between the layer of copper and pad-limiting layer.Type: GrantFiled: May 19, 1999Date of Patent: October 17, 2000Assignee: International Business Machines CorporationInventors: Daniel Charles Edelstein, Vincent McGahay, Henry A. Nye, III, Brian George Reid Ottey, William H. Price
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Patent number: 6130156Abstract: A method of fabricating an interconnect wherein there is initially provided a first layer of electrically conductive interconnect (3). A via (7) is formed which is defined by walls extending to the first layer of interconnect. A layer of titanium (9) is formed between the electrically conductive interconnect and the first layer of electrically conductive metal (11). A first layer of electrically conductive metal is formed on the walls of the via having a predetermined etch rate relative to a specific etch species and a second layer of electrically conductive metal (13) is formed on the first layer of electrically conductive metal having an etch rate relative to the specific etch species greater than the first layer and which preferably extends into the via.Type: GrantFiled: March 30, 1999Date of Patent: October 10, 2000Assignee: Texas Instruments IncorporatedInventors: Robert H. Havemann, Girish A. Dixit, Stephen W. Russell
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Patent number: 6117763Abstract: A method of making a semiconductor device includes forming a low permittivity dielectric layer over one or more conductive lines of a semiconductor device. The dielectric layer is made using a silicon-containing material having a relatively low permittivity including, for example, silicon oxyfluoride (SiO.sub.y F.sub.x) and hydrogen silsesquioxane (HSQ). An optional oxide layer may be formed over the dielectric layer. At least a portion of the dielectric layer and/or the optional oxide layer is subsequently removed to form a planar dielectric layer having a contaminated surface layer. The contaminated surface layer is due to exposure to water and is removed by, for example, exposing the surface to an acid, such as hydrofluoric acid.Type: GrantFiled: September 29, 1997Date of Patent: September 12, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Charles May, Robin Cheung
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Patent number: 6107185Abstract: A method for manufacturing an integrated circuit using damascene processes is provided in which dielectric surfaces subject to chemical-mechanical polishing are roughened after polishing to increase the surface area to provide more surface for chemical and mechanical bonding of subsequent layers.Type: GrantFiled: April 29, 1999Date of Patent: August 22, 2000Assignee: Advanced Micro Devices, Inc.Inventor: Todd P. Lukanc
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Patent number: 6100196Abstract: A method for making copper interconnections in an integrated circuit is described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.Type: GrantFiled: September 15, 1999Date of Patent: August 8, 2000Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Lap Chan, Jia Zhen Zheng