Abstract: A process for manufacturing a semiconductor device having a lower wiring layer, an interlayer insulating film and an upper wiring layer in this order and a connection hole formed in the interlayer insulating film on the lower wiring layer, wherein the connection hole is provided by the steps of: forming a photoresist layer on the interlayer insulating film; and forming in the photoresist layer an opening for the connection hole which exposes the interlayer insulating film at the bottom thereof and an opening for a dummy connection hole which does not expose the interlayer insulating film at the bottom thereof.

Abstract: A plug is formed of polysilicon, or other oxidizable conductor. Chemical-mechanical polishing is performed, with a polish stop layer defining the top of the dielectric layer. The upper portion of the polysilicon is oxidized to a controlled depth, then the oxidized portion is removed by an etch, followed by removal of the polish stop layer. The plug thus formed protrudes a controllable distance above the surrounding dielectric, providing good contact to subsequent conductive layers.

Abstract: Tungsten nitride adhesion to an underlying dielectric is enhanced by forming a thin layer of silicon over the dielectric before depositing the tungsten nitride. A twenty angstrom layer of amorphous silicon is formed over a silicon oxide dielectric. Tungsten nitride is formed over the silicon layer using a plasma enhanced chemical vapor deposition with tungsten hexafluoride and nitrogen. As the tungsten nitride is formed, the tungsten hexafluorine and nitrogen reacts with the amorphous silicon to produce an adhesion layer that includes silicon nitride and tungsten silicide.

Abstract: A first contact hole for a bit line is formed in an interlayer insulating film, and a polysilicon film is formed on the inner surface of the contact hole and on the interlayer insulating film. Subsequently, the polysilicon film is subjected to isotropic dry etching using a resist as a mask, and the interlayer insulating film is subjected to RIE etching, thereby forming a second contact hole in the interlayer insulating film in a peripheral circuit region. Then, a laminated film is formed on the inner surface of the second contact hole and on the polysilicon film, and the second contact hole is filled with a filling member. The laminated film and the polysilicon film are patterned, thereby forming a bit line in a memory cell region.

Abstract: A method of substantially reducing Si consumption and bridging during metal silicide contact formation comprising the steps of: (a) forming a metal silicon alloy layer over a silicon-containing substrate containing an electronic device to be electrically contacted, said silicon in said alloy layer being less than about 30 atomic % and said metal is Co, Ni or mixtures thereof; (b) annealing said metal silicon alloy layer at a temperature of from about 300° to about 500° C. so as to form a metal rich silicide layer that is substantially non-etchable compared to said metal silicon alloy or pure metal; (c) selectively removing any non-reacted metal silicon alloy over non-silicon regions; and (d) annealing said metal rich silicide layer under conditions effective in forming a metal silicide phase that is in its lowest resistance phase. An optional oxygen barrier layer may be formed over the metal silicon alloy layer prior to annealing step (b).

Abstract: Capping layer adhesion to a Cu or Cu alloy interconnect member is enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member with a hydrogen plasma to substantially reduce oxides thereon, forming a thin layer of copper silicide on the treated surface and depositing the capping layer thereon. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric layer, chemical-mechianiical polishing, hydrogen plasma treatment, reacting the treated surface with silane or dichlorosilane to form a layer of copper silicide on the treated surface and depositing a silicon nitride capping layer on the thin copper silicide layer.

Abstract: There is disclosed a triple well of a semiconductor device using SEG and method of forming the same.

Abstract: Poorly adherent layers such as silicon nitride and silicon dioxide exhibit improved adhesion to copper member by providing an intervening germanium-containing layer. The germanium-containing layer is copper germanide, germanium oxide, germanium nitride or combinations thereof. The germanium-containing layer enhances the adhesion such that the poorly adherent layer is less susceptible to delamination from the copper member.

Abstract: A process for PECVD of selected material films on a substrate comprising the steps of placing a substrate in a PECVD chamber and maintaining the chamber under vacuum pressure while introducing a precursor gas, a reactant gas, and an ionization enhancer agent into the chamber. A plasma is generated from the gases within the chamber. The energy generating the plasma causes the formation of charged species. The resulting charged species of the ionization enhancer agent assists in the formation of chemically reactive species of at least the precursor.

Abstract: A process for forming a metal silicide interconnect includes applying a layer of polysilicon over a semiconductor layer. A layer of amorphous silicon is formed over the layer of polysilicon followed by a layer of metal, such as titanium, over the layer of amorphous silicon. A second layer of amorphous silicon may also be formed over the layer of metal. The layer of titanium is reacted with the layer of amorphous silicon to form a small grain C49 layer of titanium silicide. The layer of polysilicon and the layer of titanium silicide are etched to form a desired interconnect structure. The small grain C49 layer of titanium silicide is then converted to the C54 phase.

Abstract: An improved method is provided for fabricating a cobalt silicide structure that includes the steps of: (1) forming a silicon structure, wherein a native oxide is located over a first surface of the silicon structure, (2) loading the silicon structure into a chamber, (3) introducing a vacuum to the chamber, (4) depositing a titanium layer over the first surface of the silicon structure, wherein the thickness of the titanium layer is selected to remove substantially all of the native oxide, (5) depositing a cobalt layer over the titanium layer, (6) depositing an oxygen impervious cap layer over the cobalt layer; and then (7) breaking the vacuum in the chamber, and (8) subjecting the silicon structure, the titanium layer, the cobalt layer and the cap layer to an anneal, thereby forming the cobalt silicide structure. The cap layer can be, for example, titanium or titanium nitride. The resulting cobalt silicide structure is substantially free from oxygen (i.e., oxide).

Abstract: The present invention is directed to a method of forming conductive interconnections in an integrated circuit device to optimize or at least maintain the speed at which signals propagate throughout the integrated circuit device. In one embodiment, the method comprises determining any variation in the size of a contact, as compared to its design size, and varying the size of a conductive line to be coupled to the contact based upon the variation in the size of the contact.

Abstract: A rapid thermal anneal (>600° C.) in a nitrogen-containing atmosphere is used to form a barrier TiN layer at the bottom of contact openings. To form source and drain contacts, contact openings are etched in a dielectric down to a titanium silicide layer on top of doped regions in the semiconductor (i.e. polysilicon or doped regions in the semiconductor substrate). The barrier TiN layer on the bottom of the contact openings is provided by a rapid thermal anneal in a nitrogen-containing atmosphere which converts the top part of the titanium silicide layer in the contact openings into a barrier TiN layer. This nitrogen-containing atmosphere contains nitrogen-containing species (e.g., N2, NH3, N2O) that react with titanium silicide to form TiN under the conditions provided by the rapid thermal anneal.

Abstract: There is provided a semiconductor device comprising, for example, a MOS structure having a low electrical resistance in contacts and local interconnects, and a method for fabricating the device. When openings are formed in a dielectric region of a MOS structure, the thin metal silicide layer on top of a drain/source region is diminished due to the limited selectivity of the etch process and the need to over-etch to obtain appropriate electrical contacts. Consequently, the contact resistance is increased resulting in an increased contact resistance. Therefore, a bilayer metal is deposited on the metal silicide layer and the surface of the openings, wherein the metal layer that is in contact with the metal silicide layer is preferably the same metal as the metal of the metal silicide layer. In a subsequent annealing process, the metal of the bilayer partially converts into metal silicide, thereby increasing the initial metal silicide layer and concurrently reducing the contact resistance.

Abstract: A method for lowering the anneal temperature required to form a multi-component material, such as refractory metal silicide. A shallow layer of titanium is implanted in the bottom of the contact area after the contact area is defined. Titanium is then deposited over the contact area and annealed, forming titanium silicide. A second embodiment comprises depositing titanium over a defined contact area. Silicon is then implanted in the deposited titanium layer and annealed, forming titanium silicide. A third embodiment comprises combining the methods of the first and second embodiments. In further embodiment, nitrogen, cobalt, cesium, hydrogen, fluorine, and deuterium are also implanted at selected times.

Abstract: A method of forming a metal silicide comprising contact over a substrate includes forming an opening in an insulative material to a substrate region with which electrical connection is desired. The opening has insulative sidewalls. The insulative sidewalls within the opening are coated with an electrically conductive material. The coating less than completely fills the opening. An example process is to deposit an elemental metal or metal alloy layer, and then nitridize it. Preferably, the substrate region comprises silicon which reacts with the metal layer during deposition to form a silicide of the metal(s). A preferred deposition comprised forming a plasma from source gases comprising TiCl4 and H2. A metal silicide layer is then substantially chemical vapor deposited on the conductive coating and over the substrate region relative to any exposed insulative material to fill remaining volume of the opening with the metal silicide.

Abstract: A semiconductor device has a thin semi-insulating polycrystalline silicon (SIPOS) film on the surface of a silicon substrate having a diffused region therein. The SIPOS film is thermally treated at the bottom of a via-plug of an overlying metallic film to form a metallic silicide for electrically connecting the via-plug with the diffused region, whereas the SIPOS film is maintained as it is for insulation on a dielectric film. The SIPOS film protects the diffused regions against over-etching to thereby improve the junction characteristics and provide a larger process margin for contacts between the metallic interconnects and the diffused regions.

Abstract: Cu interconnection patterns with improved electromigration resistance are formed by depositing a barrier metal layer, such as W or WN, to line an opening in a dielectric layer. The exposed surface of the deposited barrier metal layer is treated with silane or dichlorosaline to form a thin silicon layer thereon. Cu is then deposited to fill the opening and reacted with the thin silicon layer to form a thin layer of Cu silicide at the interface between Cu and the barrier metal layer, thereby reducing the interface defect density and improving electromigration resistance.

Abstract: The adhesion of a diffusion barrier or capping layer to Cu and/or Cu alloy interconnect members is significantly enhanced by treating the exposed surface of the Cu and/or Cu alloy interconnect members with a silane or dichlorosilane plasma to form a layer of copper silicide thereon prior to depositing the capping layer. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, treating the exposed surface of the Cu or Cu alloy interconnect member in a silane or dichlorosilane plasma to form the copper silicide layer and depositing a capping layer of silicon nitride thereon.

Abstract: A method for forming a metal/metal nitride layer. A dielectric layer is formed on a substrate comprising a conductive region. The dielectric layer comprises an opening exposing a portion of the conductive region. A conformal metal layer is formed on the dielectric layer by physical vapor deposition using a collimator to cover the exposed conductive region. A metal nitride layer is formed on the metal layer. A part of the metal layer may be exposed due to poor step coverage. An implanting process is performed on the metal nitride layer and on the exposed metal layer using a nitric gas.

Abstract: A liner material and method of use is disclosed. The method includes depositing a silicon layer into a deep void, such as a via or trench, and physical vapor depositing a cobalt seed layer onto the silicon. A supplemental cobalt layer is electroplated over the seed layer. The structure is then annealed, forming cobalt silicide (CoSix). The layer can be made very thin, facilitating further filling the via with highly conductive metals. Advantageously, the layer is devoid of oxygen and nitrogen, and thus allows low temperature metal reflows in filling the via. The liner material has particular utility in a variety of integrated circuit metallization processes, such as damascene and dual damascene processes.

Abstract: A method for forming a barrier metallization layer upon a semiconductor substrate. A semiconductor substrate is provided which has formed upon its surface a barrier metallization layer. The barrier metallization layer has formed in-situ upon its surface a silicon layer. The silicon layer has a thickness such that the contact resistance of the barrier metallization layer is not substantially increased. In a further embodiment, the barrier metallization layer and the silicon layer are sintered to form a metal silicide layer upon the surface of the barrier metallization layer.

Abstract: The present invention is a method for fabricating a gate of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with the gate having low resistivity. The MOSFET has a drain region, a source region, and a channel region fabricated within a semiconductor substrate, and the MOSFET initially has a gate comprised of a first metal silicide on polysilicon disposed on a gate dielectric over the channel region. Generally, the method of the present invention includes a step of depositing a first dielectric layer over the drain region, the source region, and the gate of the MOSFET. The present invention also includes steps of polishing down the first dielectric layer over the drain region and the source region, and of polishing down the first dielectric layer over the gate until the first metal silicide or the polysilicon of the gate is exposed.

Abstract: A new method of tungsten plug metallization using a silicide glue layer is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer is provided covering the semiconductor device structures wherein a contact opening is made through the insulating layer to one of the semiconductor device structures. A silicide layer is deposited conformally over the surface of the insulating layer and within the contact opening as a combined ohmic contact and glue layer. In a first embodiment, a tungsten layer is deposited overlying the silicide layer. The tungsten layer not within the contact opening is removed to complete the formation of the tungsten plug metallization. In a second embodiment, the silicide layer not within the contact opening is selectively removed and a tungsten layer is selectively deposited overlying the silicide layer within the contact opening to complete formation of the tungsten plug metallization in the fabrication of an integrated circuit.

Abstract: Low resistivity contacts are formed on source/drain regions and gate electrodes at a suitable thickness to reduce parasitic series resistances, thereby significantly reducing consumption of underlying silicon, while significantly reducing junction leakage. Embodiments include selectively depositing a metal layer, such as nickel, on the source/drain regions and on the gate electrode and ion implanting to form a barrier layer within the nickel layers which does not react with silicon or nickel silicide during subsequent solicitation. The barrier layer confines salicidation to the relatively thin underlayer layer of nickel, thereby minimizing consumption of underlying silicon while the unsilicidized overlying nickel on the barrier layer ensures low sheet resistivity.

Abstract: Disclosed are an apparatus and a method for manufacturing a semiconductor device. A Si wafer set within an L/UL chamber is transferred under the state of a high vacuum through a transfer chamber into a Ti chamber. The wafer is heated to at least 300° C. within the Ti chamber by a heating mechanism arranged within the Ti chamber. Then, a TiSix film is formed at a bottom portion of a contact hole by a plasma CVD method using an Ar gas supplied through a gas line as a carrier gas and a TiCl4 gas supplied through another gas line as a source gas, Ti in the source gas being self-aligned with Si in the wafer. The wafer having the TiSix film formed therein is transferred through the transfer chamber into a W chamber without being exposed to the air atmosphere. Within the W chamber, a W film is consecutively deposited by a selective CVD method on the TiSix film.

Abstract: A method of depositing metal silicide onto a semiconductor substrate includes a step of depositing, by a CVD process, a first metal silicide layer with silane gas onto the semiconductor substrate. The method also includes a step of thermally treating and chemically cleaning the semiconductor substrate. The method further includes a step of depositing, by the CVD process, a second metal silicide layer with silane gas onto the semiconductor substrate. By this method, cracks in the metal silicide formed on the semiconductor substrate are minimized.

Abstract: A process for forming a tungsten plug structure, in a narrow diameter contact hole, has been developed. The process features the use of a composite layer, comprised on an underlying titanium layer, and an overlying, first titanium nitride barrier layer, on the walls, and at the bottom, of the narrow diameter contact hole. After an RTA procedure, used to create a titanium silicide layer, at the bottom of the narrow diameter contact hole, a second titanium nitride layer is deposited, to fill possible defects in the underlying first titanium nitride, that may have been created during the RTA procedure. The tungsten plug structure is then formed, embedded by dual titanium nitride barrier layers.

Abstract: An improved semiconductor device which prevents a short circuit between a wiring layer and a semiconductor substrate, caused by the penetration of a contact hole, will be provided. A lower conducting layer is formed on a second interlayer insulating film. A third interlayer insulating film covers lower conducting layer. A contact hole is formed in third interlayer insulating film in order to connect an upper conducting layer and lower conducting layer. A stopper layer of silicide or metal is formed below contact hole between the surface of a semiconductor substrate and lower conducting layer.

Abstract: A contact is selectively formed in a contact hole in an insulating layer deposited on a silicon substrate. The contact hole exposes a portion of the substrate. The contact is formed by selectively forming a first layer of titanium silicide in the contact hole on the exposed portion of the substrate. A layer of titanium nitride is then selectively formed on the first layer of titanium silicide. A second layer of titanium silicide is thereafter selectively formed on the layer of titanium nitride to form the contact.

Abstract: A method of fabricating copper interconnection is provided comprising forming a dielectric layer with a trench or a via on a semiconductor substrate. A titanium layer is formed on the dielectric layer. A copper layer doped with light silicon is formed in the trench or the via. The copper layer is encapsulated by annealing to make silicon doped in the copper layer diffuse toward the surface of the copper to react with the titanium layer and the gas. It prevents the copper layer from oxidation and diffusion to increase the yield.

Abstract: A method of fabricating a self-align-contact is provided. A first gate and a second gate are formed on a semiconductor substrate. A spacer is formed on the sidewalls of the first gate and the second gate, and a source/drain region is formed between the first gate and the second gate. A dielectric layer is formed on the first gate, the second gate, the source/drain region, the spacer, and the semiconductor substrate. A self-align-contact opening is formed in the dielectric layer to expose the source/drain region. A metal silicide layer is formed on the source/drain region. A first conductive layer, such as doped polysilicon, is formed on the metal silicide layer and in the self-align-contact opening. A second conductive layer is formed on the first conductive layer, and the first conductive layer and the second conductive layer are patterned.

Abstract: A semiconductor processing method includes: a) providing a substrate having a base region to which electrical connection is to be made; b) providing a first layer of a conductive first material; c) providing an etch stop layer over the first layer; d) etching a contact opening through the etch stop and first layers to the base region; e) providing a second layer of first material outwardly of the etch stop layer and within the contact opening to a thickness greater than the first layer thickness and extending outwardly beyond the contact opening upper edge; f) removing first material of the second layer and defining a second layer plug within the contact, the second layer plug having an outermost surface extending outwardly beyond the contact opening upper edge and thereby providing the second layer plug to be of greater thickness than the first layer; g) masking outwardly of the first layer and the second layer plug to define a mask pattern for definition of a circuit component from the first layer which con

Abstract: In accordance with one embodiment of the invention, a diffusion barrier layer is formed in a copper interconnect structure by first forming a layer of intermetal dielectric material on an underlying layer of conductive material. A pattern of dual damascene structures is then formed in the interconnect dielectric layer. An adhesion layer is then formed on exposed sidewalls of the damascene structure and on the upper surface of the intermetal dielectric material. The adhesion-layer-lined dual damascene structures are then filled with a conductive material that includes copper. The copper-including conductive material is then planarized to the upper surface of the intermetal dielectric material. Intermetal dielectric material is then removed to expose the conductive material. A diffusion barrier material is then deposited on exposed surfaces of the conductive material.

Abstract: In a semiconductor device, a TiN plug is formed to filled up a contact hole which is formed to penetrate through an insulator film on a conductive silicon layer in a surface region of a silicon substrate. A first titanium silicide film is formed on a bottom surface of the TiN plug, so that the TiN plug is electrically connected to the conductive silicon layer through the first titanium silicide film. A second titanium silicide film is formed on a top surface of the TiN plug, and a polysilicon electrode is formed on the second titanium silicide film, so that the TiN plug is electrically connected to the polysilicon electrode through the second titanium silicide film. Thus, the contact resistance between the TiN plug and the polysilicon electrode is reduced.

Abstract: A microelectronic device includes a first region having a first conductivity type. A second region having a second conductivity type contacts the first region at a junction therebetween. A metal silicide region contacts the second region at a contact surface apart from the junction. Impurities of the second conductivity type in the second region are concentrated between the contact surface and the junction, for example, in one or more subregions disposed between the contact surface and the junction. The subregions may include a first subregion adjacent the junction formed by an ion implantation at a first energy level, and a second subregion disposed between the first subregion and the contact surface formed by a second ion implantation at a different energy level. Related fabrication methods are also provided.

Abstract: A method for making an embedded DRAM structure with logic circuits having high performance salicide FETs is achieved. After forming the DRAM FETs and the logic salicide FETs, a planar first insulating layer is deposited, and contact openings are etched and filled with tungsten (W) to form FET and bit-line contacts and to form DRAM capacitor node contacts. A first metal is patterned to form the first metal interconnections including the DRAM bit lines. A second insulating layer is deposited and planarized. Openings are etched to form first vias for the FET metal interconnections and concurrently to form openings for the DRAM capacitor bottom electrodes. The openings are filled with tungsten to form W contacts in the vias and to form bottom electrodes. A thin high-k dielectric is formed over the bottom electrodes, and a second metal is deposited and patterned to form capacitor top electrodes and a second level of metal interconnections.

Abstract: A layered trace configuration comprising a conductive trace capped with a silicide material which allows for removal of oxide polymer residues forming in vias used for interlayer contacts in a multilayer semiconductor device and eliminates or greatly reduces the formation of metal polymer residues in the vias. The formation of an interlayer contact according to one embodiment of the present invention comprises providing a trace formed on a semiconductor substrate and a silicide layer capping the conductive layer. An interlayer dielectric is deposited over the silicide capped trace and the substrate. A via is etched through the interlayer dielectric, wherein the etch is selectively stopped on the silicide layer. Any residue forming in the via is removed and a conductive material is deposited in the via to form the interlayer contact.

Abstract: According to one aspect of the invention, a method of fabricating N+ and P+ silicided gates limits diffusion when using a Tungsten, Titanium or Cobalt silicide in the gate fabrication. An example method involves doping a polysilicon structure in first and second dual gate regions and on either side of an undoped polysilicon region, forming a silicide is over the polysilicon structure, and then stuffing the undoped polysilicon region with a species selected to inhibit lateral diffusion of dopant from the polysilicon in the silicide. Subsequently, each gate is completed so that is includes a dielectric layer arranged over the silicide and one of the doped gate poly regions. Applications include logic circuits having embedded-DRAM, and circuits directed to stand-alone logic or stand-alone DRAM.

Abstract: A contact is selectively formed in a contact hole in an insulating layer deposited on a silicon substrate. The contact hole exposes a portion of the substrate. The contact is formed by selectively forming a first layer of titanium silicide in the contact hole on the exposed portion of the substrate. A layer of titanium nitride is then selectively formed on the first layer of titanium silicide. A second layer of titanium silicide is thereafter selectively formed on the layer of titanium nitride to form the contact.

Abstract: The invention includes methods of forming a conductive silicide layers on silicon comprising substrates, and methods of forming conductive silicide contacts. In one implementation, a method of forming a conductive silicide layer on a silicon comprising substrate includes reacting oxygen with silicon of a silicon comprising substrate to form oxides of silicon from silicon of the substrate. The oxides of silicon include stoichiometric silicon dioxide and substoichiometric silicon dioxide. The stoichiometric silicon dioxide and substoichiometric silicon dioxide are exposed to ozone to transform at least some of the substoichiometric silicon dioxide to stoichiometric silicon dioxide. After the exposing, a conductive metal silicide is formed in electrical connection with silicon of the silicon comprising substrate.

Abstract: The present invention provides a method of forming a contact structure comprised of: a silicon substrate, a titanium silicide layer, a barrier layer (i.e., TiN or TiNO), and a metal layer (e.g., Al or W). There are three embodiments of the invention for forming the titanium silicide layer and two embodiments for forming the barrier layer (TiN or TiNO). The first embodiment for forming a TiSix layer comprises three selective deposition steps with varying TiCl4: SiH4 ratios. After the TiSix contact layer is formed a barrier layer and a metal plug layer are formed thereover to form a contact structure. The method comprises forming a barrier layer 140 over the silicide contact layer 126; and forming a metal plug 160 over the TiN barrier layer 140. The metal plug 160 is composed of Al or W.

Abstract: A three elemental compound for diffusion barrier layer having a superior diffusion barrier characteristics manufactured by forming the compound between the silicon diffused into the diffusion barrier layer and the two elemental compound for diffusion barrier layer before the metal wire layer penetrates into the diffusion barrier layer to reach the underlying silicon layer, using the different characteristics of the diffusion rate as above, is disclosed. A method of forming three elemental compound for diffusion barrier layer according to the present invention comprises a silicon substrate. A silicide layer is deposited on the silicon substrate. A refractory metal nitride layer is then deposited on the silicide layer. A metal wire layer is deposited on the refractory metal nitride layer.

Abstract: Semiconductor device and method for fabricating the same, is disclosed, in which LDD regions and source/drain regions are provided with a silicide for reducing resistances to prevent short channel, the device including a gate insulating film and a gate electrode formed stacked on a prescribed region of a semiconductor substrate, sidewall spacers formed at both sides of the gate insulating film and the gate electrode, first impurity regions formed in surfaces of the semiconductor substrate under the sidewall spacers, second impurity regions formed in the semiconductor substrate on both sides of the sidewall spacers and the first impurity regions, first silicide films at surfaces of the first impurity regions, and second silicide films at surfaces of the gate electrode and the second impurity regions.

Abstract: A new process for creating a transistor in an integrated circuit provides for two suicide formations, each independent of the other, from two metal depositions and formations steps. The process produces a sufficiently low resistance silicide layer over the source/drain region surfaces of the transistor while also creating a lower resistance silicide over the gate interconnects. In an example embodiment of the invention a near-planar isolation process is used applied such that the gate interconnect surfaces are co-planar. A first silicide layer is formed over the source/drain regions. A dielectric gap-fill material is applied. A planarization method such as chemical mechanical polishing is used to remove the gap fill material down to the top surface of the gate interconnect. A relatively thick suicide is then formed over the top surface of the gate interconnect.

Abstract: Submicron contact holes in semiconductor bodies are metalized in a single operation. A titanium-rich layer is first deposited, which is followed by a low-resistance TiSi.sub.2 layer. The two layers are thus deposited in one contiguous CVD process inside a single CVD chamber.

Abstract: A semiconductor process in which a local interconnect, formed above a first transistor level, is connected to the first transistor level through a self-aligned and low resistivity contact structure. A semiconductor substrate is provided and a first transistor level formed on an upper surface of the semiconductor substrate. The first transistor level includes a first transistor. A local interconnect is then formed over the first transistor level. The local interconnect is vertically displaced above the first transistor level such that the local interconnect may traverse a gate of the first transistor without contacting the gate. A contact structure is then formed to connect the first source/drain structure of the first transistor with the local interconnect.

Abstract: A contact process interconnects poly-crystal silicon layer, and more particularly, this process dramatically decreases the voltage drop within a poly-crystal silicon layer. The advantages of the process include not only improvement in the interface quality of Poly-Si/SiO2 to decrease the junction damage but also do not increase its process complexity and its mask number during the fabrication of poly-crystal silicon thin-film SRAM to meet high integration requirement in VLSI.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: A method for forming a contact structure (10) which enables the use of ultra-shallow source/drain junctions begins by forming source and drain regions (14) and gate electrode (16). The source and drain regions (14) and the gate electrode (16) are silicided to form silicide regions (20). A conductive tungsten nitride etch stop layer (22) is formed overlying the silicide regions (20). Contact plug regions (28) are then formed to contact to the etch stop layer (22) and silicided regions (20). At this point, all of the silicide regions (20) are electrically short circuited. To remove this electric short circuit, an isotropic etch process comprising hydrogen peroxide, ammonium hydroxide, and water is used to remove portions of the tungsten nitride regions which are between the individual contact portions (28) in a self-aligned manner.