Abstract: A method for fabricating a dual damascene structure contains providing a substrate having a conductive layer, an etching stop layer, a dielectric layer, and a photoresist layer thereon, performing an etching process to remove a portion of the dielectric layer through a via pattern of the photoresist layer for forming a via structure in the dielectric layer, providing CO-containing gas to perform an ash process, filling GFP materials into the via structure, forming a photoresist layer with a trench pattern on the substrate, etching the dielectric layer through the trench pattern to form a trench structure in the dielectric layer, above the via structure, and removing the etching stop layer exposed in the via structure.

Abstract: A via hole is formed by a first step of forming an opening in a resin insulating film by laser radiation, a second step of forming an opening in said resin insulating film by dry etching and a third step of performing reverse sputtering in a plasma environment.

Abstract: Fabrication of microelectronic devices is accomplished using a substrate having a recessed pattern. In one approach, a master form is used to replicate a substrate having a pit pattern. In another approach, the substrate is produced by etching. A series of stacked layers having desired electrical characteristics is applied to the substrate and planarized in a manner that creates electrical devices and connections therebetween. The microelectronic devices can include a series of row and columns and are used to store data at their intersection.

Abstract: The present disclosure improves characteristics and reliability of a device by preventing seams within a copper layer, wherein seams are created when forming a copper line by a damascene process. Such seams created within a first and a second copper layer are prevented by a process in which the first copper layer and the second copper layer are deposited at constant speeds when the first copper layer is firstly formed only in a via hole by leaving a first copper seed layer only in the via hole, and then the second copper layer is formed in a trench by forming a second copper seed layer in the trench.

Abstract: An upper-layer metal power standard cell comprises: a basic power metal layer which is disposed in an upper layer of a circuit and which supplies a power voltage from an outside of the upper-layer metal power standard cell; a transistor element layer which is formed in a predetermined arrangement on a circuit substrate under the basic power metal layer; and an inner wire layer which supplies the power voltage to the transistor element layer disposed under the basic power metal layer disposed in the upper layer from the basic power metal layer.

Abstract: An epitaxial deposition process including a dry etch process, followed by an epitaxial deposition process is disclosed. The dry etch process involves placing a substrate to be cleaned into a processing chamber to remove surface oxides. A gas mixture is introduced into a plasma cavity, and the gas mixture is energized to form a plasma of reactive gas in the plasma cavity. The reactive gas enters into the processing chamber and reacts with the substrate, forming a thin film. The substrate is heated to vaporize the thin film and expose an epitaxy surface. The epitaxy surface is substantially free of oxides. Epitaxial deposition is then used to form an epitaxial layer on the epitaxy surface.

Abstract: In a dual damascene process to form a fine interconnection structure, a semiconductor manufacturing method includes: forming a first film to be etched on an insulating layer on a semiconductor substrate; forming a first mask film with an opening on the first film; forming a second film to be etched on the first mask film, burying the opening; forming a second mask film on the second film to be etched; forming an interconnection pattern in the second mask film in the upper portion of the opening; forming an interconnection pattern by etching the second film using the second mask film, forming a via pattern by etching the first film to be etched using the first mask film; and forming a via hole and an interconnection trench in the upper portion of the via hole in the insulating layer by selectively etching the insulating layer using the interconnection and via patterns.

Abstract: Methods of forming a metal line in a semiconductor device. A method includes: depositing a first etch stop layer, an interlayer insulating layer, a second etch stop layer, and a line insulating layer on a semiconductor substrate; forming a contact hole pattern on the line insulating layer; forming a contact hole by etching an exposed portion of the interlayer insulating layer using the contact hole pattern as a mask; forming a trench pattern on the line insulating layer; forming a trench by etching an exposed portion of the line insulating layer using the trench pattern as a mask; removing exposed portions of the first etch stop layer and the second etch stop layer after forming the contact hole and the trench; forming a first metal thin film within the contact hole; and forming a second metal thin film on the first metal thin film.

Abstract: A dual damascene process is provided. A dielectric layer is formed on a substrate and then a via opening is formed in the dielectric layer to expose a liner formed on the substrate. A gap fill (GF) layer is filled into the via opening and a resistant layer is formed on the substrate. A photolithographic process and an etching process are performed to form a trench in the dielectric layer and to remain the gap fill material having a top surface with a convex shape. In the etching process, an etching rate of the gap fill material layer is larger than that of the resistant layer. The gap fill material, the resistant layer, and the liner exposed by the via opening are removed. A conductive layer fills out the trench and the via opening. This invention is focusing on controlling etch-rate to avoid shielding effect when forming the composite opening.

Abstract: A technique is provided for protecting an interlayer insulating film formed of an organic low dielectric constant material from any damage applied in a semiconductor process, and for attaining the decrease leak current in the interlayer insulating film, resulting in the improvement of reliability of a semiconductor device. The semiconductor device according to the present invention has an organic insulating films having openings. The organic insulating films have modified portions facing the openings. The modified portions contains fluorine atoms and nitrogen atoms. The concentration of the fluorine atoms in the modified portions is lower than the concentration of the nitrogen atoms. The above-mentioned modified layers protect the semiconductor device from the damage applied in the semiconductor process, while suppressing the corrosion of the conductors embedded in the openings.

Abstract: A method of manufacturing a semiconductor device includes depositing a mask material to be patterned into a desired target pattern on an underlying material; patterning the mask material into a preparatory pattern including the target pattern and being larger than the target pattern; patterning the mask material into the target pattern; and processing the underlying material by using the mask material, which has been patterned, as a mask.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: A method includes forming a barrier layer on a substrate surface including at least one contact opening; forming an interconnect in the contact opening; and reducing the electrical conductivity of the barrier layer. A method including forming a barrier layer on a substrate surface including a dielectric layer and a contact opening, depositing a conductive material in the contact opening, removing the conductive material sufficient to expose the barrier layer on the substrate surface, and reducing the electrical conductivity of the barrier layer. An apparatus including a circuit substrate including at least one active layer including at least one contact point, a dielectric layer on the at least one active layer, a barrier layer on a surface of the dielectric layer, a portion of the barrier layer having been transformed from a first electrical conductivity to a second different and reduced electrical conductivity, and an interconnect coupled to the at least one contact point.

Abstract: This invention pertains to electronic/optoelectronic devices with reduced extended defects and to a method for making it. The device includes a substrate, a semiconductor active material deposited on said substrate, and electrical contacts. The semiconductor active material defines raised structures having atomically smooth surfaces. The method includes the steps of depositing a dielectric thin film mask material on a semiconductor substrate surface; patterning the mask material to form openings therein extending to the substrate surface; growing active material in the openings; removing the mask material to form the device with reduced extended defect density; and depositing electrical contacts on the device.

Abstract: A method of forming a metal wiring layer of a semiconductor device produces metal wiring that is free of defects. The method includes forming an insulating layer pattern defining a recess on a substrate, forming a conformal first barrier metal layer on the insulating layer pattern, and forming a second barrier metal layer on the first barrier metal layer in such a way that the second barrier metal layer will facilitate the growing of metal from the bottom of the recess such that the metal can fill a bottom part of the recess completely and thus, form damascene wiring. An etch stop layer pattern is formed after the damascene wiring is formed so as to fill the portion of the recess which is not occupied by the damascene wiring.

Abstract: A method is provided for depositing a conductive material in a sub-micron recessed feature formed on a substrate. The method begins by depositing a barrier layer over a dielectric layer disposed on the substrate while under a vacuum of the type found in a vacuum chamber. A catalytic layer is deposited over the barrier layer without breaking the vacuum. A conductive material layer is deposited over the catalytic layer by electroless deposition.

Abstract: By incorporating an etch control material after the formation of a material layer to be patterned, an appropriate material having a highly distinctive radiation wavelength may be used for generating a distinctive endpoint detection signal during an etch process. Advantageously, the material may be incorporated by ion implantation which provides reduced non-uniformity compared to etch non-uniformities, while the implantation process provides the potential for introducing even very “exotic” implantation species. In some embodiments, the substrate-to-substrate uniformity of the patterning of dual damascene structures may be increased.

Abstract: A method of forming a bit line of a semiconductor memory device is performed as follows. A first interlayer insulating layer is formed over a semiconductor substrate in which an underlying structure is formed. A region of the first interlayer insulating layer is etched to form contact holes through which a contact region of the semiconductor substrate is exposed. A low-resistance tungsten layer is deposited on the entire surface including the contact holes, thus forming contacts. A CMP process is performed in order to mitigate surface roughness of the low-resistance tungsten layer. The low-resistance tungsten layer on the interlayer insulating layer is patterned in a bit line metal line pattern, forming a bit line.

Abstract: The semiconductor device fabrication method according the present invention having, forming an interlayer dielectric film containing carbon above a semiconductor substrate, forming a protective film on that portion of the interlayer dielectric film, which is close to the surface and in which the carbon concentration is low, forming a trench by selectively removing a desired region of the interlayer dielectric film and protective film, such that the region extends from the surface of the protective film to the bottom surface of the interlayer dielectric film, supplying carbon to the interface between the interlayer dielectric film and protective film, and forming a conductive layer by burying a conductive material in the trench.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of conductive layers above a substrate; forming a plurality of interlayer insulating layers; forming with dry etching a first hole penetrating the upper interlayer insulating layer to reach the lower insulating layer; forming a protective film on the first hole; and forming by etching a second hole penetrating the lower interlayer insulating layer via the first hole having the protective film formed thereon to form a contact hole.

Abstract: An interconnect structure and method of fabricating the same in which the adhesion between a chemically etched dielectric material and a noble metal liner is improved are provided. In accordance with the present invention, a chemically etching dielectric material is subjected to a treatment step which modified the chemical nature of the dielectric material such that the treated surfaces become hydrophobic. The treatment step is performed prior to deposition of the noble metal liner and aides in improving the adhesion between the chemically etched dielectric material and the noble metal liner.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: A structure and process are provided that are capable of reducing the occurrence of discontinuities within the metallization, such as voiding or seams, formed during electroplating at the edges of semiconductor metallization arrays. The structure includes a metallization bar located around the periphery of the array. The process employs the structure during electroplating.

Abstract: By performing a re-sputter process during the formation of a barrier layer for a contact opening in a tungsten-based process, the reliability of the tungsten deposition, as well as the performance of the resulting contact plug, may be enhanced. During the re-sputtering process, a thickness of the titanium-based barrier layer may be reduced at the contact bottom, while at the same time the material is re-condensed on critical lower sidewall portions of the contact opening.

Abstract: A method of patterning a structure in a thin film on a substrate is described. A film stack on the substrate includes the thin film on the substrate, a developable anti-reflective coating (ARC) layer on the thin film, and a first photo-resist layer on the developable ARC layer. The first photo-resist layer and the developable ARC layer are imaged with a first image pattern and developed to form the first image pattern in the first photo-resist layer and the developable ARC layer. Thereafter, the first photo-resist layer is removed, and the developable ARC layer is modified by thermal treatment. A second photo-resist layer is then formed on the modified ARC layer, and the second photo-resist layer is imaged with a second image pattern and developed to form the second image pattern in the second photo-resist layer. The first and second image patterns are then transferred to the thin film.

Abstract: A method for making a film stack containing one or more metal-containing layers and a substrate processing system for forming the film stack on a substrate are provided. The substrate processing system includes at least one transfer chamber coupled to at least one load lock chamber, at least one first physical vapor deposition (PVD) chamber configured to deposit a first material layer on a substrate, and at least one second PVD chamber for in-situ deposition of a second material layer over the first material layer within the same substrate processing system without breaking the vacuum or taking the substrate out of the substrate processing system to prevent surface contamination, oxidation, etc. The substrate processing system is configured to provide high throughput and compact footprint for in-situ sputtering of different material layers in designated PVD chambers.

Abstract: A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.

Abstract: A method for forming a storage node contact plug in a semiconductor device is provided. The method includes: forming an inter-layer insulation layer over a substrate having a conductive plug; etching a portion of the inter-layer insulation layer using at least line type storage node contact masks as an etch mask to form a first contact hole with sloping sidewalls; etching another portion of the inter-layer insulation layer underneath the first contact hole to form a second contact hole exposing the conductive plug, the second contact hole having substantially vertical sidewalls; and filling the first and second storage node contact holes to form a storage node contact plug.

Abstract: The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The method of manufacturing an interconnect, among other steps, includes forming a via (160) in a substrate (130) and then forming a base getter material (210) in the via (160). The method further includes forming a photoresist layer (410) over the base getter material (210), the photoresist layer (410) having an opening (420) therein positioned over the via (160), and etching a trench (510) into the substrate (130) using the opening (420) in the photoresist layer (410).

Abstract: Methods for forming a via and a conductive path are disclosed. The methods include forming a via within a wafer with cyclic etch/polymer phases, followed by an augmented etch phase. The resulting via may include a first portion having a substantially uniform cross section and a second portion in the form of a hollow ball, extending laterally further within the wafer than the first portion. Back-grinding the wafer to the second portion of the via may create a vent. A conductive path may be formed by filling the via with a conductive material, such as solder. Flux gases may escape through the vent. The wafer surrounding the second portion of the via may be removed, exposing a conductive element in the shape of a ball, the shape of the second portion of the via. Semiconductor devices including the conductive paths of the present invention are also disclosed.

Abstract: In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.

Abstract: A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. Then a first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. Then conductive material essentially consisting of Cu is deposited on the first film to embed the conductive material in the concave portion. Then the semiconductor substrate is annealed. During the period until a barrier layer is formed having also a function of improving tight adhesion, it is possible to ensure sufficient tight adhesion of wiring members and prevent peel-off of the wiring members.

Abstract: Provided are a dual damascene interconnection with a metal-insulator-metal (MIM) capacitor and a method of fabricating the same. In this structure, an MIM capacitor is formed on a via-level IMD. After the via-level IMD is formed, while an alignment key used for patterning the MIM capacitor is being formed, a via hole is formed to connect a lower electrode of the MIM capacitor and an interconnection disposed under the via-level IMD. Also, an upper electrode of the MIM capacitor is directly connected to an upper metal interconnection during a dual damascene process.

Abstract: In a dual damascene process to form a fine interconnection structure, a semiconductor manufacturing method includes: forming a first film to be etched on an insulating layer on a semiconductor substrate; forming a first mask film with an opening on the first film; forming a second film to be etched on the first mask film, burying the opening; forming a second mask film on the second film to be etched; forming an interconnection pattern in the second mask film in the upper portion of the opening; forming an interconnection pattern by etching the second film using the second mask film, forming a via pattern by etching the first film to be etched using the first mask film; and forming a via hole and an interconnection trench in the upper portion of the via hole in the insulating layer by selectively etching the insulating layer using the interconnection and via patterns.

Abstract: Interconnect structures that include a conformal liner repair layer bridging breaches in a liner formed on roughened dielectric material in an insulating layer and methods of forming such interconnect structures. The conformal liner repair layer is formed of a conductive material, such as a cobalt-containing material. The conformal liner repair layer may be particularly useful for repairing discontinuities in a conductive liner disposed on roughened dielectric material bordering the trenches and vias of damascene interconnect structures.

Abstract: In a semiconductor device and a method of manufacturing the semiconductor device, a plug and a channel structure are formed. The plug fills an opening and the channel structure extends upwardly from the plug. The channel structure has a substantially vertical sidewall. The opening is formed through an insulation structure located on a substrate. The plug and the channel structure comprise a material in a single crystalline state that is changed from an amorphous state by an irradiation of a laser beam. The channel structure is doped with impurities such as boron, phosphorus or arsenic.

Abstract: Provided is a process for forming a barrier film to prevent resist poisoning in a semiconductor device by depositing a second nitrogen-free barrier layer on top of a first barrier layer containing nitrogen. A low-k dielectric layer is formed over the second barrier layer. This technique maintains the low electrical leakage characteristics of the first barrier layer and reduces nitrogen poisoning of a photoresist layer subsequently applied.

Abstract: A method for fabricating a semiconductor device comprises the steps of: forming interconnection grooves 38 in an inter-layer insulation film 34; forming an interconnection layer 44 of Cu as the main material in the interconnection grooves 38; and concurrently injecting nitrogen gas and water to the surface of the interconnection layer 44 buried in the interconnection groove 38.

Abstract: A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

Abstract: A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.

Abstract: The document explains, inter alia, a method in which a titanium nitride layer is removed by wet chemical means (106). Following removal of the titanium nitride, further metalization strata are produced (114). The result is an integrated circuit arrangement having connections which have a low electrical resistance. The circuit arrangement is particularly suitable for the purpose of switching high powers.

Abstract: A method is disclosed for forming right-angle contact/via holes for semiconductor devices. A device is provided on a substrate and covered with a first dielectric layer. A second dielectric layer having an etch rate different from that of the first layer is provided over the first layer. A first photoresist pattern is provided over the second layer to define an X or Y dimension of the contact/via hole. A second photoresist pattern is provided over the second layer to define an opposite dimension of the contact/via hole. First and second pattern dimensions are measured prior to etching to ensure appropriate dimensioning of the etched cavity. A second dry etch is then performed to form the contact/via hole. If the photoresist pattern is not within a desired tolerance, the etching process may be adjusted to ensure the cavity will have the desired dimensions.

Abstract: A semiconductor device such as a flash memory includes a semiconductor substrate, two gate insulating films formed on the substrate so as to have a first film thickness and a second film thickness smaller than the first film thickness respectively, and a polycrystalline silicon film formed on the gate insulating films so that parts of the polycrystalline silicon film on the respective gate insulating films are on a level with each other and serving as a gate electrode. The substrate is formed with a recess defined by a bottom and sidewalls substantially perpendicular to the bottom, the recess corresponding to the part of the gate insulating film with the first film thickness.

Abstract: Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. A first opening, a second opening, and a third opening are formed in a substrate such that the first opening, the second opening, and the third opening are in communication with each other. A portion of the first opening, the second opening, and the third opening are filled with a conductive material. Semiconductor devices, including the vias of the present invention, are also disclosed. A method of forming semiconductor components, semiconductor components and assemblies resulting therefrom, and an electronic system, including the vias of the present invention, are further disclosed.

Abstract: A dual damascene process starts with providing a substrate having thereon a base layer, a lower copper wiring inlaid into the base layer, and a lower cap layer covering the inlaid lower copper wiring. A dielectric layer is deposited on the lower cap layer. A TEOS-based oxide cap layer is deposited on the dielectric layer. The TEOS-based oxide cap layer has a carbon content lower than 1×1019 atoms/cm3. A metal hard mask is deposited on the TEOS-based oxide cap layer. A trench recess is etched into the metal hard mask and the TEOS-based oxide cap layer. A partial via feature is then etched into the TEOS-based oxide cap layer and the dielectric layer through the trench recess. The trench recess and partial via feature are etch transferred into the underlying dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the lower copper wiring.

Abstract: A contact via to a surface of a semiconductor material is provided, the contact via having a sidewall which is produced by anisotropically etching a dielectric layer which is placed on via openings. A protective layer is provided on the surface of the semiconductor material. To protect the substrate, an initial etch through an interlayer dielectric is performed to create an initial via which extends toward, but not into the substrate. At least a portion of the protective layer is retained on the substrate. In another step, the final contact via is created. During this step the protective layer is penetrated to open a via to the surface of the semiconductor material.

Abstract: Methods are provided for fabricating a semiconductor device that include the steps of: sequentially forming a metal interconnection and a protecting layer on a semiconductor substrate; forming a contact hole on the protecting layer; isolating the contact hole by forming a molding layer and an etching stop layer stacked thereon; forming a sacrificial layer on the etching stop layer so as to fill the contact hole; forming a photoresist layer with an opening so as to expose the sacrificial layer and such that the opening of the photoresist layer aligns with the contact hole; forming a trench in the molding layer to penetrate the sacrificial layer and the etching stop layer; and performing a wet etching on the semiconductor substrate having the trench to remove the photoresist layer and the sacrificial layer, wherein the wet etching step is performed using an organic compound and fluoride ion-based buffered solution.

Abstract: A method of making a diffusion barrier for a interconnect structure. The method comprises: providing a conductive line in a bottom dielectric trench; depositing a sacrificial liner on the cap layer; depositing an interlayer dielectric; forming a trench and a via in the top interlayer dielectric; and removing a portion of the cap layer and the sacrificial layer proximate to the bottom surface of the via. The removed portions of the cap layer and sacrificial layer deposit predominantly along the lower sidewalls of the via. The conductive line is in contact with a cap layer, and the sacrificial layer is in contact with the cap layer. The invention is also directed to the interconnect structures resulting from the inventive process.

Abstract: Methods for controlling the profile of a trench of a semiconductor structure comprise the step of depositing a photoresist within a via and overlying a second dielectric layer. An image layer is deposited overlying the photoresist and is patterned to form a first trench having a first width and a second width that are not equal and a first angle. The photoresist is dry etched using dry etch parameters, at least one of which is selected based on the first angle and the first and the second widths of the first trench to form a second trench in the photoresist. The second dielectric layer is etched to form a third trench.