Having Viaholes Of Diverse Width Patents (Class 438/638)
-
Patent number: 7875551Abstract: Methods of forming integrated circuit devices include upper sidewall spacers in contact holes to provide enhanced electrical isolation to contact plugs therein while maintaining relatively low contact resistance. These methods include forming an interlayer insulating layer on a semiconductor substrate. The interlayer insulating layer includes at least a first electrically insulating layer of a first material on the semiconductor substrate and a second electrically insulating layer of a second material on the first electrically insulating layer. A contact hole is formed that extends through the interlayer insulating layer and exposes a primary surface of the semiconductor substrate. This contact hole may be formed by selectively etching the second electrically insulating layer and the first electrically insulating layer in sequence and at a faster etch rate of the first material relative to the second material.Type: GrantFiled: October 8, 2009Date of Patent: January 25, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Doo-young Lee, Sang-sup Jeong, Sung-gil Choi, Jong-chul Park, Jin-young Kim, Ki-jin Park
-
Patent number: 7875550Abstract: Disclosed are embodiments of a semiconductor structure with a partially selfaligned contact in lower portion of the contact is enlarged to reduce resistance without impacting device yield. Additionally, the structure optionally incorporates a thick middle-of-the-line (MOL) nitride stress film to enhance carrier mobility. Embodiments of the method of forming the structure comprise forming a sacrificial section in the intended location of the contact. This section is patterned so that it is self-aligned to the gate electrodes and only occupies space that is intended for the future contact. Dielectric layer(s) (e.g., an optional stress layer followed by an interlayer dielectric) may be deposited once the sacrificial section is in place. Conventional contact lithography is used to etch a contact hole through the dielectric layer(s) to the sacrificial section. The sacrificial section is then selectively removed to form a cavity and the contact is formed in the cavity and contact hole.Type: GrantFiled: April 28, 2008Date of Patent: January 25, 2011Assignee: International Business Machines CorporationInventors: Gregory Costrini, David M. Fried
-
Patent number: 7871660Abstract: A technique for manufacturing a device that includes a deposit of getter material on a support involves treating the support on which the getter material is formed with a caustic fluid. An aspect of the technique is that it may clean and/or chemically activate the getter material without substantial damage to the getter material. The getter material may be formed on an internal wall of the device.Type: GrantFiled: November 12, 2004Date of Patent: January 18, 2011Assignee: Saes Getters, S.p.A.Inventors: Marco Moraja, Marco Amiotti, Costanza Dragoni, Massimo Palladino
-
Patent number: 7867893Abstract: A method is provided of forming a conductive via for contacting a bulk semiconductor region of a semiconductor-on-insulator (“SOI”) substrate. A first opening is formed in a conformal layer overlying a trench isolation region, where the trench isolation region shares an edge with the SOI layer. A dielectric layer then is deposited atop the conformal layer and the trench isolation region, after which a second opening is formed which is aligned with the first opening, the second opening extending through the dielectric layer to expose the bulk semiconductor region. Finally, the conductive via is formed in the second opening.Type: GrantFiled: June 28, 2007Date of Patent: January 11, 2011Assignees: International Business Machines Corporation, Kabushiki Kaisha ToshibaInventors: Haining S. Yang, Ramachandra Divakaruni, Byeong Y. Kim, Junedong Lee, Gaku Sudo
-
Patent number: 7863188Abstract: It is an object of the present invention to provide a semiconductor device where, even in a case of stacking a plurality of semiconductor elements provided over a substrate, the stacked semiconductor elements can be electrically connected through the substrate, and a manufacturing method thereof. According to one feature of the present invention, a method for manufacturing a semiconductor device includes the steps of selectively forming a depression in an upper surface of a substrate or forming an opening which penetrates the upper surface through a back surface; forming an element group having a transistor so as to cover the upper surface of the substrate and the depression, or the opening; and exposing the element group formed in the depression or the opening by thinning the substrate from the back surface.Type: GrantFiled: July 14, 2006Date of Patent: January 4, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takuya Tsurume, Yoshitaka Dozen
-
Patent number: 7858483Abstract: A method for forming a capacitor of a semiconductor device includes forming a first insulation layer having a storage node plug on a semiconductor substrate; forming an etch stop layer and a second insulation layer sequentially on the substrate having the first insulation layer; forming a hole exposing a portion of the storage node plug by selectively etching the second insulation layer by using the etch stop layer; recessing a portion of the storage node plug exposed by the hole; forming a barrier metal layer on a surface of the recessed storage node plug; forming a storage node electrode connected to the storage node plug through the barrier metal layer in the hole; and forming a dielectric layer and a metal layer for a plate electrode sequentially on the storage node electrode.Type: GrantFiled: June 15, 2005Date of Patent: December 28, 2010Assignee: Hynix Semiconductor Inc.Inventors: Hyung Bok Choi, Jong Bum Park, Kee Jeung Lee, Jong Min Lee
-
Patent number: 7855142Abstract: Methods of forming dual-damascene metal interconnect structures include forming an electrically insulating layer on an integrated circuit substrate and then forming a hard mask layer on the electrically insulating layer. The hard mask layer may include a stacked composite of at least four electrically insulating material layers therein. The hard mask layer may also have separate trench and via patterns therein that are respectively defined by at least first and second ones of the electrically insulating material layers and at least third and fourth ones of the electrically insulating material layers.Type: GrantFiled: January 9, 2009Date of Patent: December 21, 2010Assignees: Samsung Electronics Co., Ltd., International Business Machines CorporationInventors: Young Mook Oh, Youngjin Choi
-
Patent number: 7855141Abstract: A method of producing a semiconductor device having a plurality of wiring layers forms a first interlayer-insulating film, forms a plurality of grooves for wiring in the first interlayer-insulating film, fills metallic films in the grooves to form wirings, etches the first interlayer-insulating film with the wirings as a mask and removes the interlayer-insulating film between the wirings to provide grooves to be filled, and fills a second interlayer-insulating film made of a material of low dielectric constant in the grooves to be filled.Type: GrantFiled: July 13, 2009Date of Patent: December 21, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Shimooka, Hideki Shibata, Hideshi Miyajima, Kazuhiro Tomioka
-
Patent number: 7838415Abstract: A method of fabricating a dual damascene structure is described. A dielectric layer and a metal hard mask layer are sequentially formed on a substrate having thereon a conductive layer and a liner layer. The metal hard mask layer and the dielectric layer are patterned to form a via hole exposing a portion of the liner layer. A gap-filling layer is filled in the via hole, having a height of ¼ to ½ of the depth of the via hole. A trench is formed in the metal hard mask layer and the dielectric layer. The gap-filling layer is removed to expose the portion of the liner layer, which is then removed. A metal layer is formed filling in the via hole and the trench, and then the metal hard mask layer is removed.Type: GrantFiled: January 16, 2007Date of Patent: November 23, 2010Assignee: United Microelectronics Corp.Inventors: Kuang-Yeh Chang, Hong Ma
-
Patent number: 7838416Abstract: A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a memory cell, which in turn includes an electrode and a phase change material. The electrode may be disposed on a substrate and include a sublithographic lateral dimension parallel to the substrate. The phase change material may be coupled to the electrode and include a lateral dimension parallel to the substrate and greater than the sublithographic lateral dimension of the electrode. Various semiconductor devices and manufacturing methods are also provided.Type: GrantFiled: February 24, 2010Date of Patent: November 23, 2010Assignee: Round Rock Research, LLCInventor: Russell C. Zahorik
-
Patent number: 7829458Abstract: A wiring structure includes a first insulation layer located on a substrate, and first and second plugs located on the substrate and extending through the first insulation layer. The first plug includes an upper peripheral portion that defines a recess and the second plug is adjacent to the first plug. A second insulation layer is located on the first insulation layer, the first plug and the second plug. A bit line structure is located on the second insulation layer and is electrically connected to the first plug. A protection spacer is located on the recess of the first plug and a sidewall of an opening in the second insulation layer. The opening exposes the recess of the first plug, the second plug and the sidewall of the bit line structure. A pad is located in the opening and contacts the second plug.Type: GrantFiled: July 14, 2008Date of Patent: November 9, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Jae-Choel Paik
-
Patent number: 7829459Abstract: A method and apparatus for partially strapping two polysilicon lines, each having a first end and second end, uses a metal line having a plurality of spaced apart metal segments with each metal segment partially strapping a different portion of a polysilicon line. The metal segments are arranged from the first end to the second end with the signals propagating from the second end to the first end. Where two metal segments are used, the segments have lengths of x = 2 ? ? L 7 and L-X where L is the length between the first end and the second end. Where three segments are used, the segments have lengths of X=0.25 L, Y=0.48 L, and Z=0.27 L.Type: GrantFiled: August 17, 2009Date of Patent: November 9, 2010Assignee: Silicon Storage Technology, Inc.Inventor: Michael James Heinz
-
Patent number: 7816268Abstract: To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen.Type: GrantFiled: February 26, 2010Date of Patent: October 19, 2010Assignee: Renesas Elecronics CorporationInventors: Takeshi Furusawa, Daisuke Kodama, Masahiro Matsumoto, Hiroshi Miyazaki
-
Patent number: 7816266Abstract: The invention concerns a method of forming a copper portion surrounded by an insulating material in an integrated circuit structure, the insulating material being a first oxide, the method having steps including forming a composite material over a region of the insulating material where the copper portion is to be formed, the composite material having first and second materials, annealing such that the second material reacts with the insulating material to form a second oxide that provides a diffusion barrier to copper; and depositing a copper layer over the composite material by electrochemical deposition to form the copper portion.Type: GrantFiled: October 5, 2007Date of Patent: October 19, 2010Assignee: STMicroelectronics Crolles 2 SASInventors: Nicolas Jourdan, Joaquin Torres
-
Patent number: 7816257Abstract: In a method of forming an integrated circuit device, an opening is formed extending through a first and a second insulating layers and through a semiconductor layer therebetween to a surface of a substrate. The opening includes a recess in a sidewall thereof between the first and second insulating layers adjacent the semiconductor layer. A conductive plug is formed on the sidewall of the opening and on the surface of the substrate and laterally extending into the recess between the first and second insulating layers to contact the semiconductor layer. The semiconductor layer may be selectively etched at the sidewall without substantially etching the first and second insulating layers at the sidewall of the opening to form the recess between the first and second insulating layers. Related devices are also discussed.Type: GrantFiled: April 24, 2006Date of Patent: October 19, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Seong-Hwee Cheong, Gil-Heyun Choi, Sang-Woo Lee, Jin-Ho Park
-
Patent number: 7811930Abstract: A manufacturing method of a dual damascene structure is provided. First, a first dielectric layer, a second dielectric layer, and a mask layer are formed. A first trench structure is formed in the mask layer. A via structure is formed in the mask layer, the second dielectric layer, and the first dielectric layer. A portion of the second dielectric layer is then removed, so as to transform the first trench structure into a second trench structure. Here, a bottom of the second trench structure exposes the first dielectric layer.Type: GrantFiled: March 18, 2009Date of Patent: October 12, 2010Assignee: United Microelectronics Corp.Inventor: Chih-Jung Wang
-
Patent number: 7811931Abstract: A semiconductor device has a plurality of interconnect layers each including a plurality of interconnect lines. The semiconductor device includes a dielectric film (HDP film) formed by means of high density plasma-enhanced CVD and including an edge formed on the side surface of the topmost-layer interconnect lines, a silicon oxide film formed by modifying a SOG film on the HDP film between adjacent two of the topmost-layer interconnect lines in the element forming region, and a passivation film formed to cover the HDP film and the topmost-layer interconnect lines.Type: GrantFiled: January 19, 2007Date of Patent: October 12, 2010Assignee: Elpida Memory, Inc.Inventor: Masateru Ando
-
Patent number: 7807569Abstract: In one embodiment, a semiconductor device comprises a conductive pad formed in a semiconductor substrate. The semiconductor device further includes a conductive pattern overlying a peripheral region of the conductive pad. The conductive pattern has an opening to expose another region of the conductive pad. The semiconductor device also includes a conductive contact extending through the opening. The conductive contact is electrically connected to the conductive pad. As a result, manufacturing cost for the semiconductor device may be reduced while manufacturing throughput may be improved.Type: GrantFiled: March 3, 2009Date of Patent: October 5, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Je-Min Park
-
Publication number: 20100237471Abstract: A plurality of semiconductor die is mounted to a carrier separated by a peripheral region. An insulating material is deposited in the peripheral region. A first opening is formed in the insulating material of the peripheral region to a first depth. A second opening is formed in the insulating material of the peripheral region centered over the first opening to a second depth less than the first depth. The first and second openings constitute a composite through organic via (TOV) having a first width in a vertical region of the first opening and a second width in a vertical region of the second opening. The second width is different than the first width. A conductive material is deposited in the composite TOV to form a conductive TOV. An organic solderability preservative (OSP) coating is formed over a contact surface of the conductive TOV.Type: ApplicationFiled: March 17, 2009Publication date: September 23, 2010Applicant: STATS ChipPAC, LTD.Inventors: Reza A. Pagaila, Byung Tai Do, Shuangwu Huang
-
Patent number: 7799681Abstract: A method for integrating ruthenium (Ru) metal cap layers and modified Ru metal cap layers into copper (Cu) metallization of semiconductor devices to improve electromigration (EM) and stress migration (SM) in bulk Cu metal. In one embodiment, the method includes providing a planarized patterned substrate containing a Cu metal surface and a dielectric layer surface, depositing first Ru metal on the Cu metal surface, and depositing additional Ru metal on the dielectric layer surface, where the amount of the additional Ru metal is less than the amount of the first Ru metal. The method further includes at least substantially removing the additional Ru metal from the dielectric layer surface to improve the selective formation of a Ru metal cap layer on the Cu metal surface. Other embodiments further include incorporating one or more types of modifier elements into the dielectric layer surface, the Cu metal surface, the Ru metal cap layer, or a combination thereof.Type: GrantFiled: July 15, 2008Date of Patent: September 21, 2010Assignee: Tokyo Electron LimitedInventors: Kenji Suzuki, Frank M. Cerio, Jr., Miho Jomen, Shigeru Mizuno, Yasushi Mizusawa, Tadahiro Ishizaka
-
Patent number: 7799407Abstract: There is provided a bank structure which partitions off a pattern formation region in which a functional liquid is to be disposed and flow. The pattern formation region includes a first pattern formation region, and a second pattern formation region which is continuously connected to the first pattern formation region and which has a larger width than the first pattern formation region. The second pattern formation region is provided with at least one partition bank which partitions off the second pattern formation region to regulate the flow direction of the functional liquid. A partition width substantially orthogonal to the flow direction of the functional liquid which is regulated by the partition bank is less than ±20% of the width of the first pattern formation region.Type: GrantFiled: May 12, 2006Date of Patent: September 21, 2010Assignee: Seiko Epson CorporationInventors: Katsuyuki Moriya, Toshimitsu Hirai
-
Patent number: 7795141Abstract: (a1) A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. (a2) A first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. (a3) Conductive material essentially consisting of Cu is deposited on the first film to embed the conductive material in the concave portion. (a4) The semiconductor substrate is annealed. During the period until a barrier layer is formed having also a function of improving tight adhesion, it is possible to ensure sufficient tight adhesion of wiring members and prevent peel-off of the wiring members.Type: GrantFiled: July 11, 2008Date of Patent: September 14, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Noriyoshi Shimizu, Nobuyuki Ohtsuka, Hideki Kitada, Yoshiyuki Nakano
-
Patent number: 7795152Abstract: A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer layer over the dielectric layer. The polymer layer is applied uniformly and fills the apertures at different rates depending on the geometry of the apertures, or on the presence or absence of growth accelerating material. The polymer creates spacers for the etching of additional structure in between the spacers. The method is capable of achieving structures smaller than current lithography techniques.Type: GrantFiled: May 10, 2006Date of Patent: September 14, 2010Assignee: Micron Technology, Inc.Inventor: Gurtej Sandhu
-
Patent number: 7790606Abstract: A method of forming an interconnect structure in a semiconductor device in which via holes (62) defined in a dielectric layer are filled with a filler material (64), such as a porogen material, before a further dielectric layer (66) is deposited thereover. Trenches (72) are formed in the further dielectric layer and then the filler material exposed thereby in the via holes is removed. The method provides a robust process which affords improved via and trench profile control.Type: GrantFiled: October 5, 2007Date of Patent: September 7, 2010Assignee: NXP B.V.Inventor: Roel Daamen
-
Patent number: 7786023Abstract: A metal pad formation method and metal pad structure using the same are provided. A wider first pad metal is formed together with a first metal. A dielectric layer is then deposited thereon. A first opening and a second opening are formed in the dielectric layer to respectively expose the first metal and the first pad metal. Then, the first opening is filled by W metal to generate a first via. Finally, a second metal and a second pad metal are formed to respectively cover the first via and the first pad metal to generate the metal pad.Type: GrantFiled: June 25, 2007Date of Patent: August 31, 2010Assignee: Macronix International Co., Ltd.Inventors: Yung-Tai Hung, Jen-Chuan Pan, Chin-Ta Su, Ta-Hung Yang
-
Patent number: 7781892Abstract: An improved interconnect structure and method of making such a device. The improved interconnect electrically connects two otherwise separate areas on a semiconductor wafer. The interconnect preferably uses a copper conductor disposed within a trench and via structure formed in a low-k hybrid dielectric layer using a dual damascene process. Each contact region is served by a plurality of vias, each in communication with the trench conductor portion. The entry from the trench to the via is rounded for at least one and preferably all of the via structures.Type: GrantFiled: December 22, 2005Date of Patent: August 24, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsueh-Chung Chen, Chine-Gie Lou, Ping-Liang Liu, Su-Chen Fan
-
Patent number: 7781331Abstract: The present invention relates to a method for producing electrical bushings through non-conductive or semiconductive substrates, which are particularly suitable for electrical applications. The method is characterized in that a semiconductor substrate or a non-conductive substrate (13) whose front side has an electrically conductive contact point (6) at at least one location is provided with a recess (7) from its rear side such that the recess (1) on the front side of the substrate ends under that location or one of the locations at which the electrically conductive contact point or one of the electrically conductive contact points is situated and is completely covered by the latter, to which an electrically conductive structure (9) which establishes a conductive connection between the respective contact point and the rear-side surface (10, 11, 12) of the substrate through the recess or at least one of the recesses is applied from the rear side of the substrate.Type: GrantFiled: November 8, 2006Date of Patent: August 24, 2010Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.Inventor: Wolfgang Reinert
-
Patent number: 7772069Abstract: A method of forming a semiconductor device is provided. A plurality of first guide patterns are formed on a substrate. A mask layer is conformally formed on the substrate. Second guide patterns are formed in empty regions on respective sides of the first guide patterns. The mask layer is planarized and the first and second guide patterns are removed. The mask layer is etched by an anisotropic etching process.Type: GrantFiled: March 7, 2008Date of Patent: August 10, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Yong Park, Sung-Hyun Kwon, Jae-Hwang Sim, Keon-Soo Kim, Jae-Kwan Park
-
Patent number: 7767570Abstract: A method of making an integrated circuit includes providing a low-k dielectric layer on a substrate, the low-k dielectric layer including or adjacent to a plurality of conductive features; patterning the low-k dielectric layer to form trenches; patterning the low-k dielectric layer to form conductive vias and dummy vias, wherein each of the conductive vias is aligned with at least one of the plurality of the conductive features and at least one of the trenches, and each of the dummy vias is a distance above the plurality of conductive features; filling the trenches, conductive vias, and dummy vias using one or more conductive materials; and planarizing the conductive material(s).Type: GrantFiled: July 12, 2006Date of Patent: August 3, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei Shun Chen, Chin-Hsiang Lin, Vencent Chang, Lawrence Lin, Lai Chien Wen, Jhun Hua Chen
-
Patent number: 7767578Abstract: A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide layer is deposited on the dielectric layer. A metal hard mask is formed on the silicon oxide layer. A trench opening is etched into the metal hard mask. A partial via feature is etched into the dielectric layer within the trench opening. The trench opening and the partial via feature are etch transferred into the dielectric layer, thereby forming a dual damascene opening, which exposes a portion of the cap layer. A liner removal step is performed to selectively remove the exposed cap layer from the dual damascene opening by employing CF4/NF3 plasma.Type: GrantFiled: January 11, 2007Date of Patent: August 3, 2010Assignee: United Microelectronics Corp.Inventors: Chun-Jen Huang, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao
-
Patent number: 7767585Abstract: A method of cleaning for removing metal compounds attached to a surface of a substrate, wherein the cleaning is conducted by supplying a supercritical fluid of carbon dioxide comprising at least one of triallylamine and tris(3-aminopropyl)amine to the surface of the substrate and a process for producing a semiconductor device using the method of cleaning are provided. In accordance with the method of cleaning and the method for producing a semiconductor device using the method, etching residues or polishing residues containing metal compounds are efficiently removed selectively from the electroconductive material forming the electroconductive layer. When the electroconductive layer is a wiring, an increase in resistance due to residual metal compounds can be suppressed, and an increase in the leak current due to diffusion of the metal from the metal compounds to the insulating film can be prevented. Therefore, reliability on the wiring is improved, and the yield of the semiconductor device can be increased.Type: GrantFiled: September 5, 2006Date of Patent: August 3, 2010Assignees: Sony Corporation, Mitsubishi Gas Chemical Company, Inc.Inventors: Koichiro Saga, Kenji Yamada, Tomoyuki Azuma, Yuji Murata
-
Patent number: 7767587Abstract: Interconnect structures possessing a non-porous (dense) low-k organosilicate glass (OSG) film utilizing a porous low-k OSG film as an etch stop layer or a porous low-k OSG film using a non-porous OSG film as a hardmask for use in semiconductor devices are provided herein. The novel interconnect structures are capable of delivering improved device performance, functionality and reliability owing to the reduced effective dielectric constant of the stack compared with that of those conventionally employed and also because of the relatively uniform line heights made feasible by these unique and seemingly counterintuitive features.Type: GrantFiled: February 21, 2008Date of Patent: August 3, 2010Assignee: International Business Machines CorporationInventors: Nicholas C. M. Fuller, Timothy J. Dalton
-
Patent number: 7763539Abstract: A method for manufacturing a semiconductor device. In one example embodiment, a method for manufacturing a semiconductor device includes various steps. First, a dielectric layer is formed on the whole surface of a semiconductor substrate that includes an upper surface of a transistor. Next, a trench and a contact hole are formed by etching the dielectric layer so that the upper surface of the transistor is exposed. Then, a contact is formed by embedding a first conductive layer in the contact hole. Next, an etching stop layer is selectively forming on an upper part of the contact. Then, the semiconductor device is blanket-etched such that the first conductive layer remains in the trench. Next, the etching stop layer is removed. Finally, a metal line is formed by embedding a second conductive layer in the trench.Type: GrantFiled: October 31, 2008Date of Patent: July 27, 2010Assignee: Dongbu Hitek Co., Ltd.Inventor: Seung Hyun Kim
-
Patent number: 7759243Abstract: A method for forming an on-chip high frequency electro-static discharge device on an integrated circuit is described. In one embodiment of the method, a capped first dielectric layer with more than one electrode formed therein is provided. A second dielectric layer is deposited over the capped first dielectric layer. A first hard mask dielectric layer is deposited over the second dielectric layer. A cavity trench is formed through the first hard mask dielectric layer and the second dielectric layer to the first dielectric layer, wherein the cavity trench is formed in the first dielectric layer between two adjacent electrodes. At least one via is formed through the second dielectric layer about the cavity trench. A metal trench is formed around each of the at least one via. A release opening is formed over the cavity trench.Type: GrantFiled: June 23, 2008Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventors: Hanyi Ding, Kai D. Feng, Zhong-Xiang He, Xuefeng Liu, Anthony K. Stamper
-
Patent number: 7754568Abstract: A semiconductor device such as a flash memory includes a semiconductor substrate, two gate insulating films formed on the substrate so as to have a first film thickness and a second film thickness smaller than the first film thickness respectively, and a polycrystalline silicon film formed on the gate insulating films so that parts of the polycrystalline silicon film on the respective gate insulating films are on a level with each other and serving as a gate electrode. The substrate is formed with a recess defined by a bottom and sidewalls substantially perpendicular to the bottom, the recess corresponding to the part of the gate insulating film with the first film thickness.Type: GrantFiled: June 2, 2008Date of Patent: July 13, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Ryuichi Kamo, Minori Kajimoto, Hiroaki Tsunoda, Yuuichiro Murahama
-
Patent number: 7749897Abstract: A method of manufacturing a semiconductor device comprising a wiring structure that includes a vertical wiring section is disclosed. The method comprises a step of forming an interlayer insulation film made of a low dielectric constant material on a wiring layer, a step of forming a silicon oxide film by CVD using SiH4 gas and CO2 gas on the interlayer insulation film, a step of forming a chemically amplified resist film to cover the silicon oxide film, and a step of forming a first opening in a position on the chemically amplified resist film where the vertical wiring section is to be formed.Type: GrantFiled: July 18, 2008Date of Patent: July 6, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Ken Sugimoto, Yoshiyuki Ohkura, Hirofumi Watatani, Tamotsu Owada, Shunn-ichi Fukuyama
-
Patent number: 7749896Abstract: Semiconductor devices and methods for forming the same in which damages to a low-k dielectric layer therein can be reduced or even prevented are provided. A semiconductor device is provided, comprising a substrate. A dielectric layer with at least one conductive feature therein overlies the substrate. An insulating cap layer overlies the top surface of the low-k dielectric layer adjacent to the conductive feature, wherein the insulating cap layer comprises metal ions.Type: GrantFiled: August 23, 2005Date of Patent: July 6, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Wen Su, Shih-Wei Chou, Ming-Hsing Tsai
-
Patent number: 7745327Abstract: By appropriately designing a plurality of deposition steps and intermediate sputter processes, the formation of a barrier material within a via opening may be accomplished on the basis of a highly efficient process strategy that readily integrates conductive cap layers formed above metal-containing regions into well-approved process sequences.Type: GrantFiled: June 12, 2007Date of Patent: June 29, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Axel Preusse, Michael Friedemann, Robert Seidel, Berit Freudenberg
-
Patent number: 7741223Abstract: A method for fabricating a semiconductor device includes etching a substrate to form a first recess having a micro trench, etching the substrate disposed under the first recess to form a second recess having a profile substantially vertical and a width greater than a portion of the first recess where no micro trench is formed, etching the substrate disposed under the second recess to form a third recess having a profile substantially spherical, and forming a gate pattern over a resultant recess including the first to third recesses.Type: GrantFiled: June 26, 2007Date of Patent: June 22, 2010Assignee: Hynix Semiconductor Inc.Inventors: Hyun-Sik Park, Ky-Hyun Han
-
Patent number: 7737029Abstract: Methods of forming devices include forming a first electrically insulating layer having a metal interconnection therein, on a substrate and then forming a first electrically insulating barrier layer on an upper surface of the metal interconnection and on the first electrically insulating layer. The first electrically insulating barrier layer is exposed to a plasma that penetrates the first electrically insulating barrier and removes oxygen from an upper surface of the metal interconnection. The barrier layer may have a thickness in a range from about 5 ? to about 50 ? and the plasma may be a hydrogen-containing plasma that converts oxygen on the upper surface of the metal interconnection to water.Type: GrantFiled: March 18, 2008Date of Patent: June 15, 2010Assignees: Samsung Electronics Co., Ltd., International Business Machines Corporation, Chartered Semiconductor Manufacturing Ltd.Inventors: Jae-hak Kim, Griselda Bonilla, Steven E. Molis, Darryl D. Restaino, Hosadurga Shobha, Johnny Widodo
-
Patent number: 7737026Abstract: A method of forming an interconnection in a semiconductor device includes forming a first liner in a dielectric layer therein; depositing a tungsten filler on top of the first liner; performing chemical mechanical planarization (CMP) to smooth out and remove the first liner and tungsten filler from the semiconductor's exposed surface; selectively removing the first liner and tungsten filler in the via; wherein the selective removing results in the first liner and the tungsten filler being removed in an upper region of the via; forming a second liner in the upper region of the via and tungsten filler; selectively removing the second liner from the tungsten filler; forming a copper seed layer on top of the tungsten filler; depositing a copper filler on top of the copper seed layer; and performing chemical CMP to smooth out and remove the second liner and copper filler from the semiconductor's exposed surface.Type: GrantFiled: March 29, 2007Date of Patent: June 15, 2010Assignee: International Business Machines CorporationInventors: Ying Li, Keith Kwong-Hon Wong
-
Patent number: 7737023Abstract: In a process for the manufacture of a semiconductor integrated circuit device having an inlaid interconnect structure by embedding a conductor film in a recess, such as a trench or hole, formed in an organic insulating film which constitutes an interlevel dielectric film and includes an organosiloxane as a main component, the recess, such as a trench or hole, is formed by subjecting the organic insulating film to plasma dry etching in a CF-based gas/N2/Ar gas in order to suppress the formation of an abnormal shape on the bottom of the recess, upon formation of a photoresist film over the organic insulating film, followed by formation of the recess therein with the photoresist film as an etching mask.Type: GrantFiled: August 19, 2008Date of Patent: June 15, 2010Assignee: Renesas Technology CorporationInventors: Shouochi Uno, Atsushi Maekawa, Takashi Yunogami, Kazutami Tago, Kazuo Nojiri, Shuntaro Machida, Takafumi Tokunaga
-
Patent number: 7737025Abstract: A method for forming an plurality of paths on a substrate includes drilling an opening for a via to a depth to expose a first pad and a second pad, lining the opening with a conductive material, and insulating a first portion of the lining in the opening from a second portion of the lining in the opening to form a first electrical path contacting the first pad and a second electrical path contacting the second pad.Type: GrantFiled: January 24, 2007Date of Patent: June 15, 2010Assignee: Intel CorporationInventors: Todd B Myers, Nicholas R. Watts, Eric C Palmer, Renee M Defeo, Jui Min Lim
-
Patent number: 7732317Abstract: Methods of forming a cell of a NOR-type flash memory device are provided in which a first gate pattern having a first sidewall and a second gate pattern having a second sidewall that opposes the first sidewall are formed on a semiconductor substrate. A source/drain region is formed in the semiconductor substrate between the first and second gate patterns. An etch stop layer is formed on the first and second sidewalls that defines a gap region. A dielectric layer is formed in the gap region, and is then etched to form a contact hole. Finally, a conductive material is deposited in the contact hole.Type: GrantFiled: July 26, 2004Date of Patent: June 8, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Chul Shin, Jeong-Ho Park, Jung-Young Lee, Kwang-Won Park
-
Patent number: 7723849Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.Type: GrantFiled: December 28, 2006Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
-
Patent number: 7718546Abstract: A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched SixOyNz layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO2) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.Type: GrantFiled: June 27, 2007Date of Patent: May 18, 2010Assignee: Sandisk 3D LLCInventors: Steven J. Radigan, Michael W. Konevecki
-
Patent number: 7719085Abstract: A semiconductor device 1 includes an interconnect 12, a conductive layer 14 (first conductive layer), an insulating layer 20 (first insulating layer), another conductive layer 30 (second conductive layer), another insulating layer 40 (second insulating layer), a via plug 52 (first via plug), and another via plug 54 (second via plug). In the semiconductor device 1, the conductive layer 14, the insulating layer 20 and the conductive layer 30 constitute a MIM capacitor (capacitor element). To be more detailed, the conductive layer 14, the insulating layer 20 and the conductive layer 30 serve as a lower electrode, an insulating capacitor film and an upper electrode, respectively. The insulating layer 40 covers both the conductive layer 30 and the interconnect 12. The insulating layer 40 works as the etching stopper for the via plugs 52, 54.Type: GrantFiled: July 11, 2006Date of Patent: May 18, 2010Assignee: NEC Electronics CorporationInventors: Takuji Onuma, Yasutaka Nakashiba
-
Patent number: 7718527Abstract: A method is provided for integrating cobalt tungsten cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature formed in a low-k material and a first metallization layer at the bottom of the feature, forming a cobalt tungsten cap layer on the first metallization layer, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt metal cap layer, and filling the recessed feature with Cu metal. Another embodiment includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k regions, and forming a cobalt tungsten cap layer on the Cu paths.Type: GrantFiled: October 1, 2008Date of Patent: May 18, 2010Assignee: Tokyo Electron LimitedInventors: Tadahiro Ishizaka, Shigeru Mizuno, Miho Jomen
-
Patent number: RE41538Abstract: A method for making an integrated circuit device includes forming at least one interconnect structure adjacent a substrate by forming at least one barrier layer, forming a doped copper seed layer on the at least one barrier layer, and forming a copper layer on the doped copper seed layer. The method may further include annealing the integrated circuit device after forming the copper layer to diffuse the dopant from the doped copper seed layer into grain boundaries of the copper layer. The doped copper seed layer may include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant to provide the enhanced electromigration resistance. Forming the copper layer may comprise plating the copper layer. In addition, forming the copper layer may comprise forming the copper layer to include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant.Type: GrantFiled: April 22, 2005Date of Patent: August 17, 2010Inventor: James A. Cunningham
-
Patent number: RE41935Abstract: A method for plasma treatment of anisotropically etched openings to improve a crack initiation and propagation resistance including providing a semiconductor wafer having a process surface including anisotropically etched openings extending at least partially through a dielectric insulating layer; plasma treating in at least one plasma treatment the process surface including the anisotropically etched openings to improve an adhesion of a subsequently deposited refractory metal adhesion/barrier layer thereover; and, blanket depositing at least one refractory metal adhesion/barrier layer to line the anisotropically etched openings.Type: GrantFiled: January 19, 2007Date of Patent: November 16, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shing-Chyang Pan, Keng-Chu Lin, Wen-Chih Chiou, Shwang-Ming Jeng