Abstract: A process for masking an electronic component substrate involving application of a temporary mask material to the substrate to form a removably adhered temporary mask over the surface. Exemplary mask materials include polymer films and aqueous hardenable liquid coatings. An electronic component substrate having a temporary mask for masking the substrate surface from interconnect fill material.

Abstract: A thermally decomposable sacrificial material is deposited in a void or opening in a dielectric layer on a semiconductor substrate. The thermally decomposable sacrificial material may be removed without damaging or removing the dielectric layer. The thermally decomposable sacrificial material may be a combination of organic and inorganic materials, such as a hydrocarbon-siloxane polymer hybrid.

Abstract: A high integrity, reliable liner is disclosed for a via in which a titanium aluminide layer is preformed as a lining within a via hole prior to deposition of other conductive materials within the via hole. The conductive materials deposited on the preformed titanium aluminide can be either a secondary barrier layer portion of the liner, such as a titanium compound layer, which in turn has a metal plug deposited thereon, or, alternatively, a metal plug directly deposited on the titanium aluminide layer. An important advantage achieved by the present invention is that a via is formed with a substantial elimination of void formation. The enhanced vias are useful in a wide variety of semiconductor devices, including SRAMS and DRAMs.

Abstract: A high integrity, reliable liner is disclosed for a via in which a titanium aluminide layer is preformed as a lining within a via hole prior to deposition of other conductive materials within the via hole. The conductive materials deposited on the preformed titanium aluminide can be either a secondary barrier layer portion of the liner, such as a titanium compound layer, which in turn has a metal plug deposited thereon, or, alternatively, a metal plug directly deposited on the titanium aluminide layer. An important advantage achieved by the present invention is that a via is formed with a substantial elimination of void formation. The enhanced vias are useful in a wide variety of semiconductor devices, including SRAMS and DRAMs.

Abstract: An interconnection substrate comprises an uppermost interconnection layer having a plurality of terminal pads located at positions corresponding to a plurality of solder bumps (external connection terminals) provided on a semiconductor element which is to be mounted on the interconnection substrate. The interconnection substrate also has a metal column formed on each of the terminal pads and has a resin film covering a side surface of the metal column. The interconnection substrate further has an insulating layer formed on the uppermost interconnection layer so that a gap is formed between the insulating layer and an outer peripheral surface of the resin film.

Abstract: A method for manufacturing a semiconductor device of the present invention includes the steps of: (a) depositing an interlayer insulator film on a substrate including a plurality of conductive layers; (b) forming a plurality of contact holes running through the interlayer insulator film to reach respective ones of the plurality of conductive layers, each of the contact holes having a tapered portion at an upper end thereof; (c) depositing a conductive material film on the interlayer insulator film so as to fill the plurality of contact holes; (d) removing the conductive material film until a surface of the interlayer insulator film is exposed so as to form a plurality of plugs made of the conductive material film filling the plurality of contact holes; and (e) removing a portion of the interlayer insulator film, which has been exposed in the step (d), so as to remove the tapered portions.

Abstract: Embodiments include a semiconductor device comprising: a pad formed on an insulating layer and having an electric connection region with external components; and a protective insulating layer which has an aperture for exposing the electric connection region. The protective insulating layer may include a first insulating layer and a second insulating layer, and side surfaces of these insulating layers are exposed to the aperture. At least part of the side surfaces surrounding the electric connection region have a tapered configuration at an acute angle to a top surface of the pad. This semiconductor device not only enables reduction of the fabrication steps, but also provides a reliable passivation structure for a pad with sufficient thickness and stress relaxation characteristics.

Abstract: A semiconductor device substrate has fine terminals with a small pitch and is able to be easily produced at a low cost without using a special process. A mounting terminal has a pyramidal shape and extending between a front surface and a back surface of a silicon substrate. An end of the mounting terminal protrudes from the back surface of the silicon substrate. A wiring layer is formed on the front surface of the silicon substrate. The wiring layer includes a conductive layer that is electrically connected to the mounting terminal.

Abstract: The present invention relates to an improved method for forming a UBM pad and solder bump connection for a flip-chip which eliminates at least two mask steps required in standard UBM pad forming processes when repatterning the bond pad locations.

Abstract: A VLSI contact formation process in which a nitride layer is used to stop a wet oxide etch. An anisotropic plasma etch is used to cut a substantially vertical contact hole through the nitride and underlying layers. Thus, the resulting contact hole has a “Y”-shaped profile.

Abstract: An improved and new process for fabricating dual damascene copper, in which trench/via liner removal from porous low-k dielectric, is performed using a new RIE chemistry of CF4/H2, to etch SiN and SiC liners. Prior to the new process, convention liner etching produced the following deleterious results: a) Cu re-deposition by sputtering, b) polymer deposits, and c) surface roughening of the porous low-k IMD dielectric. Process details are: CF4/H2 based with approximate gas flow ratios of greater than 10 to 1, hydrogen to carbon tetra-fluoride. A nominal flow ratio of 300 to 20, hydrogen to carbon tetra-fluoride, or 15 to 1, was developed.

Abstract: This invention provides a semiconductor device that can ensure that stress on the nitride film is not increased or is reduced, and that can prevent an increase in interconnection capacity. The semiconductor device comprises a underlayer, a base oxide film that is formed on this underlayer, a nitride film pattern with a hole pattern that is provided on this base oxide film, holes that penetrate the base oxide film, an upper oxide film provided on the base oxide film to cover the nitride film pattern, wiring grooves provided through the upper oxide film in which part of the nitride film pattern including the hole pattern is exposed, and wiring metal that fills the holes and wiring grooves. The nitride film pattern is formed with such a shape and size that surrounds the outside of the wiring grooves and is separate from neighbouring nitride film patterns.

Abstract: A sloped via contact is used to connect a contact on the front side of a wafer to a contact on the back side of the wafer. The walls of a small (less than 50-80 microns wide) via have typically been difficult to coat with metal. The present invention forms a small via with sloped walls, allowing easy access to the inside walls of the via for metal sputtering or plating. The small via can be formed using a dry etch process such as the well-known deep reactive ion etching (DRIE) process. Using any isotropic plasma etch process, the walls of the via are further etched from the wafer backside to create sloped walls in the via. The via is then coated with metal to make it conductive.

Abstract: A semiconductor device having reliable electrode contacts. First, an interlayer dielectric film is formed from a resinous material. Then, window holes are formed. The interlayer dielectric film is recessed by oxygen plasma. This gives rise to tapering window holes. This makes it easy to make contacts even if the circuit pattern is complex.

Abstract: A portion, positioned at an opening portion of a resist, of an anti-reflection film is etched using an etching gas containing a substituted hydrocarbon with a halogen. At the time of etching of the anti-reflection film, a carbon component of the substituted hydrocarbon with a halogen is formed as a carbonaceous deposit on side walls, less irradiated with ions, of the opening portion of the resist, and on side walls of an opening portion, formed by etching, of the anti-reflection film. The deposit acts as a side wall blocking film, to suppress lateral extension of the opening portion of the resist and the opening portion of the anti-reflection film by etching, thus allowing anisotropic etching of the anti-reflection film. With this etching method, it is possible to etch the anti-reflection film with a resist taken as a mask while suppressing a variation in pattern dimension.

Abstract: A method for treating a dielectric material using hydrocarbon plasma is described, which allows for thinner films of barrier material to be used to form a robust barrier.

Abstract: A method of increasing mechanical interlocking between a first structure and a second adjacent structure in an integrated circuit. The first structure is formed with a first surface having a first horizontal component, and the second structure is formed with a second surface having a second horizontal component. The first surface laterally engages the second surface and the first horizontal component is complementary to the second horizontal component, such that the first structure prohibits vertical movement of the second structure.

Abstract: A method for fabricating a semiconductor device has the steps of forming a conductive film on a substrate, forming an insulating film such that the conductive film is covered with the insulating film, forming, in the insulating film, a hole having a bottom portion not reaching the conductive film by using a mask having a first opening pattern, and forming, in the insulating film, an opening for exposing the conductive film by using a mask having a second opening pattern having an opening diameter larger than an opening diameter of the first opening pattern. An obtuse angle is formed between a wall surface of the opening and a bottom surface of the opening.

Abstract: Embodiments concern contacts for use in integrated circuits, and methods of their manufacture, which result in a reduced likelihood of shorting between unrelated portions of an overlying conductive layer across misaligned contacts. Embodiments of the method involve performing a first etching process to pattern the conductive layer, where the etching compound used in the first etching process is relatively selective to the conductive layer's materials. Embodiments of the method also involve performing a second, contact related etching process that removes a portion of any misaligned contacts that were exposed by the first etching process, where the etching compound used in the second etching process is selective to the contacts' materials. The embodiments of the method could be used to form vias and other interconnect structures as well.

Abstract: A method for forming a wafer package includes forming a die structure, wherein the die structure includes a first wafer, a device mounted on the first wafer, a second wafer mounted atop the first wafer with a first seal ring around the device and a second seal ring around a via contact. The method further includes forming a trench in the second wafer around the first seal ring, filling the trench and the via contact with a sealing agent, patterning a topside of the second wafer to removed the excessive sealing agent and to expose a contact pad of the via contact, and singulating a die around the first seal ring.

Abstract: According to the present invention, of the resist film applied to the entire surface of the silicon substrate, the part on the electrode pattern is removed and an opening shaped like a dish in which the diameter of the upper part is larger than that of the lower part is formed, wherein the diameter of the lower part is smaller than the outer diameter of the electrode pattern. The electrode pattern exposed at the bottom of the opening is removed by the etching process. Next, the silicon substrate is tilted and a laser beam is irradiated toward the silicon substrate exposed at the bottom of the opening with water running over the surface of the resist film in air, and a hole is formed.

Abstract: A first dielectric layer (30) and a second dielectric layer (40) are formed over an etch stop layer (20). A hardmask layer (50) is formed over the second dielectric layer and a via (62) is formed in the first dielectric layer (30) and the second dielectric layer (40). A trench (85) is formed mostly in the second dielectric layer (40) by fully or partially removing BARC from the via (62) are partially etching the trench (85) and prior to completion of the trench etch process.

Abstract: A method for making a semiconductor device is described. That method includes forming a sacrificial layer on a substrate, then forming a layer of photoresist on the sacrificial layer. After the photoresist layer is patterned, to form a patterned photoresist layer that has a first opening, a first part of the sacrificial layer is removed to generate an etched sacrificial layer that has a tapered etch profile. A second part of the sacrificial layer is then removed to generate an etched sacrificial layer that has a second opening that is substantially smaller than the first opening.

Abstract: A method of forming an organosilicate low dielectric constant insulating layer (40) in an integrated circuit, and an integrated circuit structure having such a low-k insulating layer (40), are disclosed. In the case where the low-k dielectric material of the insulating layer (40) comprises an organosilicate glass, subsequent plasma processing has been observed to break bonds between silicon and organic moieties, either by replacing an organic group with a hydroxyl group or with hydrogen, or by leaving a dangling bond. Eventually, the damaged insulating layer (40) includes silanol molecules, which results in a degraded film. The disclosed method exposes the damaged insulating layer (40) to a silylation agent such as hexamethyldisilazane, which reacts with the damaged molecules, and forms molecules that restore the properties of the film.

Abstract: A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.

Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality. An alternating process can also be arranged by selection of pulse separation and/or pulse duration to achieve reduced conformality relative to a self-saturating, self-limiting atomic layer deposition (ALD) process. In still another arrangement, layers with anisotropic pore structures can be sealed by selectively melting upper surfaces. Blocking is followed by a self-limiting, self-saturating atomic layer deposition (ALD) reactions without significantly filling the pores.

Abstract: An LCD panel is provided, the LCD panel having a substrate, a conductive layer positioned on the substrate, and a dielectric layer disposed on the surface of the conductive layer. First, a photoresist layer with an opening is formed on the dielectric layer. An etching process is then performed to form a contact hole along the opening. After that, a post treatment process is performed to form a protective layer to reduce damage on the conductive layer when the photoresist layer is stripped.

Abstract: A method for making a semiconductor device is described. That method includes forming a sacrificial layer on a substrate, then forming a layer of photoresist on the sacrificial layer. After the photoresist layer is patterned, to form a patterned photoresist layer that has a first opening, part of the sacrificial layer is removed to generate an etched sacrificial layer that has a second opening that is substantially smaller than the first opening.

Abstract: A lower portion of an interlayer insulating film is formed contiguous with a semiconductor wafer. The lower portion has a high impurity concentration and a high etching rate. An upper portion of an interlayer insulating film is formed over the lower portion apart from the semiconductor wafer. The upper portion has a low impurity concentration and a low etching rate. A plurality of contact holes are formed through the interlayer insulating film by anisotropic etching. The bottom portion of each contact hole is expanded by isotropic etching, and a contact is formed in the contact hole. Thus, a satisfactory contact is formed in a hole of a large aspect ratio.

Abstract: In order to fabricate a metallization plane with lines and contacts, four dielectric layers are applied to a substrate. Firstly, contact holes are etched through the top two dielectric layers into the underlying dielectric layer, the remaining thickness of the latter layer being essentially equal to the thickness of the top layer. Line trenches are subsequently etched selectively with respect to the first dielectric layer and the third dielectric layer, whose surfaces are uncovered essentially simultaneously. After the first dielectric layer and the third dielectric layer have been patterned, contacts and lines are produced in the contact holes and line trenches.

Abstract: A semiconductor device and method for fabricating same according to an embodiment of the invention includes: preparing a semiconductor substrate having a first contact pad and a second contact pad; forming a first insulating film on the substrate; etching the first insulating film to form a groove-shaped bit line pattern and a contact exposing the first contact pad and the second contact pad, respectively; simultaneously forming a contact plug and a bit line in the contact and the bit line pattern, respectively, the contact plug and the bitline having upper surfaces that are coplanar; and forming a bottom electrode for a capacitor that is connected to the first contact pad.

Abstract: A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP.

Abstract: A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as opposed to the conventional square or rectangular cross section of interconnect lines.

Abstract: A semiconductor device includes a conductive region and line, and a contact plug electrically connecting the line and the region. The line is connected to the region via sidewalls of the plug, and the region is connected to the line via the bottom of the plug. The cross-sectional area of the plug decreases in a direction from an upper to lower portion thereof. In a first method of fabricating a semiconductor device having a self-aligned contact, the plug is formed after the line is formed in an interlayer dielectric layer. Portions of the dielectric layer and line are etched to form a contact hole in which the plug is formed. In a second method, a line having a gap therein is formed in an interlayer dielectric layer. Portions of the dielectric layer, including the gap in the line, are etched to form the contact hole.

Abstract: A process for forming a bond pad structure to be used to accommodate a subsequent wire bond, has been developed. The process features defining a bond pad opening in a composite insulator stack, exposing a portion of a top surface of an upper level metal interconnect structure at the bottom of the bond pad opening. The bond pad opening is formed with a top portion of the composite insulator stack laterally pulled back from a bottom portion of the same composite insulator stack. The bond pad structure, comprised of aluminum—copper, is then formed entirely in the bond pad opening, with the top surface of the bond pad structure lower than the top surface of the composite insulator stack, thus resulting in a bond pad structure topography offering reduced risk of damage during subsequent pre-wire bonding procedures.

Abstract: A semiconductor device, enabling reliable electrical connection of a main electrode pad with an interconnection pattern without separate provision of a via use electrode pad in addition to the existing main electrode pad, provided with a silicon substrate (semiconductor substrate), an electronic element formation layer formed on one surface of that silicon substrate, an electrode pad having an extension and electrically connected to the electronic element formation layer, a through hole passing through the electrode pad and the silicon substrate, an SiO2 film (insulating film), a via hole provided in the SiO2 film on the extension of the electrode pad, and an interconnection pattern electrically leading out the electrode pad to the other surface of the silicon substrate through the through hole and via hole, said through hole having a diameter larger at a portion passing through the electrode pad than a portion passing through the semiconductor substrate.

Abstract: A semiconductor device having a metallized interconnect structure includes a conductor having an upper contact surface and an edge surface depending from the upper contact surface. An opening in an insulating layer overlying the conduct exposes at least a portion of the upper contact surface and at least a portion of edge surface. A liner material covers the edge surface and a portion of the upper contact surface exposed by the opening. An electrically conductive material resides within the opening and is separated from the edge surface by the liner material. A method for fabricating the metallized contact structure includes the deposition and anisotrophic etching of a liner material that is differentially etchable with respect to the insulating layer overlying the conductor. By covering the edge surface of the conductor, a metallized contact structure is provided that can be reliably fabricated using zero-overlap design tolerances.

Abstract: Method and structures are provided for conformal lining of dual damascene structures in integrated circuits, and particularly of openings formed in porous materials. Trenches and contact vias are formed in insulating layers. The pores on the sidewalls of the trenches and vias are blocked, and then the structure is exposed to alternating chemistries to form monolayers of a desired lining material. In exemplary process flows chemical or physical vapor deposition (CVD or PVD) of a sealing layer blocks the pores due to imperfect conformality, and is followed by an atomic layer deposition (ALD), particularly alternately pulsed metal halide and ammonia gases injected into a constant carrier flow. An alternating process can also be arranged to function in CVD-mode within pores of the insulator, since the reactants do not easily purge from the pores between pulses. Self-terminated metal layers are thus reacted with nitrogen.

Abstract: After an etching stop layer and an interlayer dielectric film are formed on a semiconductor substrate including a contact formation portion, a polysilicon film and a anti-reflective layer are successively formed on the interlayer dielectric film. A second mask pattern exposing the polysilicon film is formed after etching the anti-reflective layer exposed through a first mask pattern. A third mask pattern is formed by attaching polymer on a sidewall of the second mask pattern. A contact hole exposing the contact formation portion is formed by etching the polysilicon film and the interlayer dielectric film using the third mask pattern as an etching mask. A conductive material is filled in the contact hole to form the contact. By attaching the polymer to the second mask pattern, a contact hole with a minute size can be formed.

Abstract: A method for manufacturing a substrate, including adhering an adhesive layer to an organic insulation substrate to form a first part; forming a via hole in the first part such that the via hole penetrates the first part; forming a conductive metal film so that the conductive metal film covers the via-hole on one side of the first part; using an electrolytic plating process, where the conductive metal Film is used as an electrode, to form a metal via member within the via hole and to form an inter-layer wire; and removing an entirety of the conductive metal film without removing the inter-layer formed by the electrolytic plating process; repeating steps (a)-(e) for a second part; and thereafter attaching the first part to the second part.

Abstract: The invention relates to a compact semiconductor structure comprising an insulation layer on a semiconductor substrate and at least two metallic conductor strips (7, 8) in said insulation layer. The invention aims to reduce the capacitive coupling between the neighbouring metallic conductor strips of a semiconductor structure and to enable the production of a more compact semiconductor structure. To achieve this, the inventive semiconductor device is characterised in that the insulation layer comprises a first insulation layer (1) of a predetermined thickness consisting of a first insulation material and a second insulation layer (10) of a predetermined thickness consisting of a second insulation material and located above the first insulation layer (1). The two or more metallic conductor strips (7, 8) extend from the first insulation layer (1) into the second insulation layer (10) and the second insulation material has a lower relative dielectric constant than the first insulation material.

Abstract: A semiconductor-device fabrication method includes a step of forming a contact hole in a semiconductor substrate 1 and a step of forming a conductive contact hole. The step of forming the contact hole is performed by repeating two times or more a burying step of depositing a conductive material 5 to bury the conductive material in the contact hole and an etch-back step of removing the conductive material around the contact hole by etch back.

Abstract: A method for making a semiconductor device is described. That method includes forming a sacrificial layer on a substrate, then forming a layer of photoresist on the sacrificial layer. After the photoresist layer is patterned, to form a patterned photoresist layer that has a first opening, part of the sacrificial layer is removed to generate an etched sacrificial layer that has a second opening that is substantially smaller than the first opening.

Abstract: A method of fabricating a sub-lithographic sized via is disclosed. A dual-polymer method is used to form a stacked layer of polymer materials wherein a first polymer layer has a first etch rate and a second polymer layer has a second etch rate. The first etch rate is preselected to be faster than the second etch rate when the first and second polymer layers are isotropically etched. The second polymer layer is made from a photo active material and is operative as an etch mask for the first photoresist layer. The etching is continued until the first polymer layer has a sub-lithographic feature size that is less than a lithography limit of a lithography system. A dielectric material is deposited on the etch mask and the first polymer layer. The first polymer layer is lifted-off to define a sub-lithographic sized via.

Abstract: A multilayer printed wiring board is formed with a plurality of conductor layers laminated as a whole with insulating layers interposed, a non-penetrating via hole provided in the insulating layer as bottomed by the conductor layer exposed, a plated layer provided inside the via hole for electric connection between the conductor layers, the via hole being formed to be of a concave curved surface of a radius in a range of 20 to 100 &mgr;m in axially sectioned view at continuing zone of inner periphery to bottom surface of the via hole, whereby the equipotential surfaces occurring upon plating the plated layer are curved along the continuing zone to unify the density of current for rendering the plated layer uniform in the thickness without being thinned at the continuing zone.

Abstract: A method of manufacturing a semiconductor device comprises a step of forming a through-hole in a semiconductor chip having an electrode and forming a conductive layer on a region comprising an inner side of the through-hole. An intermediate portion of the through-hole is formed to be larger than an edge portion thereof, and the conductive layer is formed by electroless plating.

Abstract: A method of fabricating a semiconductor device includes steps of forming an interlayer dielectric film to cover upper sides of a bit line pad and a storage node pad defining a first conductive layer, simultaneously forming a plurality of contact holes reaching upper surface of the first conductive layer through the interlayer dielectric film, expanding in width upper portion of part of the aforementioned plurality of contact holes, thereby forming a trench for a second conductive layer, and arranging conductors in the aforementioned plurality of contact holes and the aforementioned trench for a second conductive layer. Thus, a bit line contact, a storage node contact and a bit line serving as the second conductive layer are obtained.

Abstract: A hard mask made from polysilicon is used to etch a layer to be patterned. The hard mask is patterned using a resist mask. The etching of the hard mask is carried out in such a way that the openings which are etched into the hard mask have inclined sidewalls. This reduces the cross section of the openings, with the result that smaller openings can be formed in the layer that is to be patterned than the openings which have been predetermined by the resist mask. The hard mask is etched using only HBr. The inclination of the openings etched into the hard mask can be set by way of the TCP power and/or the bias power of a TCP etching chamber, and/or by way of the HBr flow rate.

Abstract: A shadow mask is applicable to forming a minute film on a substrate by evaporation or the like. The shadow mask comprises a support film, a stopper film, a polyimide film and a thin plate. The support film has enough mechanical strength necessary for forming predetermined sized holes. The stopper film is formed on the support film and is used as an etching stopper while forming the holes in the support film. The polyimide film is formed on the stopper film and bonds the stopper film to the thin plate. The thin plate is formed on the polyimide film and is made of a material which is the same as that of the substrate on which the film is formed or a material whose thermal expansion rate is substantially the same as that of the substrate. Openings of the shadow mask are formed at predetermined regions through the support film, the stopper film, the polyimide film and the thin plate. Each of the openings has a tapered portion and a projected portion.

Abstract: A method for selectively anisotropically a semiconductor feature to form a tapered sidewall profile including providing a semiconductor wafer including an anisotropically etched feature formed in at least one dielectric insulating layer including a relatively larger width dimension portion overlying and encompassing at least one relatively smaller diameter dimension portion the smaller diameter dimension portion further including a bottom portion including an overlying liner; and, selectively anisotropically etching the anisotropically etched feature according to a reactive ion etching (RIE) process to form a tapered sidewall portion of the at least one relatively smaller diameter portion.