Abstract: A method of forming a contact opening between two conductive features over a semiconductor substrate. Oxide spacers are formed adjacent to the conductive features. A doped oxide layer is then deposited over the semiconductor substrate. Finally, the contact opening is etched through the doped oxide layer between the conductive features such that the oxide spacers are exposed within the contact opening.

Abstract: A system for estimating a plasma damage for subsequent layout design of a semiconductor device includes an antenna ratio extraction unit for extracting an antenna ratio from each of existing provisional layout patterns to be exposed to plasma in each of plasma processes. An index calculation unit is connected to the antenna ratio extraction unit for receiving the antenna ratio extracted by the antenna ratio extraction unit and calculating an individual damage index representing a degree of a plasma damage in accordance with the antenna ratio. An index addition unit is connected to the index calculation unit for receiving the individual damage indexes from the index calculation unit and adding the individual damage indexes to estimate a plasma damage.

Abstract: The present invention discloses a technique of enhancing adhesion between a passivation layer and a low-K dielectric layer, in which a SiO2 layer as the passivation formed on the low-K dielectric layer is subjected to N2O plasma annealing. This technique is useful in improving the yield of a process for preparing Cu damascene interconnection.

Abstract: A metalization process forms metal contacts having defined profiles for contact between microelectromechanical (MEMS) devices or chemical sensors with semiconductor devices. Gold contacts may be used for connecting the MEMS devices or chemical sensors to integrated CMOS devices. Gold contacts are deposited over a photoresist via having sidewalls for forming upwardly extending flanges. The metal contacts to the underlying semiconductor device, are formed using a polymethylmethacrylate (PMMA) etch back process for exposing and dissolving the gold metalization layer save the metal contact under a surviving portion of the etched back PMMA layer in a dimple of the gold layer over the photoresist via. The photoresist layer serves to form deep well gold contacts having upwardly extending flanges for connection to the MEMS devices or chemical sensors and to the integrated semiconductor devices.

Abstract: In a semiconductor integrated circuit having improvement in integration, it is an object of the present invention to provide a structure ensuring a contact area between a contact plug and a conductive layer formed thereon and connected thereto, to thereby realize reduction in contact resistance. A plurality of bit lines (8) are selectively formed in an interlayer insulating film (9). Each of the bit lines (8) is connected to a predetermined impurity diffusion layer (2) through a contact plug (7). The upper surface of a contact plug (10) as an end opposite to the lower surface thereof protrudes from the main surface of the interlayer insulating film (9). On the contact plug (10), a capacitor lower electrode (11) is formed to cover the protruding part of the contact plug (10) in such a manner that the center of the capacitor lower electrode (11) is located at a position deviated from the center of the contact plug (10).

Abstract: An auxiliary capacitor for a pixel of an active matrix type liquid crystal display is provided without decreasing the aperture ratio. A transparent conductive film for a common electrode is formed under a pixel electrode constituted by a transparent conductive film with an insulation film provided therebetween. Further, the transparent conductive film for the common electrode is maintained at fixed potential, formed so as to cover a gate bus line and a source bus line, and configured such that signals on each bus line are not applied to the pixel electrode. The pixel electrode is disposed so that all edges thereof overlap the gate bus line and source bus line. As a result, each of the bus lines serves as a black matrix. Further, the pixel electrode overlaps the transparent conductive film for the common electrode to form a storage capacitor.

Abstract: A structure and method for determining barrier layer integrity for multi-level copper metallization structures in integrated circuit manufacturing. Novel testing structures prevent any conducting residues of the copper CMP from diffusing into the dielectric layer. Barrier layer integrity is tested by performing CV or IV measurements between the copper lines and the silicon wafer.

Abstract: A semiconductor device and a method of manufacturing thereof are provided wherein no hollow area is generated in a contact wiring plug which is formed in the interlayer insulation layer. According to the method of manufacturing of this semiconductor device, a contact wiring plug 13 of a two layered structure of a barrier metal layer and a tungsten layer is formed by using a spattering method or the like. At this time, since the recessed part 10a has a shape which gradually spreads to the outside to a greater degree in relation to the closeness to the upper surface, the formation of the contact wiring plug 13 is carried out under excellent covering conditions. As a result, a semiconductor device wherein no hollow area is generated in the contact wiring plug, which is formed in the interlayer insulation layer, can be gained.

Abstract: A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics.

Abstract: Disclosed is a method for forming a contact portion of a semiconductor element. An exemplary method includes the steps of depositing an insulation layer on a lower thin film on which there is formed a semiconductor element electrode or a metal wiring pattern, and then realizing an even upper surface of the insulation layer; forming a photosensitive film pattern thereon having a contact or via hole pattern in which inner walls of the contact holes or via holes smoothly curve downward to reach an upper surface of the insulation layer; dry-etching the insulation layer using a mask following the photosensitive film pattern to form contact holes or via holes; removing the photosensitive film pattern, then depositing a barrier metal and tungsten to fill the contact holes or the via holes; and performing a chemical mechanical polishing process to remove the barrier metal and the tungsten from the upper surface of the semiconductor element until the insulation layer is exposed and a flat surface is realized.

Abstract: The present invention relates to lithographic methods for forming a dual relief pattern in a substrate, and the application of such methods to fabricating multilevel interconnect structures in semiconductor chips by a Dual Damascene process in which dual relief cavities formed in a dielectric are filled with conductive material to form the wiring and via levels. The invention comprises a twice patterned single mask layer Dual Damascene process modified by the addition of an easy-to-integrate sidewall liner to protect organic interlevel and intralevel dielectrics from potential damage induced by photoresist stripping steps during lithographic rework. The invention further comprises a method for forming a dual pattern hard mask which may be used to form dual relief cavities for use in Dual Damascene processing, said dual pattern hard mask comprising a first set of one or more layers with a first pattern, and a second set of one or more layers with a second pattern.

Abstract: A method for forming a contact hole having a stepped sidewall is disclosed. First, a capping layer is formed on a semiconductor substrate, and then, a first dielectric layer and a second dielectric layer having different etch rates are formed on the capping layer. A preliminary contact hole is anisotropically etched through the layers, and part of the way through the substrate. After this, the sidewalls of the preliminary contact hole are isotropically etched with an etching agent having a higher etch rate for the second dielectric layer than for the first dielectric layer, thereby forming a step sidewall. Finally, the exposed portions of the capping layer are removed to complete the contact hole fabrication.

Abstract: A novel structure of an active electro-optical device is disclosed. The device is provided with complementary thin film insulated gate field effect transistors (TFTs) therein which comprise a P-TFT and an N-TFT. P-TFT and N-TFT are connected to a common signal line by the gate electrodes thereof, while the source (or drain) electrodes thereof are connected to a common signal line as a well as to one of the picture element electrodes. In case of driving the active electro-optical device, a gradation display can be carried out in a driving method having a display timing determined in relation to a time F for writing one screen and a time (t) for writing in one picture element, by applying a reference signal in a cycle of the time (t), to the signal line used for a certain picture element driving selection, and by applying the select signal to the other signal line at a certain timing within the time (t), and whereby setting the value of the voltage to be applied to a liquid crystal.

Abstract: A high integrity, reliable liner is disclosed for a via in which a titanium aluminide layer is preformed as a lining within a via hole prior to deposition of other conductive materials within the via hole. The conductive materials deposited on the preformed titanium aluminide can be either a secondary barrier layer portion of the liner, such as a titanium compound layer, which in turn has a metal plug deposited thereon, or, alternatively, a metal plug directly deposited on the titanium aluminide layer. An important advantage achieved by the present invention is that a via is formed with a substantial elimination of void formation. The enhanced vias are useful in a wide variety of semiconductor devices, including SRAMS and DRAMs.

Abstract: A method for forming a contact plug without a dimple surface is provided. The present method is characterized in that forming a trench-shaped opening penetrating a dielectric layer formed on a semiconductor substructure having a lower electrical conductor, and forming a liner layer with a tapered width decreasing from the top of the trench-shaped opening to the bottom thereof, and then forming a conductive plug to fill the trench-shaped opening. Since the width of the liner layer is decreased gradually from the top of the trench-shaped opening, a seam is formed in the trench-shaped opening below the surface of the dielectric layer when depositing a conductive layer over the dielectric layer and the trench-shaped opening for the conductive plug. Thereby, a conductive plug without a dimple surface is formed in the trench-shaped opening by etching back the conductive layer.

Abstract: The present invention provides a semiconductive substrate which includes front and back surfaces and a hole which extends through the substrate and between the front and back surfaces. The hole is defined in part by an interior wall portion and forms an outer conductive sheath. Conductive material is formed proximate at least some of the interior wall portion. Subsequently, a layer of dielectric material is formed within the hole, over and radially inwardly of the conductive material. A second conductive material is then formed within the hole over and radially inwardly of the dielectric material layer. The latter conductive material constitutes an inner conductive coaxial line component.

Abstract: The present invention provides a method of automatically defining a landing via on a semiconductor wafer. The present invention involves first forming a conductive layer and a photoresist layer on the surface of the semiconductor wafer. Then, patterns of a plurality of word lines are defined on the surface of the photoresist layer, and patterns of a plurality of auxiliaries are defined around the area predetermined to form the landing via between each two word lines on the surface of the photoresist layer. Thereafter, the patterned photoresist layer is used as a hard mask to etch the conductive layer to form each word line on the semiconductor wafer, and to simultaneously form the auxiliaries around the area predetermined to form the landing via. Finally, a plurality of spacers are formed around each word line and each auxiliary dovetail together to form a landing via hole and to automatically define the position of the landing via.

Abstract: A structure of a DRAM and a manufacturing process therefor, suitable for a substrate on which a plurality of word lines and a plurality of source/drain regions on sides of each of these word lines are formed. A plurality of bit line contacts and a plurality of node contacts are formed in electric contact with the source/drain regions. A first patterned insulating layer is formed on the substrate, in which a plurality of openings are formed in the insulating layer to expose the bit line contacts. The substrate is covered with a first conductive layer and a second insulating layer in sequence. The second insulating layer, the first conductive layer and the first insulating layer are patterned in sequence to form a plurality of bit line stacked structures and a plurality of bit lines electrically connecting to the bit contacts, exposing the node contacts. As a result, the bit line stacked structure forms a plurality of trenches and the bit line stacked structure is orthogonal to the word lines.

Abstract: The dual damascene method having steps of; after a first insulating film, a first organic insulating film, a second insulating film, and a metal film are formed in sequence, a first opening having a wiring pattern is formed in the metal film, then a second opening having a via pattern is formed in the second insulating film, then the first organic insulating film is etched using the second insulating film as a mask, then the first insulating film and the second insulating film are etched simultaneously while using the metal film and the first organic insulating film as a mask, and then the first organic insulating film is etched while using the metal film as a mask, at this stage, a wiring recess is formed in the first organic insulating film and the second insulating film, and a via-hole is formed in the first insulating film.

Abstract: A method for forming a line of a semiconductor device is provided, which improves the life span of the line and its reliability by improving resistance to electromigration (EM).

Abstract: An interconnect fabrication process and structure provides barrier enhancement at the via sidewalls and improved capability to fabricate high aspect ratio dual damascene interconnects. A via structure is patterned into the via dielectric first, then a dielectric barrier (for example, anisotropically etched silicon nitride) is formed only along the via sidewalls in the dual damascene structure prior to deposition of a metal barrier (for example, Ta/TaN). In this way, the effective barrier thickness along the bottom of the via is increased, eliminating the structure's susceptibility to metal migration. The absence of dielectric barrier along the interconnect trench sidewalls leads to low interconnect resistance and low interconnect capacitance. The present invention also provides an improved fabrication method for obtaining high aspect ratio dual damascene interconnect structures.

Abstract: A fabrication method for a dual damascene structure is provided. A barrier layer and a copper seed layer are formed on a substrate comprising a dual damascene opening, wherein the barrier layer and the copper seed layer cover the dual damascene opening. A sacrificial layer is then formed on the copper seed layer, filling the dual damascene opening. Using the copper seed layer as an etch stop layer, the sacrificial layer is etch back. The exposed copper seed layer is then removed, followed by completely removing the sacrificial layer. A metal copper layer is formed in the dual damascene opening by plating, filling the opening of the dual damascene opening.

Abstract: A structure suitable for connecting an integrated circuit to a supporting substrate wherein the structure has thermal expansion characteristics well-matched to the integrated circuit is an interposer. The integrated circuit and the interposer are comprised of bodies that have substantially similar coefficients of thermal expansion. The interposer has a first surface adapted to electrically and mechanically couple to the integrated circuit. The interposer has a second surface adapted to electrically and mechanically couple to a supporting substrate. Electrically conductive vias provide signal pathways between the first surface and the second surface of the interposer. Various circuit elements may be incorporated into the interposer. These circuit elements may be active, passive, or a combination of active and passive elements.

Abstract: A method for fabricating a metal conductor in a semiconductor device includes forming a trench in a dielectric layer of the semiconductor device. The method also includes depositing a first conducting material within the trench to form a continuous liner layer within the trench. The liner layer is formed at a first predetermined temperature. The method further includes filling a remaining portion of the trench over the liner layer with a second conducting material at a second predetermined temperature. The second predetermined temperature is greater than the first predetermined temperature.

Abstract: The present invention is a contact/via comprising and its method of fabrication. The contact/via of the present invention includes a conductive film. An opening having a top and bottom is formed on the conductive film. The opening has a first sidewall and a second sidewall wherein the first sidewall is opposite the second sidewall. The first sidewall has a stair step configuration such that the first sidewall is closer to the second sidewall at the bottom of the opening than at the top of the opening. A conductive film is then formed on the first sidewall in the opening and on the bottom of the opening on the conductive film.

Abstract: A metal contact structure of a semiconductor device and a method for forming the same are provided. The diameter of the upper portion of a contact hole that exposes a region of a lower conductive layer is formed to be larger than the diameter of the lower portion of the contact hole. The metal contact structure is formed without a void or a key hole. This is accomplished by forming at least two metal layers to fill the contact hole by performing a first deposition, an etch back, and a second deposition. The metal layer which fills the contact hole is etched back using a barrier metal layer formed on the entire surface of the contact hole as an etching stop layer. Thus, a void or key hole is not generated by making the upper portion of the contact hole to be wider than the lower portion of the contact hole and by depositing the metal which fills the contact hole through the processes of firstly depositing the metal, etching back the metal, and secondly depositing the metal.

Abstract: A dual damascene manufacturing process, which is applicable on a dual damascene structure, is described. The etching stop layer at a bottom of the trench line is removed followed by a thermal treatment to smooth out the surface at the bottom of the trench line and in the via to form a larger and smoother opening at the top part of the via. The via and the trench line are then filled with a barrier layer and a metal layer.

Abstract: A method for electrically linking the contacts of a semiconductor device to their corresponding digit lines includes disposing a quantity of mask material into a trench through which the contact is exposed. The mask also abuts a connect region of a conductive element of a corresponding conductive line and, therefore, protrudes somewhat over a surface of the semiconductor device. A layer of insulative material is formed over the semiconductor device with the mask exposed therethrough. The mask is then removed, leaving open cavities, including the trench and a strap region continuous with both the trench and a connect region of the corresponding conductive line. Conductive material is introduced into each open cavity to define conductive plugs or studs and conductive straps that are electrically isolated from one another. Semiconductor devices including features that have been fabricated in accordance with the method are also within the scope of the present invention.

Abstract: A lower portion of an interlayer insulating film is formed contiguous with a semiconductor wafer. The lower portion has a high impurity concentration and a high etching rate. An upper portion of an interlayer insulating film is formed over the lower portion apart from the semiconductor wafer. The upper portion has a low impurity concentration and a low etching rate. A plurality of contact holes are formed through the interlayer insulating film by anisotropic etching. The bottom portion of each contact hole is expanded by isotropic etching, and a contact is formed in the contact hole. Thus, a satisfactory contact is formed in a hole of a large aspect ratio.

Abstract: A manufacturing process which enables the opening of a downwardly protruding window for a dual damascene structure, etc. both easily and in a well-controlled fashion even in a case where the opening is small. After a depression constituted by a silicon nitride film, etc. has been configured above an interlayer insulating film, a mask is obtained by configuring a window on a portion of it in such a way that said interlayer insulating film will become bared to its bottom. Next, this mask is etched back, followed by the etching of the interlayer insulating film underneath, as a result of the interlayer insulating film becomes etched while the thickness disparity within the mask is being reflected by the corresponding attribute of the interlayer insulating film underneath, and accordingly, a downwardly protruding window (e.g., dual damascene structure, etc.) can be easily formed within said interlayer insulating film.

Abstract: A method for forming a contact hole in a semiconductor device includes the steps of forming a polymer layer on an upper portion and a side wall of photo resist mask, while etching an oxide layer under the photoresist mask to form a contact hole that uses an etchant gas comprising CH2F2 gas; and etching the oxide layer while stopping the supply of CH2F2 gas to the etching process.

Abstract: A method for forming, within a low dielectric constant dielectric layer formed upon a substrate employed within a microelectronics fabrication, a conductor pattern employing a hard mask cap layer. There is first provided a substrate having conductor regions formed therein upon which is formed a low dielectric constant dielectric layer. There is then formed over the substrate a silicon containing hard mask cap layer. There is then formed over the hard mask cap layer a patterned photoresist etch mask layer. There is then subtractively etched employing the patterned photoresist etch mask layer and a first subtractive etching environment the pattern into the hard mask layer. There is then subtractively etched employing the patterned hard mask layer and a second etching environment the pattern into the low dielectric constant dielectric layer, simultaneously stripping the photoresist etch mask layer.

Abstract: A dual damascene process is disclosed, in which a contact via and trench pattern is etched into insulating layer(s). The via is first partially filled by selective metal (e.g., tungsten) deposition, thereby forming a partial plug that raises the floor and reduces the effective aspect ratio of the trench and via structure. The remaining portion of the contact via is then filled with a more conductive material (e.g., aluminum). This deposition also at least partially fills the overlying trench to form metal runners. In the illustrated embodiment, hot aluminum deposition fills the portion of the contact via left unoccupied by the selective deposition and overfills into the trench. A further, cold aluminum deposition then follows, topping off the trench prior to planarization.

Abstract: Embedded interconnections of copper are formed by forming an insulating layer, forming embedded interconnections of copper in the insulating layer, making an exposed upper surface of the insulating layer and an exposed surface of the embedded interconnections of copper coplanar according to chemical mechanical polishing, and forming a protective silver film on the exposed surface of the embedded interconnections of copper. These steps are repeated on the existing insulating layer thereby to produce multiple layers of embedded interconnections of copper. The exposed surface of the embedded interconnections of copper is plated with silver according to immersion plating.

Abstract: The bit lines composed of a conductive film containing the tungsten as a principal component are formed inside the side wall spacers formed on the side walls of the wiring grooves. The TiN film having a higher adhesive strength to the silicon oxide than the tungsten is formed on the boundary faces between the bit lines and the side wall spacers, which functions as an adhesive layer that prevents strippings on the boundary faces between the bit lines and the side wall spacers. Thereby, the invention prevents disconnections, even when the width of the wirings having the tungsten as the principal component is fined to 0.1 &mgr;m or less.

Abstract: A method of etching trenches through a low-k material layer using a hard mask wherein the trenches are sized down from the mask size by etching without sacrificing a vertical trench profile is described. A low-k dielectric material is provided over a region to be contacted on a substrate. A hard mask layer is deposited overlying the dielectric material. A mask is formed over the hard mask layer wherein the mask has a first opening of a first width. A second opening is etched in the hard mask layer where it is exposed by the mask wherein the second opening has a second width smaller than the first width and wherein the second opening has inwardly sloping sidewalls. A trench is etched through the dielectric layer to the region to be contacted through the second opening whereby the trench has a width equal to the second width. The trench is filled with a metal layer to complete fabrication of the integrated circuit device.

Abstract: There is provided a method of fabricating a semiconductor memory device including a memory cell having transistor and a capacitor, and a cylindrical accumulation electrode, the method including the steps of (a) forming a first insulating film on a lower interlayer insulating film, (b) forming at least one hole through the first insulating film so that the hole reaches the lower interlayer insulating film, (c) forming a polysilicon layer in the hole so that an upper surface of the polysilicon layer is located lower than an upper surface of the first insulating film, (d) covering the first insulating film and the polysilicon layer with a second insulating film, (e) etching back the second insulating film so that the second insulating film remains only on a sidewall of the first insulating film, and (f) etching the polysilicon layer with the second insulating film being used as a mask so that the polysilicon layer has a thickness different from a thickness of the first insulating film after the polysilicon layer

Abstract: A method of fabricating a gate. A gate dielectric layer is formed, and a lower portion of a floating gate is formed encompassed by a first dielectric layer. Second dielectric layers with different etching rates are formed to cover the upper portion of the floating gate and the first dielectric layer. Using an etching mask, an opening is formed within the second dielectric layer to expose the floating gate and a portion of the second dielectric layers by performing an anisotropic etching process. Using the same etching mask, the second dielectric layers exposed within the opening is further etched by performing an isotropic etching process. Due to the different etching rates, a dielectric layer with an uneven and enlarged surface is formed. A conformal conductive layer is formed on the exposed lower portion of the floating gate and the exposed second dielectric layers as an upper portion of the floating gate.

Abstract: A method of forming a dual damascene structure comprises the steps of providing a substrate having a first conductive layer formed thereon, and then sequentially forming a first dielectric layer, an anti-reflection layer and a second dielectric layer over the substrate. Next, the first dielectric layer, the anti-reflection layer and the second dielectric layer are patterned to form a first opening that exposes the conductive layer. Thereafter, the second dielectric layer is patterned to form a trench (or second opening) in a position above the first conductive layer. The trench and the first opening together form an opening of the dual damascene structure. Finally, a second conductive material is deposited into the opening and the trench to form conductive lines and the dual damascene structures.

Abstract: Interconnect structures comprising a substrate having a first level of electrically conductive features formed thereon; a patterned interlevel dielectric material formed on said substrate, wherein said patterned interlevel dielectric includes via spaces, wherein at least one of said via spaces is a slot via in which an anti-fuse material is formed on a portion thereof; and a second level of electrically conductive features formed in said spaces, whereby the anti-fuse material in the slot via provides a connection between the first and second levels of electrically conductive features and a method of fabricating the same.

Abstract: A semiconductor device includes a semiconductor substrate on which an element is formed, a lower wiring formed on the semiconductor substrate, and an upper wiring formed on and connected to the lower wiring. The upper wiring includes a plurality of regions having different thicknesses in a continuous wiring region excluding a connection region for connecting the upper and lower wirings.

Abstract: A method of manufacturing an electrical interconnection of a semiconductor device produces an erosion protecting plug in a contact hole to protect a selected portion of an interlayer dielectric layer when the interlayer dielectric layer is being etched to form a recess for a conductive line. The contact hole is formed in the interlayer dielectric layer. The contact hole is filled with an organic material to form the erosion protecting plug. The organic material is a photoresist material or an organic polymer. A photoresist pattern is formed for exposing the erosion protecting plug and a portion of the interlayer dielectric layer adjacent to the erosion protecting plug. A recess which extends down to the contact hole is formed by etching the portion of the interlayer dielectric layer which is exposed by the photoresist pattern. The erosion protecting plug and the photoresist pattern are then removed. A conductive line filling the recess and a contact filling the contact hole are then formed.

Abstract: The present invention is directed to a method for forming semiconductor devices and semiconductor device precursors having gradual slope contacts. The method for forming a semiconductor precursor includes the steps of: forming a layer of conductive material in a first layer; forming a layer of a hard mask material onto at least a portion of the first layer; etching the layer of hard mask material to expose a portion of the first layer; forming facets on the layer of hard mask material; and forming a via in the first layer such that the via extends through the first layer to expose at least a portion of the layer of conductive material.

Abstract: A method for forming void free tungsten plug contacts (56a-56c) begins by etching a contact opening (55a-55c) using a C2F6 and CHF3 chemistry. The etch chemistry is then changed to an O2 and CH3F chemistry in order to insitu remove the contact photoresist while tapering an upper portion of the contact opening. A tungsten deposition process is then performed whereby the tapered portion of the contact reduces the effects of nonconformal and step-coverage-inconsistent tungsten deposition wherein voids in the contact are either substantially reduced or totally avoided within the contact structure. The reduction of or total elimination of voids (22) within the tungsten contact will increase yield, increase reliability, and reduce electromigration failures within integrated circuit devices.

Abstract: A method of forming amorphous silicon spacers followed by the forming of metal nitride over the spacers in a copper damascene structure -single, dual, or multi-structure- is disclosed in order to prevent the formation of fluorides in copper. In a first embodiment, the interconnection between the copper damascene and an underlying copper metal layer is made by forming an opening from the dual damascene structure to the underlying copper layer after the formation of the metal nitride layer over the amorphous silicon spacers formed on the inside walls of the dual damascene structure. In the second embodiment, the interconnection between the dual damascene structure and the underlying copper line is made from the dual damascene structure by etching into the underlying copper layer after the forming of the amorphous silicon spacers and before the forming of the metal nitride layer.

Abstract: A method for forming a damascene interconnection. After forming an insulating layer on a semiconductor substrate, the insulating layer is patterned and etched to form an opening. A barrier layer is formed on an entire surface of a resulting structure where the opening is formed. A seed layer is formed on at least on a sidewall of the opening on which the barrier layer is formed, and on a top surface of the insulating layer, using an ionized physical vapor deposition (PVD) apparatus having a target to which a power for making plasma is applied, and a chuck to which a radio frequency (RF) bias for accelerating ions is applied. When the seed layer is formed using an ionized PVD process, the power and bias are controlled to resputter an initial seed layer formed on a bottom of the opening. The resputtered seed layer is redeposited on the sidewall of the opening, forming a seed layer with a good step coverage characteristic on the sidewall.

Abstract: A first insulating film, a first wiring layer and a second insulating film are successively formed over a semiconductor substrate. A resist mask is patterned over the second insulating film, and isotropic etching and anisotropic etching are successively carried out to define a plurality of via holes within the second insulating film. The via holes thus have a first portion formed by the isotropic etching and a second portion formed by the anisotropic etching. The resist mask is removed, and a high melting-point metal film is formed over the second insulating film so as to be embedded in the plurality of via holes. The high melting-point metal film and the second insulating film are then polished down to the first portion of each of the via holes such that respective portions of the high melting-point metal film formed within adjacent ones of the plurality of via holes are isolated from each other.

Abstract: The present invention relates to an improved method for forming a UBM pad and solder bump connection for a flip-chip which eliminates at least two mask steps required in standard UBM pad forming processes when repatterning the bond pad locations.

Abstract: A method for fabricating a locally reinforced metallic microfeature on a substrate provided preferably with an electrical contacting or a driving circuit, and on an organic, patterned sacrificial layer, which is removed after the metallic microfeature is applied, is described. In fabricating the local reinforcement of the microfeature, at least one further organic layer, formed as a mask, is deposited, which is likewise removed following pattern delineation of the metallic layer.

Abstract: A method of fabricating ultra small vias in insulating layers on a semiconductor substrate for an integrated circuit by a first exposure of a photoresist to line pattern with the semiconductor substrate in a first position and the exposure dosage being insufficient to develop the photoresist followed by a second overlapping exposure of the line pattern with the semiconductor substrate being in a position 90° from the first position and again being insufficient in exposure dosage to develop the photoresist, the overlapped line exposures creating via exposures of sufficient dosage to develop the photoresist, thereby creating a smaller via opening than with a single exposure.