Abstract: In a semiconductor device, a TiN plug is formed to filled up a contact hole which is formed to penetrate through an insulator film on a conductive silicon layer in a surface region of a silicon substrate. A first titanium silicide film is formed on a bottom surface of the TiN plug, so that the TiN plug is electrically connected to the conductive silicon layer through the first titanium silicide film. A second titanium silicide film is formed on a top surface of the TiN plug, and a polysilicon electrode is formed on the second titanium silicide film, so that the TiN plug is electrically connected to the polysilicon electrode through the second titanium silicide film. Thus, the contact resistance between the TiN plug and the polysilicon electrode is reduced.

Abstract: A method is provided to increase the contact area of a contact window. In this method, the contact area is mainly increased by a concavity which is formed by first forming a thin oxide layer in the contact region using local oxidation, then further by removing the thin oxide layer. Additionally, in order to reduce the contact resistance, a metal oxide layer can be selectively formed at the contact interface.

Abstract: A method of fabricating a semiconductor device includes the steps of providing a semiconductor chip (10) with a memory area (22) and a logic area (26). The memory area (22) and the logic area (26) each have gate structures (50) formed therein. The step of sequentially forming silicided junctions (44) in the logic area (26) and implanted junctions in the memory area (26) is also included.

Abstract: The present invention is a method of fabricating void-free and volcano-free tungsten plugs. A silicon film was formed over contact hole surfaces for restricting the reflow of a dielectric layer. A titanium film is formed over the silicon layer. By performing a thermal process to the silicon layer and the titanium layer in a nitride-containing environment, the etching damage to the substrate can be recovered and a silicon silicide and a titanium nitride can be formed. The contact resistance of plugs can be significantly reduced, when compared with known technology. The undesired formation of voids and volcano can be eliminated. The method can be employed to fabricate defect-free advanced ULSI devices.

Abstract: A fabrication method of a semiconductor device is provided, which makes it possible to form a thin and elongated refractory-metal silicide layer while preventing the overgrowth phenomenon. This method is comprised of the steps (a) to (c). In the step (a), a first refractory metal film is formed on a silicon region. In the step (b), a second refractory metal film is formed on the first refractory metal film. The second refractory metal film contains a same refractory metal as the first refractory metal film and nitrogen. A stress of the second refractory metal film is controlled to be a specific value or lower. In the step (c), the first refractory metal film and the second refractory metal film are heat-treated in an atmosphere excluding nitrogen, thereby forming a refractory-metal silicide layer at an interface between the silicon region and the first refractory metal film due to silicidation reaction of the first refractory metal film with the silicon region.

Abstract: A silicide layer is formed on a conductive layer in a microelectronic device by forming a first silicide layer on the conductive layer. A second silicide layer is then formed on the first silicide layer, the second silicide layer having a concentration of silicon that is less than the first silicide layer. Preferably, the first silicide layer and the second silicide layer are formed of tungsten silicide. The first silicide layer and the second silicide layer are preferably annealed to form a merged silicide layer. According to another aspect, a contact structure for contacting a microelectronic layer in a microelectronic device is formed by forming an insulation layer on the microelectronic layer, the insulation layer having a contact hole therethrough that exposes a portion of the microelectronic layer. A conductive layer is then formed on the insulation layer, the conductive layer extending through the contact hole to contact the exposed portion of the microelectronic layer.

Abstract: A microelectronic device includes a first region having a first conductivity type. A second region having a second conductivity type contacts the first region at a junction therebetween. A metal silicide region contacts the second region at a contact surface apart from the junction. Impurities of the second conductivity type in the second region are concentrated between the contact surface and the junction, for example, in one or more subregions disposed between the contact surface and the junction. The subregions may include a first subregion adjacent the junction formed by an ion implantation at a first energy level, and a second subregion disposed between the first subregion and the contact surface formed by a second ion implantation at a different energy level. Related fabrication methods are also provided.

Abstract: A method is disclosed for providing a self-aligned silicide strap for connecting thin polysilicon layers (poly-1 and poly-2, etc.) separated by non-conducting gaps. A butting contact opening to the layers is formed in an overlying insulating layer. The contact exposes the poly-1 and poly-2 layers. A thin polysilicon layer (poly-3) is then deposited over the insulating layer and into the contact. This is followed by deposition of a refractory metal layer. The poly-3 layer should be thin enough that, alone, it cannot supply enough silicon to support full silicidation of the refractory metal layer. The structure is next sintered so that a silicide strap is formed in the contact opening and across exposed portions of the poly-1 and poly-2 layers. The ratio of silicon to titanium in regions over the insulating layer is lower than that in the strap, such that these more metallic regions may be selectively removed.

Abstract: A layered trace configuration comprising a conductive trace capped with a silicide material which allows for removal of oxide polymer residues forming in vias used for interlayer contacts in a multilayer semiconductor device and eliminates or greatly reduces the formation of metal polymer residues in the vias. The formation of an interlayer contact according to one embodiment of the present invention comprises providing a trace formed on a semiconductor substrate and a silicide layer capping the conductive layer. An interlayer dielectric is deposited over the silicide capped trace and the substrate. A via is etched through the interlayer dielectric, wherein the etch is selectively stopped on the silicide layer. Any residue forming in the via is removed and a conductive material is deposited in the via to form the interlayer contact.

Abstract: A doped oxide and an undoped oxide are formed on a substrate. Then, the substrate is annealed to re-flow the doped oxide layer. The doped oxide is then etched back. Next, a contact hole is created by etching. An amorphous silicon layer is formed on the surface of the doped oxide layer and along the surface of the contact hole. Next, high temperature is used to recover the etching damage and simultaneously transform or convert the amorphous silicon into a polysilicon layer. A titanium layer and a titanium nitride are respectively formed onto the polysilicon layer. Next, rapid thermal process (RTP) is introduced to form a titanium silicide beneath the titanium nitride layer. A tungsten layer is formed on the titanium nitride layer and refilled into the contact hole. The tungsten layer is then etched back to form a tungsten plug with void-free in the contact hole. A conductive layer is formed on the titanium nitride layer.

Abstract: A method of a method of fabricating a contact. A substrate having a plurality of gates and a plurality of lightly doped source/drain regions is provided. A dielectric layer is formed and patterned to form a self-align contact window to expose a first lightly doped source/drain region of said lightly doped source/drain regions, and to form a first spacer on a side wall of a first gate of said gates simultaneously. An ion implantation is performed by using the first spacer as a mask, so that a first heavily doped source/drain region is formed in the first lightly doped source/drain region. A doped poly-silicon layer is formed over the substrate, and a metal silicide layer is formed on the doped poly-silicon layer. The doped poly-silicon and the metal silicide layer are patterned to form a self-align contact.

Abstract: A method of fabricating an interpoly dielectric layer of an embedded DRAM wherein a substrate having a logic FET is provided and the logic FET has a source/drain region where a titanium suicide layer is formed thereon. An oxide layer is formed on the substrate and a silicion nitride layer is formed by PECVD on the oxide layer. The thermal stability can be improved because the formation of the compressive silicon nitride layer and the oxide layer prevents junction leakage, which is produced from the embedded DRAM.

Abstract: The present invention provides improved device speed by using two silicides with two different compositions: one silicide is overlaid on a polysilicon gate layer, to form a "polycide" layer with improved sheet resistance, and the other is clad on at least some "active" areas of the monocrystalline silicon, to form a "salicided" active area with improved sheet and contact resistance. Preferably one silicide is a reaction product and the other is deposited.

Abstract: A method for producing a titanium silicide. Titanium is deposited in a chamber in a reactive sputtering manner while flowing a mixture of argon gas and SiH.sub.4 or Si.sub.2 H.sub.6 into the chamber.

Abstract: A method of fabricating a transistor, comprising the following steps. A silicon semiconductor substrate having a pad oxide portion within an active area is provided. A polysilicon layer is deposited over the silicon semiconductor substrate and over the pad oxide portion. A pad oxide layer is deposited over the polysilicon layer. Shallow isolation trench regions are formed on either side of the active area. The pad oxide layer is removed. The polysilicon layer is etched and removed over the pad oxide portion leaving polysilicon portions between the pad oxide portion and the shallow isolation trench regions. The pad oxide portion is replaced with a gate oxide portion. A gate conductor, having exposed side walls, is formed over the gate oxide portion and between the polysilicon portions. Sidewall spacers are formed on the exposed side walls of the gate conductor with the sidewall spacers contacting the polysilicon portions.

Abstract: A contact is selectively formed in a contact hole in an insulating layer deposited on a silicon substrate. The contact hole exposes a portion of the substrate. The contact is formed by selectively forming a first layer of titanium silicide in the contact hole on the exposed portion of the substrate. A layer of titanium nitride is then selectively formed on the first layer of titanium silicide. A second layer of titanium silicide is thereafter selectively formed on the layer of titanium nitride to form the contact.

Abstract: A method for forming metal interconnection of semiconductor device is disclosed. In the present invention, an aluminum layer in the 10 to 100 .ANG. range is deposited on the bottom of the contact before or after the deposition of a titanium layer for barrier metal, which forms TiAl.sub.3 by the reaction of titanium and aluminum. According to the invention, stable contact resistance and low leakage current can be obtained in the application of ultra shallow junction.

Abstract: A method for forming a refractory metal silicide layer on a silicon surface in which a first layer of a refractory metal is formed on the silicon surface. A second layer extends over the first layer and is made of a nitrogen containing refractory metal. The silicon surface and the first and second layers are subjected to a heat treatment in an argon gas atmosphere to form a refractory metal silicide layer on an interface between the silicon surface and the first layer.

Abstract: The phosphorus concentration of an upper electrode and the phosphorus concentration of a lower electrode can be made equally high without loss of adhesion between the polysilicon and a metallic layer. It includes a step of forming a stacked layer structure consisting of: a lower electrode layer provided on an underlay, a dielectric layer provided on this lower electrode layer, and an upper electrode layer consisting of an impurity-doped layer and a metallic layer successively provided on this dielectric layer, and a step of doping the metallic layer with the same impurity as the impurity in the impurity-doped layer prior to heat treatment of the stacked layer structure.

Abstract: A local interconnect (LI) structure is formed by forming a silicide layer in selected regions of a semiconductor structure then depositing an essentially uniform layer of transition or refractory metal overlying the semiconductor structure. The metal local interconnect is deposited without forming in intermediate insulating layer between the silicide and metal layers to define contact openings or vias. In some embodiments, titanium a suitable metal for formation of the local interconnect. Suitable selected regions for silicide layer formation include, for example, silicided source/drain (S/D) regions and silicided gate contact regions. The silicided regions form uniform structures for electrical coupling to underlying doped regions that are parts of one or more semiconductor devices. In integrated circuits in which an etchstop layer is desired for the patterning of the metal film, a first optional insulating layer is deposited prior to deposition of the metal film.

Abstract: A method of forming a crystalline phase material includes providing a stress inducing material on a substrate and, after providing the stress inducing material on the substrate, depositing a crystalline phase material over the substrate in a substantially continuous manner and changing deposition temperature at least once during the depositing, and forming the second crystalline phase of the crystalline phase material. In accordance another aspect, a method is performed by providing a stress inducing material on a substrate and, after providing the stress inducing material on the substrate, forming a crystalline phase material over the substrate in at least two discrete crystalline phase material depositions, a later of the depositions being conducted at a different temperature from an earlier of the depositions and forming the second crystalline phase of the crystalline phase material.

Abstract: A method for manufacturing a bit line. A substrate having a dielectric layer on the substrate and a contact hole penetrating through the dielectric layer and exposing portions of the substrate is provided. A patterned conductive layer is formed on the dielectric layer and fills the contact hole. The surface of the patterned conductive layer is converted into an oxide layer. The oxide layer is removed. A silicide layer is formed on the patterned conductive layer.

Abstract: A substantially inert capping layer of tungsten nitride is deposited on cobalt layers prior to silicidation, thereby avoiding any substantial interaction with cobalt. The tungsten nitride capping layer also functions as a diffusion barrier preventing oxygen from reaching the silicidation area. The resulting cobalt silicides layer exhibit lower resistivity than those formed employing a titanium capping layer. Embodiments include rapid thermal annealing to initially form a layer of cobalt monosilicide consuming a portion of the cobalt layer, removing the tungsten nitride and unreacted cobalt layer, and rapid thermal annealing again to convert the cobalt monosilicide layer to a low resistivity layer of cobalt disilicide.

Abstract: The method for fabricating a semiconductor device includes steps of forming a layered structure by sequentially depositing a silicon film containing an impurity, a metal silicide film, and an amorphous silicon film containing an impurity, forming an electrode or an interconnect in a three-layer structure by selectively etching the amorphous silicon film, the metal silicide film and the silicon film in this order, and diffusing the impurity in the amorphous silicon film into the metal silicide film by a thermal process. Thus, the impurity is supplied from the amorphous silicon film to the metal silicide film so that the ion-implantation as required in the prior art is not necessary.

Abstract: The present invention provides a method of forming a contact structure comprised of: a silicon substrate, a titanium silicide layer, a barrier layer (i.e., TiN or TiNO), and a metal layer (e.g., Al or W). There are three embodiments of the invention for forming the titanium silicide layer and two embodiments for forming the barrier layer (TiN or TiNO). The first embodiment for forming a TiSix layer comprises three selective deposition steps with varying TiCl4: SiH4 ratios. After the TiSix contact layer is formed a barrier layer and a metal plug layer are formed thereover to form a contact structure. The method comprises forming a barrier layer 140 over the silicide contact layer 126; and forming a metal plug 160 over the TiN barrier layer 140. The metal plug 160 is composed of Al or W.

Abstract: A C49-structured titanium silicide film contains at least a refractory metal having a higher melting point than titanium in the form of a substitutional solid solution, wherein a concentration of the refractory metal to a total amount of titanium and the refractory metal is in the range of above 1 at % to not more than 20 at %. On silicon, there is formed a titanium film which contains at least a refractory metal having a higher melting point than titanium, wherein a concentration of the refractory metal to a total amount of titanium and the refractory metal is in the range of above 1 at % to not more than 20 at %. The titanium film is then subjected to a heat treatment in an inert gas atmosphere for causing a silicidation reaction, thereby to form a C49-structured titanium silicide film which contains the above at least a refractory metal in the form of a substitutional solid solution.

Abstract: A three elemental compound for diffusion barrier layer having a superior diffusion barrier characteristics manufactured by forming the compound between the silicon diffused into the diffusion barrier layer and the two elemental compound for diffusion barrier layer before the metal wire layer penetrates into the diffusion barrier layer to reach the underlying silicon layer, using the different characteristics of the diffusion rate as above, is disclosed. A method of forming three elemental compound for diffusion barrier layer according to the present invention comprises a silicon substrate. A silicide layer is deposited on the silicon substrate. A refractory metal nitride layer is then deposited on the silicide layer. A metal wire layer is deposited on the refractory metal nitride layer.

Abstract: A new process for creating a transistor in an integrated circuit provides for two suicide formations, each independent of the other, from two metal depositions and formations steps. The process produces a sufficiently low resistance silicide layer over the source/drain region surfaces of the transistor while also creating a lower resistance silicide over the gate interconnects. In an example embodiment of the invention a near-planar isolation process is used applied such that the gate interconnect surfaces are co-planar. A first silicide layer is formed over the source/drain regions. A dielectric gap-fill material is applied. A planarization method such as chemical mechanical polishing is used to remove the gap fill material down to the top surface of the gate interconnect. A relatively thick suicide is then formed over the top surface of the gate interconnect.

Abstract: Stable suicides are formed utilizing excimer laser crystallization in place of a conventional second high temperature rapid thermal processing annealing step. Specifically, thermally unstable silicide having a metal-rich surface layer is conventionally formed utilizing deposition of refractory metal followed by low temperature annealing. After removal of unreacted refractory metal, an amorphous silicon film is deposited on top of the unstable silicide and exposed to radiation from an excimer laser, such that the amorphous silicon melts, reacts with refractory metal from the underlying unstable silicide, and reforms as thermally stable silicide evidencing low electrical resistance.

Abstract: A recess having a height-to-width aspect ratio from about 6:1 to about 10:1 in a semiconductor structure is taught with a method of forming the same. In a first embodiment, a refractory metal layer is formed in the recess, which can be a trench, a contact hole, or a combination thereof. A refractory metal nitride layer is then formed on the refractory metal layer. A heat treatment, preferably RTP, is used to form a metal silicide contact at the bottom of the contact hole upon semiconductor material. In a first alternative method, an ammonia high-temperature treatment is conducted to remove undesirable impurities within the refractory metal nitride layer lining the contact hole and to replace the impurities with more nitrogen. In a second alternative method, a second refractory metal nitride layer is formed by PVD upon the first refractory metal nitride layer. In either alternative, a metallization layer is deposited with the recess.

Abstract: In a process for manufacturing a semiconductor device, an N-well, a field oxide film, a gate oxide film and a polysilicon gate electrode are formed on a P-type silicon substrate. Arsenic is ion-implanted into the substrate using the polysilicon gate electrode as a mask, to form N-type diffused source/drain regions. Boron fluoride is ion-implanted into the N-well using the polysilicon gate electrode as a mask, to form P-type diffused source/drain regions. A titanium film is deposited on the whole surface, and a first heat treatment is carried out at a first temperature to form titanium silicide. Metal titanium remaining on the titanium silicide is removed so as to selectively form titanium silicide on the polysilicon gate electrode, the N-type diffused source/drain regions and the P-type diffused source/drain regions. A second heat treatment is carried out on the refractory metal silicide at a second temperature higher than the first temperature.

Abstract: A first TiSix layer is deposited on a polysilicon layer, then a silicon substrate is annealed in a vacuum atmosphere to crystallize the TiSix layer, and a second TiSix layer is provided on the first crystallized TiSix layer.

Abstract: The method of the present invention includes the steps as followings. At first, a gate oxide layer is formed on the substrate. An undoped polysilicon layer is formed over the gate oxide layer. Then, a first dielectric layer is formed over the undoped polysilicon layer. A second silicon layer is formed over the first dielectric layer. Next, the second silicon layer is patterned to define a gate region. An etching process is performed to the second silicon layer to narrow the gate region. Portions of the first dielectric layer are etched by using the residual second silicon layer as a mask. The undoped polysilicon layer is etched by using the residual second silicon layer and the residual first dielectric layer as mask. Then, a PSG is layer deposited over the residual first dielectric layer and the substrate. Subsequently, the PSG layer is etched back to form side-wall spacers to serve as ion diffusion source. A noble or refractory metal layer is deposited on all area of the substrate.

Abstract: The present invention provides a way how to use a technique for forming the contact of a diffusion layer in a self-alignment manner in combination with a salicide technique. The most important finding in the way is that when an insulating film is deposited over the entire surface, the insulating film deposited on a shared diffusion layer which is present in a depressed portion between two electrodes is thinner in a natural course of events than that deposited on open-surfaces of the two electrodes. When such an insulating film different in thickness is etched, the relatively thin insulating film formed on the shared diffusion layer is substantially completely removed, whereas the relatively thick insulating film formed on the two electrodes is not completely removed and remains as a thin film.

Abstract: A contact process interconnects poly-crystal silicon layer, and more particularly, this process dramatically decreases the voltage drop within a poly-crystal silicon layer. The advantages of the process include not only improvement in the interface quality of Poly-Si/SiO2 to decrease the junction damage but also do not increase its process complexity and its mask number during the fabrication of poly-crystal silicon thin-film SRAM to meet high integration requirement in VLSI.

Abstract: A method for substantially reducing conductive line cracking on an integrated circuit, comprising the steps of: obtaining a semiconductor structure with a first surface and with an insulating region adjacent to and rising above the first surface; forming a layer of a first conductive material above the first surface of the semiconductor structure and above the adjacent first insulating region; forming an opening through the layer of first conductive material down to the first insulating region; forming an insulation layer over the layer of first conductive material; forming a layer of a second conductive material above the insulation layer; polishing the layer of second conductive material; and forming a third conductive layer above the layer of second conductive material.

Abstract: An embodiment of the present invention teaches a method used in a semiconductor fabrication process to form a memory cell in a semiconductor device comprising the steps of: subjecting a layered structure comprising a silicon gate insulating layer, a conductively doped polysilicon gate layer and a refractory metal silicide gate film to a thermal processing step; forming a sheet resistance capping layer directly on the refractory metal silicide film during at least a period of time of the thermal processing step, the sheet resistance capping layer forming a substantially uniform surface on the refractory metal silicide film; patterning and etching the layered structure to form the transistor gate; forming source and drain regions aligned to apposing sides of the transistor gate and formed into an underlying silicon substrate; and forming a storage capacitor (such as a stacked capacitor or a container cell) connecting to one of the source and drain regions.

Abstract: A method for fabricating a semiconductor device, such as a MOS (metal-oxide semiconductor) transistor, with self-aligned silicide is provided. This method can prevent junction leakage between the silicide and the substrate so as to allow the resultant semiconductor device to have reliable performance. The method includes the steps of preparing a semiconductor substrate; forming at least one transistor element over the substrate, the transistor element including a pair of source/drain regions, a gate, a dielectric layer over the gate, and a spacer on the sidewall of the gate; and performing an ion-bombardment process so as to transport one part of the dielectric layer that is adjacent to the top of the spacer to beside the bottom of the spacer.

Abstract: A semiconductor device has a semiconductor layer such as of Si, an insulator film formed on the semiconductor layer and having a contact hole formed therein, a first contacting layer such as of Ti formed in the contact hole so as to be in contact with the semiconductor layer, a second contacting layer such as of TiN formed on the first contact material, and a contacting material such as W formed on the second contacting layer so as to substantially fill the contact hole. The first contacting layer in as formed state has a thickness of 4 nm or greater, while the second contacting layer as formed has a thickness of 1 nm or greater. The optimum thicknesses of the contacting layers are determined based on the pattern rule, e.g., 3.5 m rule, and the kinds of the materials such as Ti, TiN and W. Electrically stable ohmic contact can be obtained at a high yield.

Abstract: Methods of establishing electrical communication with substrate node locations, methods of forming DRAM circuitry, and semiconductor assemblies are described. In one implementation, a contact opening is formed over a substrate node location with which electrical communication is desired. The contact opening has a base over which a refractory metal layer is formed. A refractory metal silicide layer is formed over the refractory metal layer, and the substrate is exposed to conditions effective to convert the refractory metal layer to a refractory metal silicide. In one embodiment, the refractory metal layer and the refractory metal silicide layer are chemical vapor deposited. In another embodiment, the refractory metal silicide layer comprises a silicide of the refractory metal layer. In a preferred implementation, the refractory metal layer comprises titanium and the refractory metal silicide layer comprises titanium silicide.

Abstract: A semiconductor device with a contact structure includes a silicon substrate, a diffusion region formed in a surface of the silicon substrate, a silicide film of a high melting point metal deposited on the diffusion region, an insulating film formed on the silicon substrate, a contact hole formed in the insulating film such that the silicide film is exposed at a bottom of the contact hole, an anti-diffusion film formed on at least the exposed surface of the silicide film at the bottom of the contact film, a plug formed in the contact hole by selective Al-CVD, and a metal wiring formed on the insulating film. The metal wiring is electrically connected to the diffusion region by the plug, the anti-diffusion film and the silicide film. The anti-diffusion film is formed by nitriding the surface of the silicide film such that only the grain boundaries of the grains of the silicide film are nitrided.

Abstract: A method of forming buried contacts in MOSFET and CMOS devices which substantially reduces the depth of the buried contact trench. A split polysilicon process is used to form the gate electrode and contact electrode. The first polysilicon layer is very thin layer of undoped polysilicon, having a thickness of less than 100 Angstroms. The second polysilicon layer is a layer of doped polysilicon having a thickness of between about 950 and 1150 Angstroms. The buried contact can be formed either using ion implantation or diffusion of impurities from the layer of doped second polysilicon into the contact region. When the metal layers are etched to form the gate electrode and contact electrode the resulting buried contact trench is less than 500 Angstroms deep.

Abstract: A process is described wherein logic and memory share the same chip. Contacts to the gates in the memory areas are made using a silicide process, while contacts to the logic circuits are made using the SALICIDE process, thus ensuring high performance. The two processes have been integrated within a single chip by first covering the gate pedestals in both areas with a layer of cap oxide. The wafer is then covered with a layer of BARC (Bottom Anti-Reflection Coating) which is etched back so as to expose only the cap oxide that covers the top surfaces of the gate pedestals. This allows the cap oxide to be removed from only these top surfaces. In an alternative embodiment, photoresist may be used in place of BARC. The remaining cap oxide is then selectively removed in only the logic area and the standard SALICIDE process is applied, resulting in SALICIDE contacts to source, gate, and drain on the logic side and silicide contacts to the gates on the memory side.

Abstract: A method for forming a contact structure (10) which enables the use of ultra-shallow source/drain junctions begins by forming source and drain regions (14) and gate electrode (16). The source and drain regions (14) and the gate electrode (16) are silicided to form silicide regions (20). A conductive tungsten nitride etch stop layer (22) is formed overlying the silicide regions (20). Contact plug regions (28) are then formed to contact to the etch stop layer (22) and silicided regions (20). At this point, all of the silicide regions (20) are electrically short circuited. To remove this electric short circuit, an isotropic etch process comprising hydrogen peroxide, ammonium hydroxide, and water is used to remove portions of the tungsten nitride regions which are between the individual contact portions (28) in a self-aligned manner.

Abstract: A method of forming salicide, of which the characteristics is the formation of a silicon nitride layer before the source/drain being implanted with dopant. The silicon nitride layer avoid the oxygen within the oxide layer to implant into the source/drain. Thus, a better salicide is obtained. In addition, the formation of the parasitic spacers made of silicon nitride at the side wall bottom of the gate spacer increases the distance between the salicide and the junction. Consequently, the leakage current is prevented. While the silicon nitride layer is removed, the polysilicon of gate and the silicon of the source/drain are amorphized. This is advantageous to the formation of salicide without the step of ion implantation.

Abstract: The method of the present invention includes forming a MOS on a semiconductor substrate. Subsequently, a silicon-rich metal silicide layer is deposited on the MOS and substrate by using chemical vapor deposition to act as a silicon material source. Then, a thermal process is carried out to separate a portion of the silicon out of the metal silicide layer, thereby forming a silicon layer on top of the gate of the MOS, source/drain. The nest step is to remove the metal suicide layer. A self-aligned metal silicide layer is formed on the silicon layer.

Abstract: A method is provided for improving silicide formation, and the electrical ntact provided thereby, on non-planar silicon structures. In this method, a semiconductor device structure is initially formed having non-planar surface regions. A metal layer is deposited on the non-planar surfaces. The metal deposition process step is followed by an off-axis implantation of non-dopant ions, causing a mixing of the metal and silicon atoms at the metal and non-planar silicon structure interface. The off-axes implantation also serves to disrupt the native silicon dioxide layer between the silicon and metal layers regions. Thermal processing is then used to form silicide on the non-planar surfaces of the semiconductor silicon structure.

Abstract: Low resistivity metal silicide layers are formed on a gate electrode and source/drain regions at an optimum thickness for reducing parasitic series resistances with an attendant consumption of silicon from the gate electrode and source/drain regions. Consumed silicon from the gate electrode and source/drain regions is then replaced employing metal induced crystallization, thereby avoiding a high leakage current. Embodiments include depositing a layer of amorphous silicon on the metal silicide layers and heating at a temperature of about 400.degree. C. to about 600.degree. C. initiating metal induced crystallization, thereby causing the metal silicide layers grow upwardly as silicon in the underlying gate electrode and source/drain regions is replaced.

Abstract: The invention relates to integrated circuits and to via hole structures which include a tungsten silicide barrier layer and to methods of forming such via hole structures. In an exemplary embodiment, a metal layer is formed on a sidewall and a bottom surface of the via hole, a WSi.sub.x barrier layer is formed on the first metal layer by chemical vapor deposition and the via hole is subsequently filled with a metal. The tungsten silicide barrier layer effectively suppresses device degradation resulting from the release of gaseous species from the sidewall of the via hole during plug formation. Semiconductor devices can thus be fabricated which are immune or less susceptible to metal open failures due to incomplete via filling.

Abstract: The present invention discloses a method of doping and preventing silicide formation in selective areas of a polysilicon gate in MOS, PMOS, NMOS or CMOS manufacturing technologies. The process includes the steps of: depositing a non-conformal dopant containing layer on the top surface of the body and the top surface of the polysilicon gate; removing a portion of the non-conformal dopant containing layer to expose the top surface of the polysilicon gate; and heating to diffuse dopant from the dopant containing layer. Silicidation is then provided by depositing a metal layer and annealing the metal layer. As a first alternative method, the heating and removing step may be reversed. As a second alternative method, after removal of the non-conformal layer, a metal layer can be deposited followed by a combination anneal of the metal layer and non-conformal dopant containing layer.