Abstract: A new method of forming selective salicide structures is described whereby robust salicide structures are formed on exposed logic FET's, while blocking salicide formation on memory FET's. Thus, yielding logic FET's with robust salicide structures which exhibit low sheet rho lines and contacts, while blocking salicide formation on the sensitive memory FET's which operate at low voltage and have low leakage, shallow junctions. A conformal layer of thick silicon nitride in conjunction with a salicide blockout mask forms robust selective salicide structures. These structures exhibit low leakage and lack leakage problems caused by bridging, silicide ribbons or stringers.

Abstract: A method for forming a metal silicide layer. There is first provided a substrate. There is then formed over the substrate a silicon layer, where the silicon layer has other than an amorphous silicon surface. There is then annealed thermally the silicon layer at a temperature greater than a silicidation temperature for forming a metal silicide layer upon the silicon layer to thus form from the silicon layer a thermally annealed silicon layer. Finally, there is then deposited upon the thermally annealed silicon layer a metal silicide forming metal while employing a metal deposition method such that upon contact with the thermally annealed silicon layer the metal silicide forming metal reacts in-situ to form a metal silicide layer upon a partially consumed thermally annealed silicon layer formed from the thermally annealed silicon layer.

Abstract: First, there is formed a silicon film doped with impurities on a semiconductor substrate. Next, a refractory metal film is formed on the silicon film. Then, the silicon film and the refractory metal film are reacted by heat treatment to form a refractory metal silicide film.

Abstract: A first tungsten silicide layer relatively rich in silicon is formed on an object by using a process gas having a phosphorus atom-containing gas added thereto, and a second tungsten silicide layer relatively rich in tungsten is formed on the first tungsten silicide layer, so that a tungsten silicide film is formed. The addition amount of the phosphorus atom-containing gas to the process gas is 0.02 to 0.2% by volume “in terms of a phosphine gas”.

Abstract: The invention includes methods of forming buried bit line memory circuitry and semiconductor processing methods of forming conductive lines. In but one implementation, a semiconductor processing method of forming a conductive line includes forming a silicon comprising region over a substrate. A TiNx comprising layer is deposited over the silicon comprising region, where “x” is greater than 0 and less than 1. The TiNx comprising layer is annealed in a nitrogen and hydrogen plasma atmosphere effective to transform at least an outermost portion of the TiNx layer over the silicon comprising region to TiN. After the annealing, an elemental tungsten comprising layer if formed on the TiN and at least the elemental tungsten comprising layer, the TiN, and any remaining TiNx layer is patterned into conductive line. In one implementation, a method such as the above is utilized in the fabrication of buried bit line memory circuitry.

Abstract: Process for forming a boron-doped silicon gate layer underlying a cobalt silicide layer that reduces the risk of grooving and agglomeration of cobalt silicide layer, as well as boron penetration into a gate oxide layer. The process includes providing a PMOS transistor structure that includes an N-well on a P-type silicon substrate, a gate oxide layer and a silicon gate layer. Next, a cobalt layer is deposited on the PMOS transistor structure, which is then subjected to a first thermal treatment to form a bilayer CoSi/silicon stack structure. After removing unreacted cobalt, boron dopant (BF2+ or B+) and nitrogen ions (N2+) are implanted into the bilayer CoSi/silicon stack structure. The bilayer CoSi/silicon stack structure, implanted boron and implanted nitrogen are then subjected to second thermal treatment to form a CoSi2 layer on the silicon gate layer and to thermally activate the implanted boron.

Abstract: A semiconductor device is formed by forming a groove portion whose side surface is formed of a first insulating film and whose bottom surface is formed of a silicon film on the main surface of a semiconductor substrate, forming a metal film on the silicon film of a bottom portion of the groove portion, reacting the silicon film with the metal film by a heat treatment to selectively form a silicide film on the bottom portion of the groove portion, removing the metal film other than a portion thereof which has been converted to metal silicide after the metal silicide layer is formed, and forming a second insulating film on the metal silicide film to form one of a wiring and an electrode which is covered with the first and second insulating films.

Abstract: A two-step silicidation process for fabricating a semiconductor device is disclosed. The method includes the following steps. Firstly, two trench isolation regions are formed in a semiconductor substrate. A gate oxide layer and a polysilicon layer and a barrier layer are formed. Patterning is carried out to etch portions of the barrier layer. The areas between the trench isolation regions and the gate region are respectively used as a source area and a drain area. First ions are implanted into the substrate. A dielectric layer is blanket formed and the dielectric layer is etched back to form dielectric spacer. The second ions are implanted into the substrate. The first silicide regions respectively are formed in the source area and the drain area. A poly-metal dielectric (PMD) layer is formed and is etched back. Finally, the second silicide region is formed on and in the polysilicon layer.

Abstract: In a method of forming a salicide layer in an embedded dynamic random access memory, a thin oxide layer, a silicon nitride layer and a thick oxide layer are sequentially formed over a substrate after performing an annealing process to a source/drain region. The insulating layer on a gate and a source/drain region in a logic region and a gate in a memory region. Salicide layers are formed on the three regions mentioned above. Formation of the salicide layers can lower resistance of the three regions, increase speed and can avoid forming a salicide layer on the source/drain region in the memory region. Thus, current leakage can be avoided. In addition, the step of forming a salicide layer is conducted after the annealing process of the source/drain region, so problems of thermal stability and inter-diffusion of impurities in the polysilicon layer can also be solved.

Abstract: A nitridization process to form a barrier layer on a substrate is described. The nitridization process includes depositing a layer of metal or metal silicide on a surface of the substrate, placing the substrate into a high density, low pressure plasma reactor, introducing into the high density low pressure plasma reactor a gas including nitrogen, and striking a plasma in the high density, low pressure plasma reactor under conditions that promote nitridization of at least a portion of the layer of metal or metal silicide to produce a composition of metal nitride or metal silicon nitride, respectively.

Abstract: A method for fabricating a semiconductor device improves step coverage and resistivity. The method includes the steps of forming a doped silicon layer on a substrate, forming a silicide layer containing more metal atoms than silicon atoms on the doped silicon layer, and heat treating in nitrogen to form a second silicide layer having a tetragonal phase crystal structure and a silicon nitride film on the top surface of the second silicide layer.

Abstract: After a cobalt film 12 and a titanium nitride film 13 as a barrier film against oxygen are formed over the surfaces of impurity diffusion layers 9, 10 on a silicon substrate 1, a first heat treatment is performed at a temperature below 400° C., forming a Co2Si film 31. Following this, the titanium nitride film and the unreacted cobalt film are removed, using a mixed solution of sulfuric acid and hydrogen peroxide and then another heat treatment is performed at a temperature in a range of 700˜900° C. and thereby forms a CoSi2 film. According to the present invention, the generation of spikes of cobalt silicide which may pierce the diffusion layers is well suppressed and, thus, the leakage current is well-controlled so that good transistor characteristics as well as high reliability are attained.

Abstract: A method of film processing comprises forming an integrated titanium/titanium nitride (Ti/TiN) film structure having an intermediate layer. The intermediate layer comprises species containing Si, and preferably containing Si and Ti, such as titanium silicide (TiSix), or TiSixOy, among others. The intermediate layer protects the underlying Ti film against chemical attack during subsequent TiN deposition using a titanium tetrachloride (TiCl4)-based chemistry. The method allows reliable Ti/TiN film integration to be achieved with excellent TiN step coverage. For example, the film structure can be used as an effective barrier layer in integrated circuit fabrication.

Abstract: A method for forming the gate electrode in an integrated circuit, in which a cap silicon nitride layer is deposited in a two step process to improve the condition of silicon nitride residue remaining on the surface of tungsten silicide. First, a layer of polysilicon and a layer of tungsten silicide are sequentially formed on the semiconductor substrate, subsequently, a thin film of silicon nitride is formed at a first temperature and a second silicon nitride is formed at a second temperature, then the pattern of the contact window of gate is defined and the first etching is performed to remove the second and the second silicon nitride, finally, the second etching is performed to remove the layers of polysilicon and tungsten silicide to form a gate electrode.

Abstract: Cu interconnection patterns with improved electromigration resistance are formed by depositing a barrier metal layer, such as W or WN, to line an opening in a dielectric layer. The exposed surface of the deposited barrier metal layer is treated with silane or dichlorosaline to form a thin silicon layer thereon. Cu is then deposited to fill the opening and reacted with the thin silicon layer to form a thin layer of Cu silicide at the interface between Cu and the barrier metal layer, thereby reducing the interface defect density and improving electromigration resistance.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

Abstract: The adhesion of a diffusion barrier or capping layer to Cu and/or Cu alloy interconnect members is significantly enhanced by treating the exposed surface of the Cu and/or Cu alloy interconnect members with a silane or dichlorosilane plasma to form a layer of copper silicide thereon prior to depositing the capping layer. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric interlayer, chemical mechanical polishing, treating the exposed surface of the Cu or Cu alloy interconnect member in a silane or dichlorosilane plasma to form the copper silicide layer and depositing a capping layer of silicon nitride thereon.

Abstract: A method for fabricating a high speed and high density nonvolatile memory cell is disclosed. First, a semiconductor substrate with defined field oxide and active region is prepared. A stacked silicon oxide/silicon nitride layer is deposited and then the tunnel oxide region is defined. A thick thermal oxide is grown on the non-tunnel region. After removing the masking silicon nitride layer, the source and drain are formed by an ion implantation and a thermal annealing. The pad oxide film is etched back, and a metal silicide film is formed and then stripped. A topography of the doped substrate region is then made rugged. Thereafter, a thin oxide is grown on the rugged doped substrate region to form a rugged tunnel oxide. Finally, the floating gate, the interpoly dielectric, and the control gate are sequentially formed, and the memory cell is finished.

Abstract: In order to prevent a thick metal nitride film formed in a contact hole or a through-hole and on an insulating film to bury the hole from being cracked of peeled off, a method for easily removing unnecessary metal film on the insulating film while leaving a metal silicide film formed in the hole is provided. The method comprises the steps of depositing a titanium film in the hole formed in the insulating film and on the insulating film by CVD, forming the metal silicide film by a reaction between the titanium film on a bottom of the hole and a semiconductor substrate and, then, selectively removing unnecessary metal film other than the metal silicide film by using an etching gas containing halogen.

Abstract: A method for forming self-aligned raised source and drain regions on a semiconductor wafer includes the steps of defining a substrate, growing a first layer of dielectric material over the substrate, depositing a layer of polysilicon over the first layer of dielectric material, patterning and forming at least one gate, depositing a second layer of dielectric material over the gate and the first dielectric layer and masking the second dielectric layer to define a source region and a drain region. The method also includes the steps of anisotropically etching to form sidewall spacers contiguous with the gate, collimated sputtering to deposit a layer of silicon, and implanting ions into the deposited silicon.

Abstract: A strip for TiN with selectivity to TiSi2 consisting of a water solution of H2O2 with possible small amounts of NH4OH.

Abstract: The present invention relates to high aspect-ratio electrical connections, wiring trenches, and methods of forming the same in semiconductor devices. In particular, the present invention relates to formation of contacts with refractory metal and/or refractory metal nitride liners that assist in filling of the contacts. Additionally disclosed is the combination of shallow junction fabrication and high aspect-ratio contact formation to form contacts between a shallow junction and microcircuitry wiring. More particularly, the present invention relates to aluminum filled contacts that fill contact corridors, trenches, or vias in semiconductor devices that are initially lined with a titanium layer and at least one other layer. Preferred other layers include CVD, PVD, or reacted TiN, Co, Ge, and Si.

Abstract: A semiconductor fabrication method is provided for the fabrication of a polysilicon-based load circuit (called poly-load) for SRAM (static random-access memory). In accordance with this method, a lightly doped polysilicon layer is formed. This lightly doped polysilicon layer is doped with an impurity element to a predetermined concentration corresponding to the desired resistive characteristic of the poly-load. Further, this lightly-doped polysilicon layer is partitioned into two parts: a first part to be formed into the desired poly-load and a second part to be formed into a conductive interconnecting line that is electrically connected to the poly-load. After this, a metal silicide layer is formed over the second part of the lightly doped polysilicon layer to serve as the conductive interconnecting line. Next, an ILD (Inter Layer Dielectric) layer is formed over the poly-load and the conductive interconnecting line, and then the ILD layer is subjected to a densification process.

Abstract: A liner material and method of use is disclosed. The method includes depositing a silicon layer into a deep void, such as a via or trench, and physical vapor depositing a cobalt seed layer onto the silicon. A supplemental cobalt layer is electroplated over the seed layer. The structure is then annealed, forming cobalt silicide (CoSix). The layer can be made very thin, facilitating further filling the via with highly conductive metals. Advantageously, the layer is devoid of oxygen and nitrogen, and thus allows low temperature metal reflows in filling the via. The liner material has particular utility in a variety of integrated circuit metallization processes, such as damascene and dual damascene processes.

Abstract: An integrated circuit device is presented. The integrated circuit device of the present invention comprises a semiconductor substrate having a combination of transistor gates formed using a conventional dielectric-capped gate stack for self-aligned diffusion contacts (SAC) as well as a transistor gate structure formed by removing the dielectric-cap gate stack from selected regions of the semiconductor substrate and replacing the dielectric-cap gate stack with a second gate conductor which is patterned using a damascene process.

Abstract: A gate insulator layer is formed over the semiconductor substrate and a first silkcon layer is then formed over the gate insulator layer. An first dielectric layser is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, of the first silicon layer, and of the first dielectric layer. A doping step using low energy implantation or plasma immersion is carried out to dope the substrate to form an extended source/drain junction in the substrate under a region uncovered by the gate region. An undoped spacer structure is formed on sidewalls of the gate region and a second silicon layer is formed on the semiconductor substrate. The first dielectric layer is then removed and another doping step is performed to dope the first silicon layer and the second silicon layer. A series of process is then performed to form a metal silicide layer on the first silicon layer and the second silicon layer and also to diffuse and activate the doped dopants.

Abstract: A method of fabricating a crown capacitor comprises first providing a substrate having a transistor, constituted by at least one diffused region, formed thereon and overlaid by a first insulating layer. Bit lines are formed in the first insulating layer. A first masking layer and a second insulating layer are sequentially formed over the substrate. The second insulating layer, the first masking layer and the first insulating layer are patterned to form a contact hole that exposes the diffused region. A second masking layer is conformally formed and etched back to form masking spacers on the sidewalls of the contact hole. The second insulating layer is removed. A first conductive layer is conformally formed over the first masking layer and extending to the surface of the masking spacers and the bottom of the contact hole. A third insulating layer is formed over the first conductive layer and fills the contact hole.

Abstract: A method for forming a barrier metallization layer upon a semiconductor substrate. A semiconductor substrate is provided which has formed upon its surface a barrier metallization layer. The barrier metallization layer has formed in-situ upon its surface a silicon layer. The silicon layer has a thickness such that the contact resistance of the barrier metallization layer is not substantially increased. In a further embodiment, the barrier metallization layer and the silicon layer are sintered to form a metal silicide layer upon the surface of the barrier metallization layer.

Abstract: A process sequence for forming a semiconductor device utilizes a passivation annealing process using deuterium which enhances immunity to hot carrier effects and extends device lifetime. The process sequence is carried out prior to the introduction of metal conductive films to the device. The process sequence includes a three-step passivation, de-passivation, re-passivation sequence and utilizes a barrier film to encapsulate deuterium molecules in the vicinity of a gate oxide, during the de-passivation operation.

Abstract: Insulated electrodes are formed by first forming on an integrated circuit substrate, an insulating layer, a conductive layer on the insulating layer, and a metal silicide layer on the conductive layer, and then forming a metal silicon nitride layer on the metal silicide layer. The metal silicon nitride layer acts as a silicon protrusion-preventing layer on the metal silicide layer that prevents formation of silicon protrusions from the metal silicide layer during subsequent processing. Reliability and/or yield problems that are caused by undercutting of an insulation layer in an insulated electrode may also be reduced by forming on an integrated circuit substrate, an insulating layer, conductive layer on the insulating layer and a metal silicide layer on the conductive layer.

Abstract: A method of fabricating a one-time programmable read only memory (OTP-ROM) with reduced size is disclosed. In accordance with the method of the present invention, a stacked structure is formed on a substrate. The stacked structure comprises a first oxide layer, a first polysilicon layer, and a second oxide layer formed in sequence on the substrate. The substrate beside the stacked structure is exposed by the stacked structure. An implanted region is formed in the exposed substrate beside the stacked structure. A spacer is formed on a sidewall of the stacked structure. A silicide layer is formed on the implanted region. A silicon nitride layer is formed to cover the second oxide layer, the spacer, and the silicide layer. A second polysilicon layer is formed to cover the silicon nitride layer. The second polysilicon layer is patterned to form a control gate. The first polysilicon layer is further patterned to form a floating gate.

Abstract: A method for fabricating a low resistivity polymetal silicide conductor/gate comprising, the steps of forming a polysilicon (66) over a gate oxide (64) followed by protection of the polysilicon (66) with a sacrificial material (68), is disclosed. Gate sidewalls (70) are created to protect the sides of the polysilicon (66) and the sacrificial material (68), followed by stripped the sacrificial material (68) to expose the top surface of the polysilicon (66). Next, a diffusion barrier (76) is deposited over the exposed polysilicon (66) and a metal layer (78) is selectively grown on the diffusion barrier (76) to form a gate contact and conductor. Finally, a dielectric layer (80) is deposited over the selectively grown metal layer (78), the sidewalls (70) and the gate oxide (64).

Abstract: A new method of tungsten plug metallization using a silicide glue layer is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer is provided covering the semiconductor device structures wherein a contact opening is made through the insulating layer to one of the semiconductor device structures. A silicide layer is deposited conformally over the surface of the insulating layer and within the contact opening as a combined ohmic contact and glue layer. In a first embodiment, a tungsten layer is deposited overlying the silicide layer. The tungsten layer not within the contact opening is removed to complete the formation of the tungsten plug metallization. In a second embodiment, the silicide layer not within the contact opening is selectively removed and a tungsten layer is selectively deposited overlying the silicide layer within the contact opening to complete formation of the tungsten plug metallization in the fabrication of an integrated circuit.

Abstract: Low resistivity contacts are formed on source/drain regions and gate electrodes at a suitable thickness to reduce parasitic series resistances, thereby significantly reducing consumption of underlying silicon, while significantly reducing junction leakage. Embodiments include selectively depositing a metal layer, such as nickel, on the source/drain regions and on the gate electrode and ion implanting to form a barrier layer within the nickel layers which does not react with silicon or nickel silicide during subsequent solicitation. The barrier layer confines salicidation to the relatively thin underlayer layer of nickel, thereby minimizing consumption of underlying silicon while the unsilicidized overlying nickel on the barrier layer ensures low sheet resistivity.

Abstract: A gate electrode is made up of a polycrystalline silicon film containing phosphorous as a dopant for determining its conductivity type, a titanium silicide film of the C54 structure, and a tungsten silicide film all of which films are laid one on another in said order. A method of manufacturing a semiconductor device of the present invention involves sequentially forming a non-single-crystal silicon film containing a dopant for determining a conductivity type of the non-single-crystal silicon film, a titanium film, and a metal silicide film on a substrate. A titanium silicide film of a C49 and/or C54 structure is formed by performing a heat treatment so as to cause the titanium film to react with the non-single-crystal silicon film while reducing a first native oxide film formed in a first interface between the titanium film and the non-single-silicon film and a second native oxide film formed in a second interface between the titanium film and the metal silicide film.

Abstract: A process for forming a tungsten plug structure, in a narrow diameter contact hole, has been developed. The process features the use of a composite layer, comprised on an underlying titanium layer, and an overlying, first titanium nitride barrier layer, on the walls, and at the bottom, of the narrow diameter contact hole. After an RTA procedure, used to create a titanium silicide layer, at the bottom of the narrow diameter contact hole, a second titanium nitride layer is deposited, to fill possible defects in the underlying first titanium nitride, that may have been created during the RTA procedure. The tungsten plug structure is then formed, embedded by dual titanium nitride barrier layers.

Abstract: A method of depositing metal silicide onto a semiconductor substrate includes a step of depositing, by a CVD process, a first metal silicide layer with silane gas onto the semiconductor substrate. The method also includes a step of thermally treating and chemically cleaning the semiconductor substrate. The method further includes a step of depositing, by the CVD process, a second metal silicide layer with silane gas onto the semiconductor substrate. By this method, cracks in the metal silicide formed on the semiconductor substrate are minimized.

Abstract: A contact is selectively formed in a contact hole in an insulating layer deposited on a silicon substrate. The contact hole exposes a portion of the substrate. The contact is formed by selectively forming a first layer of titanium silicide in the contact hole on the exposed portion of the substrate. A layer of titanium nitride is then selectively formed on the first layer of titanium silicide. A second layer of titanium silicide is thereafter selectively formed on the layer of titanium nitride to form the contact.

Abstract: A process for forming a silicided MOS transistor (100) begins by providing source and drain regions (104) and (106) and a gate electrode (110). Silicon nitride spacers (116) are formed adjacent the gate electrode (110). A cobalt layer (118) and an overlying titanium layer (120) are then deposited in contact with the regions (104), (106), and (110). A rapid thermal process (130) is then used to react the titanium, cobalt, and silicon together to form silicide regions (124), (126), and (128), and intermetallic compound layers (132) and (134). The intermetallic compound layers (132) and (134) are then etched using two sequentially-performed wet etch steps (136) and (138). The resulting structure (100) has a nitride spacer (116) and field oxide regions (107) which are free from cobalt residual contamination (38).

Abstract: A method for forming a multilevel interconnection between a polycide layer and a polysilicon layer is disclosed. The multilevel interconnection comprises: forming a first impurity-containing conductive layer on a semiconductor substrate; forming a first silicide layer, having a first region thinner than a second region, on the first impurity-containing conductive layer; forming an interlayer dielectric layer in other than the first region; forming a contact hole for exposing the first silicide layer of the first region; and connecting a second impurity-containing conductive layer to the first silicide layer through the contact hole.

Abstract: A method of fabricating a self-align-contact is provided. A first gate and a second gate are formed on a semiconductor substrate. A spacer is formed on the sidewalls of the first gate and the second gate, and a source/drain region is formed between the first gate and the second gate. A dielectric layer is formed on the first gate, the second gate, the source/drain region, the spacer, and the semiconductor substrate. A self-align-contact opening is formed in the dielectric layer to expose the source/drain region. A metal silicide layer is formed on the source/drain region. A first conductive layer, such as doped polysilicon, is formed on the metal silicide layer and in the self-align-contact opening. A second conductive layer is formed on the first conductive layer, and the first conductive layer and the second conductive layer are patterned.

Abstract: A semiconductor device manufacturing method is provided. In this method for interconnecting conductive layers, an insulating layer is formed over the surface of a semiconductor substrate having conductive layers formed thereon. The insulating layer is removed from over the conductive layers and a silicon layer is coated on the overall surface of the resultant structure. The insulating layer and some silicon are then removed from an area except for the area from a first conductive layer through a second conductive layer, and a refractory metal layer is formed on the overall surface of the resultant structure. This refractory metal is used for silicidation. A metal silicide layer is then formed from the first conductive layer through the second conductive layer by thermally treating the refractory metal layer.

Abstract: A method for forming ultra shallow junctions in a semiconductor wafer with reduced silicon consumption during salicidation supplies additional silicon during the salicidation process. After the gate and source/drain junctions are formed in a semiconductor device, high resistivity metal silicide regions are formed on the gate and source/drain junctions. Silicon is then deposited in a layer on the high resistivity metal silicide regions. An annealing step is then performed to form low resistivity metal silicide regions on the gate and source/drain junctions. The deposited silicon is a source of silicon that is employed as a diffusion species during the transformation of the high resistivity metal silicide (such as CoSi) to a low resistivity metal silicide (such as CoSi.sub.2).

Abstract: A stable, high-value polysilicon resistor is achieved by using a silicide layer that prevents diffusion of hydrogen into the resistor. The resistor can also be integrated into a salicide process for making FETs without increasing process complexity. A polysilicon layer with a cap oxide is patterned to form FET gate electrodes and the polysilicon resistor. The lightly doped source/drains, insulating sidewall spacers, and source/drain contacts are formed for the FETs. The cap oxide is patterned to expose one end of the resistor, and the cap oxide is removed from the gate electrodes. A refractory metal is deposited and annealed to form the salicide FETs and concurrently to form a silicide on the end of the resistor. The unreacted metal is etched. An interlevel dielectric layer is deposited and contact holes with metal plugs are formed to both ends of the resistor. A metal is deposited to form the first level of metal interconnections, which also provides contacts to both ends of the resistor.

Abstract: Interconnects for semiconductor devices are formed by forming a reaction control layer on a lower conductive layer of a semiconductor device, forming a reactive metal layer on the reaction control layer, opposite the lower conductive layer, reacting the lower conductive layer with the reactive metal layer, through the reaction control layer, to form an ohmic contact for the semiconductor device, and forming an upper conductive layer on the ohmic contact, opposite the lower conductive layer. Interconnects so formed may provide reduced contact resistance and reduced agglomeration of the ohmic contact region, independent of reaction temperatures. The reactive metal layer is preferably a refractory metal and the reaction control layer is preferably a refractory metal compound. The upper conductive layer is also preferably a refractory metal.

Abstract: A method of fabricating a DRAM integrated circuit structure (30) and the structure so formed, in which a common interconnect material (42, 48) is used as a first level interconnection layer in both an array portion (30a) and periphery portion (30p) is disclosed. The interconnect material (42, 48) consists essentially of titanium nitride, and is formed by direct reaction of titanium metal (40) in a nitrogen ambient. Titanium silicide (44) is formed at each contact location (CT, BLC) as a result of the direct react process. Storage capacitor plates (16, 18) and the capacitor dielectric (17) are formed over the interconnect material (42, 48), due to the thermal stability of the material. Alternative processes of forming the interconnect material (42, 48) are disclosed, to improve step coverage.

Abstract: A method for making interlevel contacts having low contact resistance (R.sub.c) between patterned polycide layers is described. The method and resulting contact structure consists of depositing and conductively doping a first polysilicon layer having a first tungsten silicide (WSi.sub.2) layer. The first polysilicon/silicide (first polycide) layer is patterned to form the first polycide interconnecting conducting layer. An insulating layer is deposited over the patterned first polycide layer and contact openings are anisotropically plasma etched in the insulating layer to the underlying polycide layer. The etching is continued to remove completely the first silicide layer in the contact openings, and to etch into the first polysilicon layer. After a brief hydrofluoric (HF) etch, a second doped polysilicon layer is deposited and patterned to form a second conducting interconnecting level over the contact openings.

Abstract: The present invention is directed to a method for forming semiconductor devices and semiconductor device precursors having gradual slope contacts. The method for forming a semiconductor precursor includes the steps of: forming a layer of conductive material in a first layer; forming a layer of a hard mask material onto at least a portion of the first layer; etching the layer of hard mask material to expose a portion of the first layer; forming facets on the layer of hard mask material; and forming a via in the first layer such that the via extends through the first layer to expose at least a portion of the layer of conductive material.

Abstract: A process for the controlled formation of self-aligned dual thickness cobalt silicide layers during the manufacturing of a semiconductor device that requires a minimum number of steps and is compatible with standard MOS processing techniques. In the process according to the present invention, a semiconductor device structure (such as an MOS transistor) is first provided. The semiconductor device structure includes exposed silicon substrate surfaces (such as shallow drain and source regions) and a silicon layer structure disposed above the semiconductor substrate surface (such as a polysilicon gate). A cobalt layer is then deposited over the semiconductor device structure followed by the deposition of a titanium capping layer. Next, the thickness of the titanium capping layer above the silicon layer structure (e.g. a polysilicon gate) is selectively reduced using, for example, chemical mechanical polishing techniques.

Abstract: The present invention pertains to a carrier layer and a contact enabled by the carrier layer which enables the fabrication of aluminum (including aluminum alloys and other conductive materials having a similar melting point) electrical contacts in multilayer integrated circuit vias, through holes, or trenches having an aspect ratio greater than one. In fact, the structure has been shown to enable such contact fabrication in vias, through holes, and trenches having aspect ratios as high as at least 5:1, and should be capable of filing apertures having aspect ratios up to about 12:1. The carrier layer, in addition to permitting the formation of a conductive contact at high aspect ratio, provides a diffusion barrier which prevents the aluminum from migrating into surrounding substrate material which operates in conjunction with the electrical contact.