Abstract: A method for forming salicide on the peripheral logic region of the embedded DRAM without using a salicide block mask layer to protect the memory cell region of the embedded DRAM and without oxide wet dip to prevent oxide loss in the field oxide is disclosed. Additionally, the landing plug process in the memory cell region is performed by a self-aligned contact (SAC) etching process with a silicon nitride layer as an etching protective layer.

Abstract: A method of manufacturing a semiconductor device in which a cobalt silicide layer is formed on a semiconductor substrate. In the method, the semiconductor substrate is prepared, and cobalt is deposited on the semiconductor substrate by sputtering while heating the semiconductor substrate at a temperature approximately equal to 200 degrees Celsius. Thereafter, cobalt is deposited on the semiconductor substrate by sputtering while heating the semiconductor substrate at a temperature between 300 degrees Celsius and 400 degrees Celsius without exposing the semiconductor substrate to the atmosphere. Preferably, the semiconductor substrate is thereafter rapid thermal annealed at a temperature equal to or higher than 500 degrees Celsius in nitrogen atmosphere for a predetermined time. Further, at least a part of cobalt portion or cobalt oxide portion on the semiconductor substrate is removed by wet etching.

Abstract: A method for establishing low sheet resistance for the Titanium Salicide process that teaches a C-54 TiSix process by means of an additional vacuum bake. The present invention teaches an additional vacuum bake step prior to pre-metal HF dip during the Si-ion mixing process, an additional vacuum bake step prior to PAI during the PAI process, an additional vacuum bake step prior to pre-metal HF dip during the PAI process.

Abstract: According to a method of manufacturing a MIS semiconductor device of the present invention, a gate insulating film is formed on a silicon substrate, and a silicon thin film is deposited on the gate insulating film, whereafter a silicon film containing germanium is deposited on the silicon thin film and an amorphous silicon film is deposited on the germanium-containing silicon film. Further, heat treatment is performed to diffuse the germanium in the germanium-containing silicon film into the silicon thin film, and a metal film is deposited on the amorphous silicon film and heat treatment is performed to cause a silicidation reaction to occur with the metal film to form a silicide film. Therefore, the germanium-containing silicon film which can control gate depletion can be formed stably with a good reproducibility. Further, since the silicide film on the gate electrode is formed on the silicon film, it can be formed with a low resistance.

Abstract: In producing a thin film transistor used for such devices as a large-sized liquid crystal display panel with a high pixel density, a leftover of an insulating film caused by insufficient etching and a loss of a semiconductor layer caused by overetching are prevented, and a reliable electrical contact between the source and drain electrodes and the semiconductor layer is achieved. These are achieved by (a) forming a contact hole region of a silicon film so that the region has a larger thickness, for example, by making the film to have a plurality of layers, and (b) providing a silicide layer between an electrode metal and the semiconductor layer.

Abstract: The invention advantageously provides a novel method for making self-aligned contacts on a semiconductor substrate. A gate electrode having a vertical sidewall and a protecting layer thereon is formed over the semiconductor substrate. A doped region is formed in the substrate adjacent to the gate electrode. An insulating sidewall spacer is formed on the sidewall of the gate electrode. A second doped region is formed in the substrate adjacent to the sidewall spacer. A second protecting layer is formed to cover or blanket the first protecting layer, the sidewall spacer, and the substrate. An interlayer insulting layer is provided on the second protecting layer in order to form a planer surface. The interlayer insulating layer and the second protecting layer are etched to expose the doped regions to form the self-aligned contacts.

Abstract: A method of fabricating a self-align-contact is provided. A first gate and a second gate are formed on a semiconductor substrate. A spacer is formed on the sidewalls of the first gate and the second gate, and a source/drain region is formed between the first gate and the second gate. A dielectric layer is formed on the first gate, the second gate, the source/drain region, the spacer, and the semiconductor substrate. A self-align-contact opening is formed in the dielectric layer to expose the source/drain region. A metal silicide layer is formed on the source/drain region. A first conductive layer, such as doped polysilicon, is formed on the metal silicide layer and in the self-align-contact opening. A second conductive layer is formed on the first conductive layer, and the first conductive layer and the second conductive layer are patterned.

Abstract: A process for the formation of metal salicide regions and metal salicide exclusion regions in an integrated circuit (IC) that requires a minimum number of steps and is compatible with standard MOS processing techniques. In the process, an IC structure is first provided. The IC structure includes a plurality of MOS transistor structures with exposed silicon surfaces, such as source regions, drain regions and polysilicon gates. A metal layer (e.g., cobalt, titanium, tantalum, nickel or molybdenum) is then deposited over the IC structure, followed by the formation of a photoresist masking layer on those MOS transistor structures where metal salicide regions are to be formed. The metal layer from those MOS transistor structures where metal salicide exclusion regions are to be formed is then removed, followed by stripping of the photoresist masking layer from those MOS transistor structures where metal salicide regions are to be formed.

Abstract: A method of substantially reducing Si consumption and bridging during metal silicide contact formation comprising the steps of: (a) forming a metal silicon alloy layer over a silicon-containing substrate containing an electronic device to be electrically contacted, said silicon in said alloy layer being less than about 30 atomic % and said metal is Co, Ni or mixtures thereof; (b) annealing said metal silicon alloy layer at a temperature of from about 300° to about 500° C. so as to form a metal rich silicide layer that is substantially non-etchable compared to said metal silicon alloy or pure metal; (c) selectively removing any non-reacted metal silicon alloy over non-silicon regions; and (d) annealing said metal rich silicide layer under conditions effective in forming a metal silicide phase that is in its lowest resistance phase. An optional oxygen barrier layer may be formed over the metal silicon alloy layer prior to annealing step (b).

Abstract: The present invention is directed to a method for forming semiconductor devices and semiconductor device precursors having gradual slope contacts. The method for forming a semiconductor precursor includes the steps of: forming a layer of conductive material in a first layer; forming a layer of a hard mask material onto at least a portion of the first layer; etching the layer of hard mask material to expose a portion of the first layer; forming facets on the layer of hard mask material; and forming a via in the first layer such that the via extends through the first layer to expose at least a portion of the layer of conductive material.

Abstract: The present invention relates to an integrated circuit wiring capable of reducing the contact resistance between lines and a fabricating method thereof. The wiring in accordance with the present invention includes a gate oxide film formed on the upper surface of a semiconductor device. A first line including a first silicon film pattern that is formed on an upper surface of the gate oxide film and has a certain width; and a silicide film pattern that is formed on the upper surface of the first silicon film and has a smaller width than that of the first silicon film pattern to thereby expose a certain region of the first silicon film pattern. A second line is formed to contact the silicide film pattern and the exposed certain region of the silicon film pattern.

Abstract: A contact interface having a substantially annular silicide ring along sides of a depression formed in an active surface of the semiconductor substrate, wherein the depression is formed by an etching process to form a contact opening through a dielectric layer. The contact interface is formed by depositing a layer of conductive material, such as titanium, with a high bias power IMP deposition. The conductive material is turned to a silicide by an annealing process, thereby forming the contact interface.

Abstract: Disclosed herein is a method for manufacturing a semiconductor device having a high melting point metal silicide layer, especially a cobalt silicide layer. The uniformity of the metal silicide layer improves characteristics of the semiconductor device such as a heat resistance. In the present invention, the uniformity of the eventual metal silicide layer is improved by adjusting the degree of ion-implantation and thermal treatment of a precursor of the metal silicide layer.

Abstract: A method for manufacturing a salicide transistor, a semiconductor storage, and a semiconductor device that can solve both an increase in narrow-line resistance and an increase in P-N-junction leakage, and can give an optimized process as the total LSI device manufacturing process flow. After adding an impurity in the high-concentration source/drain region on a semiconductor substrate, a heat treatment is performed at a first temperature, then a heat treatment is performed for forming salicide at a second temperature higher than a predetermined temperature and lower than the first temperature for a first period of time, an interlayer insulating film is formed, and heat treatment is performed at a third temperature higher than the second temperature and lower than the first temperature. Since the crystallinity of the implanted layer 109 has been recovered before forming the silicide protecting film, salicide can be formed under the conditions where the crystallinity of the diffusion layer is good.

Abstract: There is provided a method for manufacturing a semiconductor device for forming a silicide layer of metal of high melting point, wherein the metal of high melting point is processed in sputtering under a condition in which no deterioration is produced by the sputtering apparatus. There is also provided a sputtering apparatus for manufacturing semiconductor device. In the method of the present invention, a high melting point metal is accumulated on a silicon substrate formed with a gate electrode of a semiconductor element to form a metallic film of high melting point, thereafter it is heat treated to form a silicide layer of the high melting point metal at an interface layer with the metallic film with high melting point, and in this case, the metallic film of high melting point is accumulated in sputtering by a magnetron sputtering device under a condition in which an electrical load amount Q reaching to the gate electrode is less than 5 C/cm2.

Abstract: A method for manufacturing a capacitor. A semiconductor substrate is divided into a peripheral circuit region and a memory cell region. An isolation structure is formed in the memory cell region. A gate oxide layer is formed over the substrate outside the isolation structure. A polysilicon layer is formed over the gate oxide layer and the isolation structure. The polysilicon layer and the gate oxide layer are patterned to form a bottom electrode above the isolation structure. In the meantime a polysilicon gate electrode is also formed above the peripheral circuit region. Spacers are formed on the sidewalls of the polysilicon gate electrode and the bottom electrode. A metal silicide layer is formed over the bottom electrode and the polysilicon gate electrode. A dielectric layer is formed over the metal silicide layer above the bottom electrode. A metallic layer is formed over the dielectric layer to form a capacitor.

Abstract: A method of forming a crystalline phase material includes, a) providing a stress inducing material within or operatively adjacent a crystalline material of a first crystalline phase; and b) annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. The stress inducing material preferably induces compressive stress within the first crystalline phase during the anneal to the second crystalline phase to lower the required activation energy to produce a more dense second crystalline phase. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials for providing into layers are Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material.

Abstract: A method of forming electrical contacts includes the step of implanting ions into a contact hole at an angle to create an enlarged plug enhancement region at the bottom of a contact hole. Thus, even if the contact hole is misaligned, over-sized, or over-etched, the enlarged plug enhancement region contains subsequently formed barrier layers and other conductive materials to reduce current leakage into the underlying substrate or into adjacent circuit elements.

Abstract: After a metal deposition preclean, a very thin titanium layer is deposited followed by a thick nickel layer on a semiconductor silicon substrate. The titanium and nickel are deposited sequentially in a vacuum cluster tool to prevent oxidation of titanium in air. The silicon substrate and the metal layers are subject to a relatively low temperature anneal. The annealing causes the titanium to act as a reductant to break up the residual surface oxide on the surface of the silicon substrate and allows the nickel to react with the silicon substrate to form nickel silicide.

Abstract: Capping layer adhesion to a Cu or Cu alloy interconnect member is enhanced by treating the exposed surface of the Cu or Cu alloy interconnect member with a hydrogen plasma to substantially reduce oxides thereon, forming a thin layer of copper silicide on the treated surface and depositing the capping layer thereon. Embodiments include electroplating or electroless plating Cu or a Cu alloy to fill a damascene opening in a dielectric layer, chemical-mechianiical polishing, hydrogen plasma treatment, reacting the treated surface with silane or dichlorosilane to form a layer of copper silicide on the treated surface and depositing a silicon nitride capping layer on the thin copper silicide layer.

Abstract: A multiple step chemical vapor deposition process for depositing a tungsten silicide layer on a substrate. A first step of the deposition process includes a pretreatment step in which WF6 is introduced into a deposition chamber. Next, the introduction of WF6 is stopped and a silicon-containing gas, e.g., SiH4, is introduced into the chamber. Finally, during a third step, the SiH4 flow is stopped and DCS and WF6 are introduced into the chamber to deposit a tungsten silicide layer on the substrate.

Abstract: A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of metal. The layer of metal silicide is patterned to define the boundaries of the local interconnect. The metal silicide is reacted with the layer of metal to form a composite structure. The composite structure includes the metal silicide, another metal silicide formed as silicon from the metal silicide reacts with the underlying layer of metal and an intermetallic compound of the metal from the layer of metal and metal from the layer of metal silicide.

Abstract: There is provided an RF sputtering film forming method of forming a compound film having a stable composition by use of stable plasma with a broad process window to thus facilitate composition control of the compound film. In the RF sputtering film forming method, an alternating voltage or alternating current is applied to a part or all of walls positioned on the outside of a space formed between a wafer and a target, or an electron temperature in the plasma is reduced by oscillating the RF power in a pulse fashion, or a sputtering gas is composed of at least one kind of gases of helium, neon, xenon, and krypton, or a minus voltage is applied to a part or all of the walls positioned on the outside of the space formed between the wafer and the target.

Abstract: A method for establishing low sheet resistance for the Titanium Salicide process that teaches a C-54 TiSix process by means of an additional vacuum bake. The present invention teaches an additional vacuum bake step prior to pre-metal HF dip during the Si-ion mixing process, an additional vacuum bake step prior to PAI during the PAI process, an additional vacuum bake step prior to pre-metal HF dip during the PAI process.

Abstract: A self-aligned silicide process. A substrate has at least a transistor formed thereon. A thin metal layer is formed over the substrate. A first rapid thermal process is performed to make the metal layer react with polysilicon of the gate and of the source/drain regions to form a first metal silicide layer. The metal layer, which does not react with polysilicon, is removed. A selective raised salicide process is performed to form a second metal silicide layer on the first metal silicide layer. A second rapid thermal process is performed to transform the first metal silicide layer and the second metal silicide layer from a high-resistance C49 phase into a low-resistance C54 phase.

Abstract: Method for forming a metal line in a semiconductor device, which can effectively suppress abnormal oxidation in formation of metal line of tungsten or tungsten silicide, including the steps of (1) forming an insulating material layer on a semiconductor substrate, and forming a conduction line on the insulating material layer, (2) nitriding an exposed surface of the conduction line, and (3) oxidizing the semiconductor substrate including the conduction line having a nitride layer formed on the exposed surface thereof.

Abstract: Disclosed is a novel contact structure comprising an underlying layer of titanium silicide, an intermediate layer of titanium boride, and an overlying layer of polysilicon. Also disclosed is a method for forming the contact structure which comprises depositing a titanium layer in the bottom of a contact opening having oxide insulation sidewalls, forming an overlying layer of polysilicon above the titanium layer, and annealing the two layers together. The resulting contact structure is formed with fewer steps than contact structures of the prior art and without the need for additional steps to achieve uniform sidewall coverage, due to high adhesion of the overlying layer of polysilicon with oxide insulation sidewalls of the contact opening. The contact structure has low contact resistance, and provides a suitable diffusion barrier due to a high melting point.

Abstract: A method of forming a silicide on a silicon layer. First, a monosilane based tungsten-silicide layer is formed on the silicon layer. Next, a dichlorosilane based tungsten-silicide layer is formed on the monosilane based tungsten-silicide layer.

Abstract: An integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors of the memory cells.

Abstract: A method of manufacturing semiconductor device which can reduce contact resistance and stabilize contact interface, is disclosed. According to the present invention, firstly, a semiconductor substrate on which a lower conductor pattern is formed is provided. The lower conductor pattern has a first doped polysilicon layer and a first tungsten silicide layer formed thereon. Next, an intermediate insulating layer is formed on the substrate. The intermediate insulating layer is then etched to expose a portion of the surface of the first tungsten silicide layer of the lower conductor pattern, thereby forming a contact hole. Thereafter the substrate in which the contact hole is formed, is thermally treated by rapid thermal processing under H2 atmosphere. A second doped polysilicon layer and the second tungsten silicide layer are then formed on the surface of the contact hole treated thermally and on the intermediate insulating, sequentially.

Abstract: A process for forming a metal silicide interconnect includes applying a layer of polysilicon over a semiconductor layer. A layer of amorphous silicon is formed over the layer of polysilicon followed by a layer of metal, such as titanium, over the layer of amorphous silicon. A second layer of amorphous silicon may also be formed over the layer of metal. The layer of titanium is reacted with the layer of amorphous silicon to form a small grain C49 layer of titanium silicide. The layer of polysilicon and the layer of titanium silicide are etched to form a desired interconnect structure. The small grain C49 layer of titanium silicide is then converted to the C54 phase.

Abstract: In one aspect, the invention provides a method of forming an integrated circuitry memory device. In one preferred implementation, a conductive layer is formed over both memory array areas and peripheral circuitry areas. A refractory metal layer is formed over the conductive layer to provide conductive structure in both areas. According to a preferred aspect of this implementation, the conductive layer which is formed over the memory array provides an electrical contact for a capacitor container to be formed. According to another preferred aspect of this implementation, the conductive layer formed over the peripheral circuitry area constitutes a conductive line which includes at least some of the silicide. In another preferred implementation, the invention provides a method of forming a capacitor container over a substrate. According to a preferred aspect of this implementation, a conductive layer is elevationally interposed between an upper insulating layer and a lower conductive layer over the substrate.

Abstract: A method for forming uniform ultrathin silicide features in the fabrication of an integrated circuit is described. A metal layer is deposited over the surface of a silicon semiconductor substrate. An array of heated metallic tips contact the metal layer whereby the metal layer is transformed to a metal silicide where it is contacted by the metallic tips and wherein the metal layer not contacted by the metallic tips is unreacted. The unreacted metal layer is removed leaving the metal silicide as uniform ultrathin silicide features. Alternatively, a metal acetate layer is spin-coated over the surface of a silicon semiconductor substrate. An array of heated metallic tips contacts the metal acetate layer whereby the metal acetate layer is transformed to a metal silicide where the metallic tips contact the metal acetate layer and wherein the metal acetate slayer not contacted by the metallic tips is unreacted.

Abstract: According to one embodiment of the invention, a high pressure anneal is utilized to form titanium silicide at the bottom of a contact hole, at a pressure of at least approximately 1.1 atmospheres, from a reaction between deposited titanium and underlying silicon. When such high pressures are used, temperatures of less than approximately 700 degrees Celsius are utilized. According to another embodiment of the invention, a conductive plug fill material is deposited within a contact hole such that the plug structure is relatively free of voids. Either during deposition of the conductive plug fill material or after such deposition, the conductive plug fill material is subjected to a high pressure force-fill, at a pressure of at least approximately 1.1 atmospheres. When such high pressures are used, temperatures of less than approximately 700 degrees Celsius are utilized for the force-fill. Aluminum can be used for the conductive plug fill material when using this embodiment of the invention.

Abstract: A process for forming a metal silicide layer on a conductive region in a semiconductor substrate, located at the bottom of a high aspect ratio contact hole, and for selectively forming a barrier layer on the underlying metal silicide layer, has been developed. After opening a high aspect ratio contact hole in an insulator layer, titanium ions are directionally implanted into a top portion of the conductive region, exposed at the bottom of the high aspect ratio contact hole. An anneal procedure, performed in a nitrogen containing ambient, results in the selective formation of a metal silicide layer, such as titanium disilicide, on the conductive region, and results in the selective formation of a barrier layer, such as titanium nitride, on the underlying metal silicide layer. Formation of a metal plug structure, in the high aspect ratio contact hole, overlying and contacting the underlying barrier layer, followed by formation of an overlying metal interconnect structure, is then accomplished.

Abstract: A method for forming a refractory metal silicide layer on a silicon surface in which a first layer of a refractory metal is formed on the silicon surface. A second layer extends over the first layer and is made of a nitrogen containing refractory metal. The silicon surface and the first and second layers are subjected to a heat treatment in an argon gas atmosphere to form a refractory metal silicide layer on an interface between the silicon surface and the first layer.

Abstract: A method for forming a low resistance metal/polysilicon gate for use in CMOS devices comprising: (1) a novel anneal step prior to formation of a diffusion barrier layer and (2) a novel diffusion barrier layer composed of titanium nitride deposited over titanium silicide or titanium nitride deposited directly on the polysilicon. A first insulating layer is formed over a silicon substrate, and a polysilicon layer is formed over the first insulating layer. In a key step, the polysilicon layer is annealed to prevent peeling of the subsequently formed diffusion barrier layer. A diffusion barrier layer comprising titanium nitride deposited over titanium silicide or titanium nitride deposited directly on the polysilicon is formed over the polysilicon layer. A tungsten layer is formed over the diffusion barrier layer, and a capping layer comprising a silicon nitride layer over an oxide layer can be formed over the tungsten layer.

Abstract: Self-aligned silicidation (e.g., Ti, Co, or Ni silicides) for silicon integrated circuits with an HF-based final etch of the silicide to remove filaments. Either ultradilute HF solution or HF vapor may be used.

Abstract: The invention encompasses methods of forming silicide interconnects over silicon comprising substrates. In one implementation, a first layer comprising a metal and a non-metal impurity is formed over a region of a silicon comprising substrate where a silicide interconnection is desired. An elemental metal comprising second layer is formed over the first layer. The substrate is annealed to cause a reaction between at least the elemental metal of the second layer and silicon of the substrate region to form a silicide of the elemental metal of the second layer. In another considered aspect, a method of forming a silicide interconnect over a silicon comprising substrate includes providing a buffering layer to silicon diffusion between a refractory metal comprising layer and a silicon containing region of a substrate.

Abstract: A semiconductor device having a metal interconnection includes an insulating film provided on a semiconductor substrate via a diffusion layer. An interlayer contact hole is formed in the insulating film. A metal silicide layer is provided at the bottom of the interlayer contact hole. A first conductive film comprises a single or a plurality of metal films provided on the insulating film and the interlayer contact hole. A second conductive film is provided in the interlayer contact hole. A third conductive film is provided on the first conductive film and the second conductive film. A fourth conductive film is provided on the third conductive film. This semiconductor device has improved durability with respect to electromigration or stress migration. Even when the interconnection has a multilevel structure, the contact resistance can be reduced by causing the interlayer contact hole portions to contact one another by the same kind of metal.

Abstract: A method of fabricating an improved spacer comprising the steps of providing a semiconductor substrate that has a gate already formed thereon. A PNO spacer is formed on a sidewall of the gate. The method of forming the PNO spacer comprises first forming a PNO layer on the conductive layer and the semiconductor, and performing an anisotropic etching step on the PNO layer to form the PNO spacer. The step of forming the PNO layer includes chemical vapor deposition (CVD) using PH3, O2, NH3 and N2 as reagents. The step of etching the PNO layer includes plasma etching using CFX+O2 as plasma source. The material of the PNO spacer is a chemical compound PXNYOZ containing phosphorous (P), nitrogen (N) and oxygen (O) and does not contain silicon. Therefore, the PNO spacer can avoid erosion during etching and does not react with Ti during the Salicide process.

Abstract: A method for forming a DRAM cell with a crown full metal capacitor electrode with integrated selective tungsten contact hole. When the MOSFET devices are defined, a metal landing pad with Ti/TiN/W/TiN is first deposited and etched. After an insulating layer is deposited and node contact is formed, a CVD TiN layer is deposited and etched to form TiN spacers on the node contact sidewalls. Next, selective tungsten is formed in the node contact and use reactive ion etching to etch back. Thereafter, another insulating layer is deposited and the crown pattern opening is formed. Then, a TiN/W metal layer is deposited to serve as the bottom electrode of the stacked capacitor. After a photoresist layer is formed, then a chemical mechanical polishing method is used to remove portions of the photoresist layer and the TiN/W metal layer by using insulating layer as an polishing stop. The remaining photoresist and insulating layer are removed.

Abstract: A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.

Abstract: Silicide interfaces for integrated circuits, thin film devices, and backend integrated circuit testing devices are formed using a barrier layer, such as titanium nitride, disposed over a porous, thin dielectric layer which is disposed between a silicon-containing substrate and a silicidable material which is deposited to form the silicide interfaces for such devices. The barrier layer prevents the formation of a silicide material within imperfections or voids which form passages through the thin dielectric layer when the device is subjected to a high temperature anneal to form the silicide contact from the reaction of the silicidable material and the silicon-containing substrate.

Abstract: A method and device for improved salicide resistance in polysilicon gates under 0.20 &mgr;m. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure with recessed thick inner spacers and thick outer spacers. Another embodiment provides a gate electrode structure with recessed thin inner spacers and recessed thick outer spacers. Another embodiment provides a gate electrode structure with thin inner spacers and partially recessed outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers. The inner spacer stack with thin inner spacers and thin outer spacers. Another embodiment provides a gate electrode structure with two spacer stacks. The outermost spacer stack with recessed thin inner spacers and recessed thick outer spacers.

Abstract: A method of manufacturing an integrated circuit to optimize the contact resistance between impurity diffusing layers and silicide is disclosed herein. The method includes implanting a first material to a layer of semiconductor to create a buried amorphous silicon layer; implanting a second material in the layer of semiconductor and buried amorphous layer, forming a dopant profile region with a curved shape; depositing a layer of metal on the layer of semiconductor; melting the buried amorphous layer to reconfigure the curved shape to a substantially vertical profile of maximum dopant concentration; and forming silicide with the layer of semiconductor and layer of metal, the bottom of the silicide located in the vertical shape on the dopant profile region.

Abstract: A method for lowering the anneal temperature required to form a multi-component material, such as refractory metal silicide. A shallow layer of titanium is implanted in the bottom of the contact area after the contact area is defined. Titanium is then deposited over the contact area and annealed, forming titanium silicide. A second embodiment comprises depositing titanium over a defined contact area. Silicon is then implanted in the deposited titanium layer and annealed, forming titanium silicide. A third embodiment comprises combining the methods of the first and second embodiments. In further embodiment, nitrogen, cobalt, cesium, hydrogen, fluorine, and deuterium are also implanted at selected times.

Abstract: A semiconductor processing method of making electrical connection between an electrically conductive line and a node location includes, a) forming an electrically conductive line over a substrate, the substrate having an outwardly exposed silicon containing node location to which electrical connection is to be made, the line having an outer portion and an inner portion, the inner portion laterally extending outward from the outer portion and having an outwardly exposed portion, the inner portion having a terminus adjacent the node location, and b) electrically connecting the extending inner portion with the node location. An integrated circuit is also described. The integrated circuit includes a semiconductor substrate, a node location on the substrate, and a conductive line over the substrate which is in electrical communication with the node location. The conductive line includes an outer portion and an inner portion.

Abstract: A process of forming a layer of conductive material over a layer of insulating material is provided. A wafer is positioned on a wafer platform such that it is thermally and electrically coupled to the wafer platform. A clamping ring engages the peripheral edge of the wafer such that the wafer is held against the top surface of the wafer platform. The clamping ring is electrically coupled to the wafer pedestal. The wafer is exposed to a plasma comprising conductive material and an initial layer of conductive material is formed over the insulating layer until the top surface of the wafer is electrically coupled to the clamping ring. The wafer pedestal is then electrically biased and additional conductive material is formed. Once the initial layer of conductive material is electrically coupled to the clamping ring, the potential difference between the top and bottom surface of the wafer is zero such that arcing through the wafer is reduced.

Abstract: A method of filling contact holes in a dielectric layer on an integrated circuit wafer. The method reduces processing steps and results in a reliable metal plug filling the contact hole. In one embodiment the contact hole is filled using blanket deposition of titanium silicide using chemical vapor deposition followed by etchback. In a second embodiment the contact hole is filled with titanium silicide using selective chemical vapor deposition of titanium silicide. In a third embodiment an adhesion layer of titanium silicide is formed on the sidewalls and bottoms of the contact holes. A conductor metal of titanium silicide, aluminum, tungsten, or copper is used to fill the contact hole using selective chemical vapor deposition.