Abstract: A manufacturing method for transistors wherein silicide is directed doped with a conductive impurity includes the steps of: forming a field oxide film defining an active region on a semiconductor substrate; forming transistors wherein a doped first silicide film is formed on gate electrodes on said active region; forming an interlayer dielectric film having contact holes on the whole surface of said semiconductor substrate; forming spacers on the innerwalls of each contact hole;p forming a thin doped polysilicon film on the whole surface of said semiconductor surface; and forming a doped second silicide film on the whole surface of said doped polysilicon film, filling each contact hole. The silicide film is directly doped with conductive impurity so that the conductive impurity of a polysilicon film can be prevented from being diffused to the outside. Therefore, the doped silicide film is useful to prevent the threshold voltage from increasing and the saturation current from reducing.

Abstract: A semiconductor device which can interconnect different types of impurity region without increasing a contact resistance including a first impurity diffusion region formed on a first portion of a semiconductor substrate, a second impurity diffusion region formed on a second portion of the semiconductor substrate, an interlevel insulating layer having a contact hole exposing the first and second impurity regions on the semiconductor substrate, a first conductive layer formed on the interlevel insulating layer, a second conductive layer formed on the overall surface of the substrate, wherein the second conductive layer formed on the first impurity diffusion region is doped with the same impurities as doped into the first impurity diffusion region and the second conductive layer formed on the second impurity diffusion region is doped with the same impurities as doped into the second impurity diffusion region, and a manufacturing method thereof are disclosed.

Abstract: A method for forming a silicide layer in a semiconductor device, including the steps of: forming a refractory metal layer on a semiconductor substrate; forming a cobalt layer on the refractory metal layer; implanting impurities in the interface between the refractory metal layer and the cobalt layer; heat treating the semiconductor substrate such that cobalt atoms from the cobalt layer pass through the refractory metal layer and form a cobalt silicide epitaxy layer on the semiconductor substrate; and removing the remaining cobalt layer and the remaining refractory metal layer.

Abstract: The present invention provides a method for preventing a polycide line situated between two poly-metal dielectric layers from drifting or deformation during a reflow process conducted for the dielectric layers by forming a dummy polycide gate and a dummy contact at a suitable location in the polycide line such that the dummy contact is anchored through the bottom dielectric layer to a dummy gate located on a field oxide isolation in the silicon substrate. The number of dummy contacts and the location for placing such contacts are determined by the length and the configuration of the polycide line and the topography of the dielectric layer that the polycide line is situated on.

Abstract: A method of fabricating an integrated circuit on a semiconductor substrate is provided including the steps of forming a tungsten silicide conductor structure having a nitride encapsulating layer on the substrate and disposing a doped nonconducting layer over the conductor structure. A self-aligned contact etch is performed wherein the etch is a selective etch of the conductor structure and the nonconducting layer. The selective etch preferentially removes material forming the nonconducting layer rather than material forming the conductor structure. The semiconductor layer is preferably doped with germanium but may also be doped with phosphorous or other known dopants. A germanium concentration of 5% to 25% provides the preferred increased selectivity of the etch. The nonconducting layer can be formed of SG, BPSG, BSG, PSG and TEOS.

Abstract: A semiconductor fabrication process has been developed in which both MOS memory devices and MOS logic devices are integrated on a single silicon chip. The process features combining process steps for both device types, however using a self-aligned contact structure, in the MOS memory device region, for purposes of increasing device density, while using metal silicide regions, only in MOS logic device regions, for purposes of improving device performance.

Abstract: A technique for providing a design window for scaled technologies in which good electrostatic discharge/electrical over stress damage and optimum transistor operation can be achieved without the use of additional masks or design steps. The M, beta, and R.sub.sub parameters of the NMOS transistor 13 and associated parasitic npn transistor 10 are selected to provide the design window.

Abstract: A method of forming a transistor having silicide contacts to the gate and source/drain regions. A semiconductor substrate is provided having spaced field oxide regions and active areas. On the active areas, a gate structure is formed having a gate oxide, gate, and gate insulating layer. In an important step, the gate 18 is laterally etched to remove a first width of the gate. A second dielectric layer 22 composed of oxide is deposited over the sidewalls of the gate, the gate 18 and the substrate 10. The second dielectric layer 22 is etched forming sidewall spacers 24 on the sidewalls of the gate 18, the gate insulating layer 20, and the gate oxide layer. The gate insulating layer 20 is then removed with a selective etch. A metal layer 30 is deposited over the resulting surface. The metal layer 30 is heat treated forming a gate silicide contact 36 on the gate 18 and source and drain silicide contacts 34 on the active areas.

Abstract: A process for creating a buried contact structure, for a MOSFET device, to be used in an SRAM cell, has been developed. The process features using a thick tungsten silicide layer, on the sides of a split polysilicon shape, followed by a series of selective, anisotropic RIE procedures, used to create a buried contact structure without crevicing or trenching of the semiconductor substrate, in an region adjacent to the buried contact structure.

Abstract: A method of making a self-aligned silicide component having parasitic spacers formed on the sides of an upper surface of the component isolating regions, the bottom sides of the spacers and the exposed sides of the gate regions, which increases a distance from a metal silicide layer at a corner of an active region neighboring the component isolating region to the source/drain junction, to prevent undesired current leakages. The formation of parasitic spacers increases a distance from the metal silicide layer lying above the gate surface to the metal silicide layer lying above the source/drain surface so that an ability to withstand electrostatic damages is enhanced.

Abstract: A method for manufacturing crown-shaped stacked capacitors on dynamic random access memory using a single photoresist mask to make the node contacts and capacitor bottom electrodes was achieved. After forming the FET gate electrodes from a first polysilicon layer and the bit lines from a second polysilicon layer, a thick planar BPSG and a hard mask composed of polysilicon or silicon nitride is deposited. Openings are etched in the hard mask and partially into the BPSG. Sidewall spacers, composed of Si.sub.3 N.sub.4 or TEOS oxide, are formed in the openings and a special selective high density plasma etch and the etchant gas mixture of O.sub.2, CHF.sub.3, CF.sub.4, CO, C.sub.4 F.sub.8, and Ar is used to form the node contact openings in the BPSG to the FETs. A conformal third polysilicon layer is then deposited and a second masking material is used to define the bottom electrodes having a crown-shape in the BPSG openings.

Abstract: In a method for manufacturing a semiconductor device incorporating a DRAM section and a logic circuit section, a refractory metal layer is formed to cover a bit line of the DRAM section, and a gate electrode and impurity diffusion regions of the logic circuit section. Then, a heating operation is performed upon sadi refractory metal layer, so that metal silicide layers are formed in the bit line of the DRAM section, and the gate electrode and the impurity diffusion regions of the logic circuit section.

Abstract: A method is disclosed for providing a self-aligned silicide strap for connecting thin polysilicon layers (poly-1 and poly-2, etc.) separated by non-conducting gaps. A butting contact opening to the layers is formed in an overlying insulating layer. The contact exposes the poly-1 and poly-2 layers. A thin polysilicon layer (poly-3) is then deposited over the insulating layer and into the contact. This is followed by deposition of a refractory metal layer. The poly-3 layer should be thin enough that, alone, it cannot supply enough silicon to support full silicidation of the refractory metal layer. The structure is next sintered so that a silicide strap is formed in the contact opening and across exposed portions of the poly-1 and poly-2 layers. The ratio of silicon to titanium in regions over the insulating layer is lower than that in the strap, such that these more metallic regions may be selectively removed.

Abstract: A local interconnection structure is disclosed. The local interconnection structure is formed on a silicon substrate in which a polysilicon gate and a number of diffusion regions exist. The structure includes a number of metal silicide layers over the substrate, a metal nitride layer over the silicide layers, and a dielectric layer over the nitride layer. The metal nitride layer which electrically connects the diffusion regions and the gate forms the interconnection. The method for fabricating the interconnection structure includes the steps of preparing the silicon substrate, sputtering a metal layer, annealing to form silicide and the nitride layers, depositing the dielectric layer, and patterning the nitride layer and the metal nitride by covering with a mask, etching away portions of both the dielectric layer and metal nitride layer not covered by the mask, and removing the mask after etching.

Abstract: The present invention is directed to a process for device fabrication in which a layer of cobalt silicide is formed as a low resistance contact layer over the source and drain regions of a device. The silicon substrate is first subjected to conditions that fore a thin layer of oxide on the surface thereof. It is advantageous if the oxide thickness is about 0.5 nm to about 1.5 nm. At least one layer of cobalt is then formed on at least the oxidized surfaces of the silicon substrate. The cobalt layer(s) is formed using conventional expedients such as e-beam evaporation. The cobalt layer(s) is formed on the substrate in an essentially oxygen free environment. Each cobalt layer has a thickness of about 1 nm to about 5 nm. While maintaining the substrate in the essentially oxygen-free environment, the substrate is annealed to form a layer of cobalt silicide. It is advantageous if the substrate is annealed at a temperature in the range of about 450.degree. C. to about 800.degree. C.

Abstract: A process for simultaneously forming a self-aligned contact, a local interconnect and a self-aligned silicide in a semiconductor device. An oxide layer is deposited over a gate structure, a source region and a drain region formed on a substrate of the semiconductor device. The gate structure may be a multi-layer structure including a polysilicon gate, a silicon nitride layer and a tungsten silicide layer. The oxide layer deposited over the gate, source and drain is etched to define portions of the oxide layer which will form contact areas of a self-aligned contact and a local interconnect of the semiconductor device. An amorphous silicon layer is then deposited over the etched oxide layer to a thickness selected such that substantially the entire thickness of remaining portions of the amorphous silicon layer will be consumed during a subsequent silicidation reaction.

Abstract: A method of manufacturing semiconductor interconnection includes the steps of providing a bottom conductive layer having an auxiliary conductive layer applied on top of the bottom conductive layer. The auxiliary conductive layer is patterned and subsequently a further conductive layer is applied over the patterned auxiliary conductive layer. A mask is then applied over the further conductive layer to form a pillar connection which provides a reliable connection in a semiconductor device.

Abstract: A method of forming metal lines such as titanium and aluminum on a semiconductor wafer by sputtering at a high temperature, preferably in the range of approximately 500.degree. C. to 800.degree. C. This method decreases the contact resistance between the layers while reducing the number of processing steps.

Abstract: An electrode wiring layer of a semiconductor device according to this invention includes a first conductive portion formed of polycrystalline silicon or the like, and second conductive portions formed as refractory metal silicide layers on opposite lateral walls of the first conductive portion. Upper surfaces and lateral surfaces thereof are coated with insulating layers formed in separate processes. The insulating layers covering the lateral surfaces in particular are formed by a self-aligning technique requiring no mask process. Where conductive layers are formed over the wiring layer according to this invention, a film forming and patterning process for insulating the conductive portions of the wiring layer is omitted and insulation of the wiring layer is secured.

Abstract: A method for producing an interconnect on a semiconductor device has silicon containing conductive surfaces and dielectric surfaces. The process includes forming separate regions of a blanket first refractory metal silicide on the silicon containing conductive surfaces, the first refractory metal silicide being composed of a first refractory metal and silicon from the surfaces, forming a blanket second refractory metal layer over the device, forming a blanket .alpha.-Si layer over the second refractory metal layer, forming a mask over the device to pattern an interconnect between the separate regions, then etching away the unwanted portions of the refractory metal layers and the .alpha.-Si layer, performing a rapid thermal annealing process on the device forming a low resistance refractory metal silicide between the .alpha.-Si layer and the second refractory metal layer, and then etching away the unwanted portions of the refractory metal layers that are not covered by the refractory metal silicide.