Abstract: A method for fabricating a semiconductor device includes forming a plurality of field oxide layers on a semiconductor substrate to define an active region; forming a plurality of gate electrodes each having sidewall spacers on the active region of the semiconductor substrate, depositing a metal layer on the semiconductor substrate including the plurality of gate electrodes, defining a first region and a second region, removing the metal layer over the second region, and forming a silicide layer on the gate electrode and on the semiconductor substrate over the first region with a first annealing process.

Abstract: A method of forming an interconnection within a high aspect ratio contact hole includes, forming a contact hole in an insulation film over a silicon substrate so that a diffusion layer, formed on a surface of the silicon substrate, is shown through the contact hole, removing spontaneous oxide film from a surface of the diffusion layer shown through the contact hole, heating at a temperature in the range of 350.degree. C. to 450.degree. C. the substrate to deposit a titanium film having a first thickness t1 by a collimated sputtering method, heating the substrate to deposit a titanium nitride film having a second thickness t2 by a collimated sputtering method, and heating the substrate to cause a titanium silicidation reaction at a boundary between the titanium film and the silicon diffusion layer thereby forming a titanium silicide film on the silicon diffusion layer at the bottom of the contact hole. Thereafter, a conductive film is formed which covers the titanium nitride film.

Abstract: A method of forming local interconnection of a SRAM, including the following steps: First, an NMOS and a PMOS are formed on a P-well and an N-well on a substrate, respectively. An isolation oxide layer is formed and the isolation oxide layer on a node is removed. A thin polysilicon layer is formed and N+ shallow implantation and N+ deep implantation is performed by using a photolithography technique. Also, P+ shallow implantation and P+ deep implantation are performed by using a photolithography technique. After the formation of a low resistance material, the low resistance material and the thin polysilicon layer are together formed.

Abstract: A process for fabricating bitlines for DRAM devices having improved bitline electrical contact is disclosed. Good electrical connection for the bitline in its contact opening is secured by forming a contact interface utilizing titanium silicide. The process includes first forming contact openings revealing the source/drain regions of the transistor of the cell units followed by the formation of a polysilicon layer filling into the openings and contacting the revealed surface of the transistor source/drain regions. A tungsten silicide layer then covers the polysilicon layer, with a titanium layer further covering the tungsten silicide layer, and the polysilicon layer in the contact opening exposed out of coverage by the tungsten silicide layer due to insufficient step coverage of the tungsten silicide layer in the openings. A titanium nitride layer then covers the titanium layer, with a titanium silicide layer interfacing between the polysilicon layer and the tungsten silicide filled inside the openings.

Abstract: Disclosed is a method for forming a silicide film on bit lines or word lines in a semiconductor device. The method includes the steps of: placing a substrate within a reacting chamber, the substrate having an objective layer on which a metal silicide film is to be formed; and supplying a first source gas for silicon component of the metal silicide and a second source gas for metal component of the metal silicide into the reacting chamber with maintaining a flow rate of the first source gas and with varying a flow rate of the second source gas, wherein the first and second source gases are discretely supplied into the reacting chamber, a reacting zone of the reacting chamber being maintained at a constant temperature range for a selected time.

Abstract: Titanium is deposited onto a semiconductor interconnect to form a salicide structure by plasma-enhanced chemical vapor deposition. The reactant gases, including titanium tetrachloride, hydrogen and optionally argon, are combined. A plasma is created using RF energy and the plasma contacts the rotating semiconductor material. This causes titanium to be deposited which reacts with exposed silicon to form titanium silicide without any subsequent anneal. Other titanium deposited on the surface, as well as titanium-rich silicon compositions (TiSi.sub.X wherein X is <2), are removed by chemical etching. If only about 40 .ANG. of titanium is deposited, it will selectively deposit onto the silicon structure without coating the oxide spacers of the interconnect. In this embodiment the need to chemically etch the substrate is eliminated.

Abstract: A method of reducing the loss of metal silicide in pre-metal etching which includes the following steps. A polysilicon gate electrode and implanted source/drain electrodes are formed on a silicon substrate. A metal silicide layer is formed on the polysilicon gate electrode and the source/drain electrodes. On the surface of the substrate, the polysilicon gate electrode, the source-drain electrodes region and the metal silicide layer, a protecting glass for insulation is formed and then dry etched to form a contact window. The metal silicide layer will form a damaged metal silicide layer in the contact window. Thereafter, a thermal process is conducted to repair the damaged metal silicide layer and finally, pre-metal etching is conducted completing the process. Pursuant to this method, the extremely low resistance of the metal silicide remains.

Abstract: A semiconductor structure that includes a silicon substrate which has a top surface, a diffusion region formed in the substrate adjacent to the top surface, a polysilicon gate formed on the top surface of the substrate adjacent to but not contacting the diffusion region, an insulator layer substantially covers the polysilicon gate and the diffusion region, the layer contains a via opening therein, and an electrically conducting plug filling at least partially the via opening providing electrical communication between the polysilicon gate and the diffusion region.

Abstract: A semiconductor device (150) is formed having a first conductive member (64) overlying a field isolation region (36) that is typically less than two microns wide. Typically, the field isolation region (36) is relatively thinner compared to wider field isolation regions. The first conductive member (64) lies between the field isolation region (36) and a second conductive member (80) to shield the substrate (20). The shielding helps to increase the field threshold voltage of the field device. The invention is particularly useful in double polysilicon process flow used in forming devices operating at a potential higher than V.sub.DD. Examples of these devices include nonvolatile memories and microcontrollers having nonvolatile memory arrays.

Abstract: A method of forming a silicide film composed of refractory metal in a certain region of a semiconductor device to be formed on a semiconductor substrate, includes the steps of (a) depositing a thin film composed of refractory metal on both a semiconductor substrate and a semiconductor device, (b) carrying out a first thermal annealing to the semiconductor substrate, semiconductor device, and refractory metal in depressurized or diluted gas atmosphere including nitrogen therein, and (c) carrying out a second thermal annealing to the semiconductor substrate, semiconductor device and refractory metal in argon gas atmosphere or high vacuum atmosphere. It is preferable that the second thermal annealing be carried out at higher temperature than the first thermal annealing. The method makes it possible to reduce a resistance of the silicide layer, and selectively form the silicide layer only on a gate electrode and a diffusion layer.

Abstract: A process for producing a layered structure in which a silicide layer on a silicon substrate is subjected to local oxidation to cause the boundary layer side of the silicide layer to grow into the silicon substrate.

Abstract: A semiconductor device and a fabrication method thereof are disclosed. A silicon nitride film is formed over a silicon semiconductor substrate. Impurity ions are then implanted into desired areas of the silicon semiconductor substrate, so that nitrogen atoms and silicon atoms from the silicon nitride film are incorporated into the surface of the silicon semiconductor substrate together with introduction of impurity ions. The silicon semiconductor substrate has a minimized content of oxygen mixed thereinto and restored crystal defects filled by nitrogen atoms upon implanting of impurity ions. The fabricated semiconductor device is free from a trade-off relation between gate-electrode depletion and junction current leakage, and short-channel effects.

Abstract: There is provided a method of fabricating a semiconductor device, including the steps of (a) forming impurity-diffused layers at a surface of a silicon semiconductor substrate in selected regions, (b) forming a refractory metal film over the impurity-diffused layers, (c) carrying out first thermal annealing in nitrogen atmosphere to convert the refractory metal film into a refractory metal silicide layer, (d) causing damage to a denaturated layer having been formed over the refractory metal film due to the first thermal annealing, (e) etching both the denaturated layer and non-reacted portions of the refractory metal film with a solution containing ammonia and hydrogen peroxide therein, and (f) carrying out second thermal annealing in nitrogen atmosphere to reduce resistance of the refractory metal silicide layer. For instance, the damage is caused to the denaturated layer by arsenic (As) ion implantation. The damage may be caused to the denaturated layer by exposing to oxygen plasma.

Abstract: Semiconductor devices may be made by forming a silicided layer on a silicon material such as that used to form the extractor of a field emission display. The silicided layer may be self-aligned with the emitter of a field emission display. If the silicided layer is treated at a temperature above 1000.degree. C. by exposure to a nitrogen source, the silicide is resistant to subsequent chemical attack such as that involved in a buffered oxide etching process.

Abstract: The present invention includes forming gate structures having a nitride cap on the substrate. An ion implantation is used to dope ions into the substrate to form the lightly doped drain (LDD) structures. An oxide layer is formed on the gate structures. Subsequently, the oxide layer is etched back to form oxide spacers on the side walls of the gate structures. Next, an ion implantation with a high dose is carried out to dope nitrogen ions into the oxide spacers, the cap silicon nitride and the silicon substrate. The cap silicon nitride layer is then removed. Then, a refractory or noble metal layer is sputtered on the substrate, nitride doped oxide spacers and the gates. A first step thermal process is performed to form SALICIDE and polycide. Next, an ion implantation is utilized to dope ions into the SALICIDE and polycide films. A second step thermal process is employed to form shallow source and drain junction.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

Abstract: A method of manufacturing a semiconductor component with a multi-level interconnect system includes providing a substrate (11), fabricating a device (12) in the substrate (11), forming an interconnect layer (15) over the substrate (11), depositing a dielectric layer (20) over the interconnect layer (15), depositing a separate interconnect layer (21) over the dielectric layer (20), etching a via (31) in the separate interconnect layer (21) and in the dielectric layer (20), and depositing a different interconnect layer (40) over the separate interconnect layer (21) and in the via (31) wherein the another interconnect layer (40) electrically couples the interconnect layer (15) and the separate interconnect layer (21).

Abstract: A method of forming a titanium silicide (69) includes the steps of forming a transistor having a source region (58), a drain region (60) and a gate structure (56) and forming a titanium layer (66) over the transistor. A first anneal is performed with a laser anneal at an energy level that causes the titanium layer (66) to react with the gate structure (56) to form a high resistivity titanium silicide phase (68) having substantially small grain sizes. The unreacted portions of the titanium layer (66) are removed and a second anneal is performed, thereby causing the high resistivity titanium silicide phase (68) to convert to a low resistivity titanium silicide phase (69). The small grain sizes obtained by the first anneal allow low resistivity titanium silicide phase (69) to be achieved at device geometries less than about 0.25 micron.

Abstract: A method for fabricating polycide contacts to semiconductor substrates, and more specifically for self-aligned contacts on substrates having field effect transistors (FETs) is achieved. After forming conventional FETs from a patterned first polysilicon layer provided with contact areas, an insulating layer is deposited. Self-aligned contact openings are etched in the insulating layer to the contact areas on the substrate, and a patterned polycide (second polysilicon/silicide) layer is used to form the electrical contacts and interconnections. However, in prior art when a photoresist mask and plasma etching are used to pattern a polycide layer, misalignment of the mask can result in notching in the sidewalls of the patterned second polysilicon layer resulting in contact damage and high leakage currents. The method of the present invention utilizes a critical pre-etch rapid thermal anneal (RTA) that essentially eliminates the notching during etching of these marginally misaligned contacts.

Abstract: A method of using titanium chloride to etchback CVD-Ti on a patterned oxide wafer and the product formed by this process. Titanium is deposited onto a wafer composed of a silicon base and a pattern oxide layer which exposes portions of the silicon. The titanium is deposited onto the wafer by CVD-Ti. The titanium is deposited as metallic Ti on the oxide layer and reacts with the silicon substrate to form titanium silicide. The wafer is then exposed to a flow of titanium tetrachloride (TiCl.sub.4) gas. The TiCl.sub.4 etches away the metallic Ti on the oxide layer and does not substantially etch the titanium silicide. Optionally titanium nitride and tungsten may then be deposited on the substrate.

Abstract: A method for forming metal plugs using fewer masks and photolithographic processes than a conventional one and therefore able to simplify the overall manufacturing processes and reduce cost. The steps are:providing a substrate having a polysilicon gate, a source/drain region and a spacer formed on the sidewall of the polysilicon gate;forming a self-aligned metal silicide layer above the substrate and covering the polysilicon gate as well as the surface of the source/drain region;forming a first dielectric layer above the substrate, and then a first conducting layer above the first dielectric layer;using a photolithographic process to define a pattern on the first conducting layer and then etching the first dielectric layer to a certain depth;forming a second dielectric layer above the substrate;etching the first dielectric layer and the second dielectric layer until the metal silicide layer is exposed so as to form contact windows in designated regions; andforming metal plugs inside the contact windows.

Abstract: A technology of forming a semiconductor integrated device is disclosed. According to the technology, titanium silicide is formed from an interaction between a source of TiCl.sub.2 transformed from TiCl.sub.4, and a source of hydrogen containing gas. The silicide layer includes a relatively planar interface with the gate electrode, the relatively planar interface being substantially free from gouges formed by a redistribution of a portion of the silicon atoms in the gate electrode.

Abstract: To provide a semiconductor device and a method of making a semiconductor device capable of preventing exfoliation at a pad electrode portion, a barrier metal layer 14, a silicon layer 15 and an aluminum layer 16 are formed on a side of a main face of a silicon substrate 11 (step A), the barrier metal layer 14, the silicon layer 15 and the aluminum layer 16 are patterned into a shape of a pad electrode (step B) and a silicide layer 17 is formed by an annealing treatment successive to the patterning step (step C).

Abstract: A microelectronic device (10) provides decreased use of bar area to form contacts between a conductive strap (24) or interconnect and subsequent levels. The conductive strap comprises a conducting layer (130) and an overlying semiconducting layer (132). Connection to subsequent levels is made generally overlying substrate conductive areas such as a gate (14) and/or a moat (16). Connection to conductive sublayer (130) is accomplished by doping an overlying semiconductor sublayer (132). Any counter-doping of substrate conductive areas is blocked by an overlying well of dopant-masking (33) or sufficiently thick semiconducting (32) material.

Abstract: A process for forming raised source/drain junctions using CMP (Chemical Mechanical Polishing) combined with a recess etch of blanket polysilicon. The raised source/drains are defined by gate conductors and by raised STI (Shallow Trench Isolation) which also reduces leakage current through the devices and improves the threshold voltage control. The process uses a salicide gate conductor, and uses conventional polysilicon deposition, CMP, and recess steps to form the raised source/drain junctions, such that it is readily implemented in commercially feasible manufacturing processes.

Abstract: A first metal silicide film is formed on an exposed silicon region of a substrate on which the silicon region and an insulating region are exposed. A metal film is deposited over the whole surface of the substrate covering the first metal silicide film, the metal film capable of being silicidized. A silicon film is deposited on the surface of the metal film. The silicon film and metal film are patterned to form a lamination pattern of the silicon film and metal film continuously extending from a partial area of the exposed silicon region to a partial area of the insulating region. The lamination pattern is heated to establish a silicidation reaction and form a second metal silicide layer.

Abstract: In order to provide a thermally stable diffusion barrier for a contact, a layer of titanium is formed on the patterned substrate. A layer of tungsten nitride is formed on the titanium layer. After an annealing step, an interfacial layer and a layer of titanium nitride are formed between the substrate and a tungsten layer. These layers provide a diffusion barrier which is more thermally stable than a titanium nitride layer applied directly on the substrate and permits the formation of a contact structures that can withstand subsequent high temperature steps.

Abstract: A process for fabricating metal plugs, such as aluminum plugs, in a semiconductor workpiece. The invention is suitable for filling narrow, high aspect ratio holes, and the invention minimizes the formation of TiAl3 or other products of interdiffusion between the plug and the wetting layer. First, an optional barrier layer is created by covering the bottom of a hole with a film containing titanium nitride doped with silicon. Second, a wetting layer is created by covering the side walls of a hole with a film containing titanium doped with silicon, in a Ti:Si molar ratio greater than 1:2. Preferably, the wetting layer is created by sputter deposition using a titanium sputtering target containing 0.1% to 20% wt silicon, most preferably 5% to 10% wt silicon. Third, the hole is filled by depositing a material consisting primarily of aluminum. The hole preferably is filled by sputter deposition using an aluminum sputtering target, optionally containing dopants such as copper.

Abstract: A method and an apparatus for making devices with low barrier height. In fabricating an n-channel and p-channel devices, hemisphere grains, silicon crystal grains and metal silicide crystal grains are formed on a contact-hole or a gate electrode on an insulating film in each semiconductor element, so that it becomes possible to control the work function, to reduce the contact resistance, and to control the threshold voltage V.sub.th.

Abstract: A static metal oxide semiconductor random access memory (SRAM) having NMOS and thin film transistors (TFTs) formed from a single polysilicon layer, and a method for forming the same. The SRAM cell comprises a plurality of NMOS transistors and TFTs that are interconnected by a local interconnect structure. The single layer of poly is used to define the TFT bodies and gates of NMOS transistors in the SRAM cell. Each TFT comprises a single polysilicon layer comprising source gate and drain regions. During the fabrication process, exposed portions of the TFT polysilicon body and exposed regions of NMOS transistors react with a refractory metal silicide to form polycide and silicide regions, respectively. An amorphous silicon pattern also reacts with the refractory metal silicide to form a local interconnect structure connecting the silicided portions of the thin film transistors and the MOS transistors.

Abstract: A method of forming a stacked capacitor of a DRAM. A number of doped polysilicon layers and a number of tungsten silicide layers are alternately formed. The doped polysilicon layers and the tungsten silicide layers are then patterned to form a lower electrode of the stacked capacitor. The doped polysilicon layers and the tungsten silicide layers are selectively etched to form a number of lateral trenches at the sidewall of the lower electrode so that the surface area of the lower electrode is increased. A dielectric layer is formed over the exposed surface of the doped polysilicon layers and the tungsten silicide layers. A conductive layer is formed on the dielectric layer as an upper electrode of the stacked capacitor so that the stacked capacitor is completed.

Abstract: A new method of forming an amorphous silicon glue layer in the formation of a contact is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer is deposited overlying the semiconductor device structures. An opening is etched through the insulating layer to contact one of the semiconductor device structures. An amorphous silicon layer is deposited overlying the insulating layer and within the opening. Ions are implanted into the amorphous silicon layer whereby grain sizes within the amorphous silicon layer are reduced. Native oxide on the surface of the amorphous silicon layer is removed. A titanium/titanium nitride layer is deposited overlying the amorphous silicon layer. A metal layer is deposited overlying the titanium/titanium nitride layer and filling the opening. The substrate is annealed whereby the titanium layer reacts with the amorphous silicon layer and the silicon semiconductor substrate to form titanium silicide.

Abstract: The invention provides a novel method, in which self-aligned, borderless contacts and local interconnections of semiconductor devices are manufactured in an integral process. The method is compatible with the LOGIC self-aligned titanium silicide (SALICIDE) and N+/P+ poly dual gate process modules. That is, this invention provides a self-aligned local-interconnect and contact (SALIC) method for a logic technology to forming the self-aligned, borderless contacts, and local interconnects (LI) simultaneously.

Abstract: Upon completion of a sputtering for a titanium layer, the titanium layer is taken out from the sputtering system, and a surface portion of the titanium layer is oxidized in the atmosphere; the titanium oxide layer is evaporated in fluoride gas atmosphere so as to prevent the titanium layer from the oxygen, and aggregation hardly takes place during silicidation of the titanium layer so that the titanium silicide layer is decreased in resistivity.

Abstract: A method for formation of both local innerconnection and silicidation of source/drain transistors using the deposition of a blanket silicon layer over the entire top surface of the transistors and selectively stripping of unwanted portions of the silicon layer is disclosed. The method includes the step of applying a photoresist mask to map out where the local interconnection and source/drain are to be located. The final recited step is to deposit a thin metal layer to provide for the silicidation to complete the transistor. The silicon layer that is deposited has a thickness of 20 to 300 millimeters, and the thin metal layer is either cobalt or titanium having a thickness of 10 millimeters to 100 millimeters.

Abstract: A self-aligned silicide method with Ti deposition, reaction, strip of TiN with selectivity to TiSi.sub.2 consisting of a water solution of H.sub.2 O.sub.2 with possible small amounts of NH.sub.4 OH, phase conversion anneal, and then strip of TiSi.sub.2 filaments with a water solution of H.sub.2 O.sub.2 plus NH.sub.4 OH.

Abstract: In order to form an ohmic contacts to both the n+ and the p+ doped regions of complementary metal oxide semiconductor substrate regions of the an integrated circuit device, wells (contact holes) are formed in the insulating using a hard mask poly-Si layer on an insulating region exposing the doped substrate regions. A TiSi.sub.x layer is formed on the walls and base of the well either by physical vapor deposition or is formed by combining a layer of poly-Si with a layer of Ti. The TiSi.sub.2 is diffused into the doped region during an annealing step. In addition, the TiSi.sub.2 layer is converted into the low resistivity C54 configuration in an annealing step.

Abstract: A method for lowering the anneal temperature required to form a multi-component material, such as refractory metal silicide. A shallow layer of titanium is implanted in the bottom of the contact area after the contact area is defined. Titanium is then deposited over the contact area and annealed, forming titanium silicide. A second embodiment comprises depositing titanium over a defined contact area. Silicon is then implanted in the deposited titanium layer and annealed, forming titanium silicide. A third embodiment comprises combining the methods of the first and second embodiments. In further embodiment, nitrogen, cobalt, cesium, hydrogen, fluorine, and denterium are also implanted at selected times.

Abstract: In a method of manufacturing a semiconductor device, a silicide layer of a refractory metal is formed in a predetermined region of a semiconductor element formed on a silicon semiconductor substrate. In the first film formation step, a first thin film consisting of the refractory metal is formed on the surfaces of the silicon semiconductor substrate and the semiconductor element. In the first heat treatment step, a heat treatment is performed with respect to the silicon semiconductor substrate, the semiconductor element, and the first thin film to form a silicide layer. In the first removal step, the first thin film is removed by etching. In the second film formation step, a second thin film consisting of a refractory metal of the same kind as that of the first thin film is formed.

Abstract: A method for fabricating SRAM polyloads that allows device dimension reduction yet maintains overall product functionality which includes the following steps: forming an insulating layer above a semiconductor substrate having a conductive gate device and a conductive voltage source line device already formed in it; etching the insulating layer selectively, and forming a first contact window and a second contact window on the surfaces of the conductive gate device and the conductive voltage source line device respectively; forming a polysilicon layer above the insulating layer, and filling up the first and the second contact windows at the same time; forming a silicide layer above the polysilicon layer; etching the silicide layer and the polysilicon layer to form a conductive wire linking the first contact window with the second contact window; and etching selectively section of the silicide layer on the conductive wire to expose the polysilicon layer below, and forming a polyload in the exposed polysilicon la

Abstract: A semiconductor processing method of providing a polysilicon film having induced outer surface roughness includes, a) providing a polysilicon layer over a substrate, the polysilicon layer having an outer surface of a first degree of roughness; b) providing a layer of a refractory metal silicide over the outer surface of the polysilicon layer, the refractory metal silicide preferably being WSi.sub.x where "x" is initially from 1.0 to 2.5, the WSi.sub.x layer and the polysilicon layer outer surface defining a first interface therebetween; c) annealing the substrate at a temperature and for a time period which are effective to transform the WSi.sub.x into a tetragonal crystalline structure and to transform the first interface into a different second interface, the WSi.sub.x layer not being in a tetragonal crystalline state prior to the anneal, the WSi.sub.x at the second interface having an increased value of "x" from the initial value of "x"; and d) etching the WSi.sub.

Abstract: A process which is capable of forming shallow source/drain regions in a silicon substrate and a doped gate electrode by implantation of cobalt silicide contacts of uniform thickness previously formed on the substrate followed by diffusion of the dopant into the substrate to form the desired source/drain regions, and into the polysilicon gate electrode to provide the desired conductivity is described.

Abstract: A method for forming within a Field Effect Transistor (FET) for use within an integrated circuit a polycide gate electrode. There is first provided a semiconductor substrate. Formed upon the semiconductor is a patterned polysilicon layer. Formed then upon the semiconductor substrate and the patterned polysilicon layer is a blanket insulator layer. The blanket insulator layer is then patterned through planarizing to form a patterned planarized insulator layer while simultaneously exposing the surface of the patterned polysilicon layer. Finally, there is formed upon the exposed surface of the patterned polysilicon layer a patterned metal silicide layer. The patterned metal silicide layer and the patterned polysilicon layer form a polycide gate electrode. The metal silicide layer within the polycide gate electrode is not susceptible to encroachment upon adjoining insulator spacers or source/drain regions within the Field Effect Transistor (FET) within which is formed the polycide gate electrode.

Abstract: A semiconductor processing method of making electrical connection between an electrically conductive line and a node location includes, a) forming an electrically conductive line over a substrate, the substrate having an outwardly exposed silicon containing node location to which electrical connection is to be made, the line having an outer portion and an inner portion, the inner portion laterally extending outward from the outer portion and having an outwardly exposed portion, the inner portion having a terminus adjacent the node location, and b) electrically connecting the extending inner portion with the node location. An integrated circuit is also described. The integrated circuit includes a semiconductor substrate, a node location on the substrate, and a conductive line over the substrate which is in electrical communication with the node location. The conductive line includes an outer portion and an inner portion.

Abstract: A method for preventing gate to source/drain bridging and reducing junction leakage by preventing defects in the source/drain region in the fabrication of a silicided polysilicon gate is described. A polysilicon gate electrode on a semiconductor substrate and associated source and drain regions within the semiconductor substrate are provided wherein spacers are formed on the sidewalls of the gate electrode. A layer of titanium is deposited over the gate electrode, spacers and source and drain regions within the semiconductor substrate. Arsenic ions are implanted into the titanium layer. The semiconductor substrate is annealed for a first time whereby the titanium layer is transformed into a titanium silicide layer except where the titanium layer overlies the spacers. The titanium layer overlying the spacers is stripped to leave the titanium silicide layer only on the top surface of the gate electrode and on the top surface of the semiconductor substrate overlying the source and drain regions.

Abstract: A self-aligned suicide SRAM load structure and its manufacturing method comprising the steps of providing a semiconductor substrate; then forming a first insulating layer over the substrate and etching an opening. Thereafter, a polysilicon layer is formed over the first insulating layer and the opening, and then a second insulating layer is formed over the polysilicon layer. Next, a photoresist layer for creating a connector pattern is formed over the second insulating layer using microlithographic processes. The second insulating layer is then etched to expose portions of the polysilicon layer. Subsequently, a metallic layer is deposited over the exposed polysilicon layer and the second insulating layer. Then, the metallic layer reacts with the polysilicon layer through heating until the two layers are completely converted into a metal silicide layer. The metal silicide layer functions as connectors, and the unreacted polysilicon layer beneath the second insulating layer functions as a polysilicon load.

Abstract: Integrated circuitry and a method of forming a contact landing pad are described. The method includes, in one embodiment, providing a substrate having a plurality of components which are disposed in spaced relation to one another; forming a silicon plug spanning between two adjacent components; forming a refractory metal layer over the silicon plug and at least one of the components; reacting the silicon plug and the refractory metal layer to form a silicide layer on the silicon plug; and after forming the silicide layer removing unreacted refractory metal layer material from the substrate.

Abstract: Disclosed is a low cost contact and interconnect layer and method for fabricating the same. A contact via is opened within an insulating layer, exposing a circuit node (e.g., transistor active area within a semiconductor substrate). The via is filled with a chemical vapor deposited (CVD) titanium silicide layer, forming electrical contact with the circuit node. The silicide layer may simultaneously form the interconnect layer for one embodiment. In other embodiments, the interconnect layer may comprise a metal strap over the titanium silicide layer, or a metal layer over an etched-back titanium silicide plug in the contact via. For any of these embodiments, the contact via may be opened after the formation of interconnect trenches, the via extending from the bottom of a trench to the circuit node. CVD provides good step coverage of the via within the trench, despite the higher aspect ratio. The interconnect layer is deposited and etched back, such that the interconnect lines are defined by the trenches.

Abstract: Undesirable counter doping of n.sup.+ /p.sup.+ gates illustratively through cross diffusion through an overlying silicide is inhibited by insertion of layers of titanium nitride and titanium, tungsten or tantalum between the polysilicon gates and an overlying silicide.

Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a first metal film including a first metal on a surface of a silicon film by sputtering using a gas mixture added with a nitrogen gas, the first metal being one of nickel and cobalt, and causing thermal reaction of the silicon film with the first metal film to form a silicide film of the first metal.