Abstract: Annealing technology is capable of heating a wafer on which a copper film is formed at a desired temperature within a short period of time. A light-shielding plate 106 of SiC (silicon carbide) exhibiting a flat emissivity irrespective of the wavelengths and emitting light over a wide band of wavelengths is interposed between the wafer 1 on which is formed a copper film having a high light reflection factor and lamps 102. The lamps 102 are turned on in this state so that the light-shielding plate 106 is heated, first, and, then, the wafer 1 is heated by light radiated from the light-shielding plate 106 that is heated, thereby to anneal the copper film.

Abstract: The present invention teaches a special annealing process to “heal” electrochemical copper deposited (ECD) defects in a dual damascene via and trench structure. The annealing step is processed after the electrochemical deposition (ECD) of the top excess copper and before the chemical mechanical polishing (CMP) of the copper. The key processing steps of this invention are the special annealing steps at key temperatures, ambient, pressures and times to anneal out the defective copper voids in the dual damascene structure. These annealing conditions are special annealing steps to promote low temperature copper surface diffusion to “heal” the voids and other defectives within the copper trench and via structure. The special annealing conditions of: temperature, ambient, pressure and time are the following: temperature in a range of about 300 to 500° C.

Abstract: A semiconductor device fabricating method includes a preparatory process that brings a first source gas containing tungsten atoms into contact with a workpiece and that does not bring a second source gas containing nitrogen atoms into contact with the workpiece, and a film forming process that forms a tungsten nitride film on the workpiece by using the first and the second source gases so as to fabricate a semiconductor device. The semiconductor device fabricating method is capable of preventing the tungsten nitride film from peeling off from a layer underlying the same when the tungsten nitride film is subjected to heat treatment.

Abstract: A method of manufacturing a contact plug in a semiconductor device is disclosed. In-situ thermal doping of an impurity such as phosphorous (P) during the process by which polysilicon for a contact plug is formed by selective growth method and after in-situ doping after the growth process is employed in order to increase the concentration of the impurity in the contact plug. As a result, the disclosed method can reduce the interfacial resistance at the plug to improve the electrical characteristics of a device of more than 1 G bits.

Abstract: Low resistance metal/semiconductor and metal/insulator contacts incorporate metal nanocrystals embedded in another metal having a different work function. The contacts are fabricated by placing a wetting layer of a first metal on a substrate, which may be a semiconductor or an insulator and then heating to form nanocrystals on the semiconductor or insulator surface. A second metal having a different work function than the first is then deposited on the surface so that the nanocrystals are embedded in the second material.

Abstract: Multilayer metal materials are selected so that the materials will alloy or intermix under rapid thermal annealing conditions. The individual materials of the multilayers are preferably chosen such that at least one of the materials may be selectively etched with respect to the other material by wet chemical or electrochemical etching. For electroplating applications, the alloyed plating base material will assume some of the etch resistance of the original electrodeposit material such that a selective wet etch of the plating base can be performed without substantial undercutting. Furthermore, the graded composition alloy will exhibit other advantageous physical and chemical properties for electrode formation and use. The alloying or intermixing may be accomplished before or after patterning of the materials, for the instance wherein the materials deposited as blanket layers.

Abstract: This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduce the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.

Abstract: A method of encapsulating metal lines (130, 132, 134, 136, 138) by implantation of dopants to form surface regions (131, 133, 135, 137, 139) after the metal lines have been fabricated. The surface regions may act as passivation layers and electromigration inhibitors and so forth.

Abstract: An interconnect opening of an integrated circuit is filled with a conductive fill, such as copper, with the interconnect opening being within an insulating layer on a semiconductor wafer. A seed layer of a first alloy is deposited conformally onto sidewalls and a bottom wall of the interconnect opening. The first alloy is comprised of a first metal dopant in a bulk conductive material. The first metal dopant has a relatively high solid solubility in the bulk conductive material, and the first metal dopant has a concentration in the bulk conductive material of the seed layer that is lower than the solid solubility of the first metal dopant in the bulk conductive material.

Abstract: A copper metallization structure and its method of formation in which a layer of a copper alloy, such as Cu—Mg or Cu—Al is deposited over a silicon oxide based dielectric layer and a substantially pure copper layer is deposited over the copper alloy layer. The copper alloy layer serves as a seed or wetting layer for subsequent filling of via holes and trenches with substantially pure copper. Preferably, the copper alloy is deposited cold in a sputter process, but, during the deposition of the pure copper layer or afterwards in a separate annealing step, the temperature is raised sufficiently high to cause the alloying element of the copper alloy to migrate to the dielectric layer and form a barrier there against diffusion of copper into and through the dielectric layer. This barrier also promotes adhesion of the alloy layer to the dielectric layer, thereby forming a superior wetting and seed layer for subsequent copper full-fill techniques.

Abstract: A method of fabricating a Ti-containing liner having good contact resistance and coverage of a contact hole is provided. The method which converts an amorphous region of ionized metal plasma deposited Ti into a substantially crystalline region includes (a) providing a structure having at least one contact hole formed therein, said at least one contact hole exposing at least a portion of a cobalt disilicide contact formed in a semiconductor substrate; (b) depositing a Ti/TiN liner in said at least one contact hole by ionized metal plasma deposition; (c) annealing said Ti/TiN liner under conditions effective to recrystallize any amorphous region formed during said annealing into a crystalline region including a TiSi2 top layer and a CoSix bottom layer; and (d) optionally forming a conductive material on said Ti/TiN liner.

Abstract: An electrode structure for a semiconductor device and a method for forming the electrode structure, and a mounted body including the semiconductor device are provided in which the semiconductor device can be easily connected to a circuit board with high reliability. An aluminum electrode is formed on an IC substrate. A passivation film is formed on the IC substrate so as to cover the peripheral portion of the aluminum electrode. A bump electrode is formed on the aluminum electrode by a wire bonding method. An aluminum oxide film is formed on the surface of the aluminum electrode that is exposed around the bump electrode. A conductive adhesive is applied as a bonding layer to the tip portion of the bump electrode of the semiconductor device by a transfer method or a printing method. The semiconductor device is aligned in the face-down state in such a manner that the bump electrode abuts on a terminal electrode of a circuit board, and is provided on a circuit board.

Abstract: This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduce the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.

Abstract: A method for improving surface wettability of inorganic low dielectric material is disclosed. The method includes an inorganic dielectric material as a low-k dielectric barrier layer is spun-on the semiconductor device. Then, inorganic dielectric material surface is treated by ultraviolet (UV) treatment that the surface characteristic of inorganic dielectric material is changed from hydrophobic to hydrophilic. Thus, the surface wettability of inorganic dielectric material can be improved and adhesion ability between the inorganic dielectric material and organic polymer can be increased.

Abstract: A process for fabricating a semiconductor device with copper interconnects is disclosed. In the process of the present invention, a layer of dielectric material is formed on a substrate. A barrier layer to prevent copper diffusion is then deposited over the entire surface of the substrate. A dual copper layer is formed on the barrier layer. The dual layer has a copper layer deposited by PVD and a copper layer deposited by electroplating. The copper layers are adjacent to each other. The ratio of the thickness (X) of the electroplated, layer to the thickness of the PVD layer (Y) is about 1:0.5 to about 1:2. The thickness of the electroplated layer is at least about 3 &mgr;m. The thickness of the PVD copper layer is at least about 100 nm. The thickness of the two layers is selected to effect recrystallization of the electroplated copper from a small grain size (0.1 &mgr;m to 0.2 &mgr;m) to a large grain size (1 &mgr;m or greater).

Abstract: A method for manufacturing a substrate with an oxide ferroelectric thin film formed thereon includes the steps of forming an electrode on a substrate, prebaking the substrate with the electrode formed thereon and forming an oxide ferroelectric thin film on the resultant electrode.

Abstract: A silicide process using a pre-anneal amorphization implant prior to silicide anneal. A layer of titanium is deposited and reacted to form titanium silicide (32) and titanium nitride. The titanium nitride is removed and a pre-anneal amorphization implant is performed to enable increased transformation of the silicide (32) from a higher resistivity phase to a lower resistivity phase. A heavy dopant species (40) is used for the pre-anneal amorphization implant such as arsenic, antimony, or germanium. After the implant, the silicide anneal is performed to accomplish the transformation. An advantage of the invention is providing a silicide process having reduced silicide sheet resistance for narrow polysilicon lines.

Abstract: The present invention provides methods of producing an anti-reflective layer on a semiconductor wafer/device and wafers/devices including that anti-reflective layer. The anti-reflective layer is produced by annealing layers of titanium and aluminum on a wafer/device to provide a roughened surface that significantly reduces reflectivity to improve the accuracy and definition provided by optical lithography processes.

Abstract: The present invention provides a manufacturing method of a semiconductor device which does not give rise to peeling of a metal film caused by oxygen held in a interlayer insulating film even when the wafer is subjected to a heat treatment after the metal film is formed on the interlayer insulating film. After the formation of the interlayer insulating film, oxygen held in the interlayer insulating film is removed from the interlayer insulating film, then a metal film on the interlayer insulating film.

Abstract: Shorting between a transistor gate electrode and associated source/drain regions due to metal silicide formation on the sidewall spacers is prevented by passivating the sidewall spacer surfaces with a solution of iodine and ethanol. Embodiments of the invention include spraying the wafer with or immersing the wafer in, a solution of iodine in ethanol.

Abstract: A process used during the formation of a semiconductor device comprises the steps of placing a plurality of semiconductor wafers each having a surface into a chamber of a batch wafer processor such as a diffusion furnace. The wafers are heated to a temperature of between about 300° C. and about 550° C. With the wafers in the chamber, at least one of ammonia and hydrazine is introduced into the chamber, then a precursor comprising trimethylethylenediamine tris(dimethylamino)titanium and/or triethylaluminum is introduced into the chamber. In the chamber, a layer comprising aluminum nitride is simultaneously formed over the surface of each wafer. The inventive process allows for the formation of aluminum nitride or titanium aluminum nitride over the surface of a plurality of wafers simultaneously. A subsequent anneal of the aluminum nitride layer or the titanium aluminum nitride layer can be performed in situ.

Abstract: A method and apparatus for selectively depositing hemispherical grained silicon on the surface of a wafer in a process chamber. The chamber is evacuated so that a partial pressure of water vapor in the chamber is less than 10−7 torr, preferably using a turbomolecular pump and a water vapor pump in cooperation. A process gas mixture including silicon is introduced into the chamber. The surface of the wafer is seeded with silicon nuclei, and the wafer is annealed to convert the silicon to HSG.

Abstract: A thermal processing method is described which improves integrated circuit metal polishing and increases conductivity following polish. A method of fabricating a metal layer in an integrated circuit is described which comprises the steps of depositing a layer of metal alloy which contains alloy dopant precipitates, and performing a first anneal of the integrated circuit to drive the alloy dopants into solid solution. The metal is quenched to prevent the alloy dopants from coming out of solution prior to removing excess metal alloy with a polish process. To improve conductivity after polishing, the dopants are allowed to come out of solution. The metal alloy is described as aluminum with alloy dopants of silicon and copper where the first anneal is performed at 400 to 500° C. This process is particularly applicable to fabrication of interconnects formed using a dual damascene process. The integrated circuit is described as any circuit, but can be a memory device such as a DRAM.

Abstract: A semiconductor device having a gate and a fabrication method therefor is disclosed, which can improve a thermal stability, has a low resistance, and assure an easy fabrication process. The fabrication method includes the steps of (1) forming a first insulating film and a conductive film on a semiconductor substrate, (2) patterning the first insulating film and a conductive film on a semiconductor substrate, (2) patterning the first insulating film and the conductive film, to form a gate, (3) forming a second insulating film thicker than the gate on an entire surface, (4) planarizing the second insulating film, to expose the gate, (5) depositing a refractory metal layer on an entire surface, (6 ) forming a silicide layer on an upper surface of the gate by heat treatment, and (7) etching the refractory metal layer and the second insulating film.

Abstract: A method of reducing electromigration in Cu interconnect lines by forming an interim layer of Ca-doped copper seed layer lining a via in a chemical solution and a semi conductor device thereby formed. The method reduces the drift velocity which then decreases the Cu migration rate in addition to void formation rate.

Abstract: A capacitor of a semiconductor device is provided which includes a semiconductor substrate, an insulating interlayer formed on the semiconductor substrate, the insulating interlayer having a contact hole which exposes a predetermined portion of the semiconductor substrate, a plug filled in the contact hole, the plug coming into contact with the semiconductor substrate, a contact layer formed on the insulating interlayer, the contact layer coming into contact with the plug, first and second barrier layers formed on the surface and sides of the contact layer, a lower electrode formed on the first barrier layer, a dielectric layer formed on the second barrier layer and lower electrode, and a upper electrode formed on the dielectric layer.

Abstract: This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduce the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.

Abstract: A semiconductor device is manufactured by a method including the steps of forming a through hole in an interlayer dielectric layer (silicon oxide layer, BPSG layer, etc.) formed on a semiconductor substrate having a device element. A barrier layer is formed on surfaces of the interlayer dielectric layer and the through hole. A wiring layer is formed on the barrier layer. The barrier layer is formed by a method including the following steps. A titanium layer that forms at least a part of the barrier layer is formed. A heat treatment is conducted in a nitrogen atmosphere to form a titanium nitride layer at least on a surface of the titanium layer. The titanium nitride layer is contacted with oxygen in an atmosphere including oxygen. A heat treatment is conducted in a nitrogen atmosphere to form titanium oxide layers and to densify the titanium nitride layer.

Abstract: A method for filling recessed micro-structures at a surface of a semiconductor wafer with metallization is set forth. In accordance with the method, a metal layer is deposited into the micro-structures with a process, such as an electroplating process, that generates metal grains that are sufficiently small so as to substantially fill the recessed micro-structures. The deposited metal is subsequently subjected to an annealing process at a temperature below about 100 degrees Celsius, and may even take place at ambient room temperature to allow grain growth which provides optimal electrical properties.

Abstract: A method for fabricating a titanium silicide film in which when a titanium silicide film is fabricated by using a Chemical Vapor Deposition, an NH3-gas plasma process or an N2-gas plasma process is conducted for several times to minimize etching of the silicon substrate and consumption of a dopant of an impurity layer, thereby restraining a leakage current from increasing. The method for fabricating a titanium silicide film includes the steps of: (a) depositing a titanium silicide film as thick as {fraction (1/n)} of a total desired thickness on a silicon substrate by using the Chemical Vapor Deposition method; (b) processing the titanium silicide film with a nitrogen-gas plasma or ammonia-gas plasma; and (c) repeatedly performing step (a) and step (b) n times.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. After planarization of the conductor core and the barrier layer, a plasma treatment is performed at 300° C. to reduce the conductor core material. A portion of a cap layer is deposited at 300° C. and the remainder is deposited at 400° C.

Abstract: IC fabrication employs the deposition of aluminum as a metallization layer. Frequently, the aluminum is doped with copper in small amounts to improve electric properties. Low temperature deposition of these layers is preferred to ensure the proper microstructure and surface roughness. Low temperature deposition (below about 300° C.) results in the formation of copper precipitates which can be difficult to remove. Annealing the layer formed, either prior to, or after formation of capping layers and additional layers thereon, drives the copper precipitate back into solution, permitting small dimension fabrication.

Abstract: A process for forming a conducting structure layer that can reduce metal etching residues, in which a pre in-situ metal layer is added before a metal layer is deposited. The pre in-situ metal layer enables the crystalloid of the metal layer to grow more 5 evenly, and thus reduces the etching residues of the conducting structure layer. A structure of a conducting structure layer is also provided.

Abstract: A TiN film is selectively formed as a barrier layer on a Cu metal layer by selective removal of a Ti metal layer on the Si metal layer after the following steps of selectively forming a Si metal layer as an etching mask on an insulation film, forming a trench pattern by selective removal of the insulation film using the Si metal layer, forming a Cu metal layer in the trench pattern with the Si metal layer remained, forming the Ti metal layer on the Si metal layer and the Cu metal layer as a barrier material with a different kind of eutectic reaction with Cu from the reaction with the etching mask by heat-treatment in an atmosphere of nitrogen, and selectively nitriding the Ti metal layer on the Cu metal layer by heat-treatment of the Ti metal layer in an atmosphere of nitrogen.

Abstract: A thermal processing method is described which improves integrated circuit metal polishing and increases conductivity following polish. A method of fabricating a metal layer in an integrated circuit is described which comprises the steps of depositing a layer of metal alloy which contains alloy dopant precipitates, and performing a first anneal of the integrated circuit to drive the alloy dopants into solid solution. The metal is quenched to prevent the alloy dopants from coming out of solution prior to removing excess metal alloy with a polish process. To improve conductivity after polishing, the dopants are allowed to come out of solution. The metal alloy is described as aluminum with alloy dopants of silicon and copper where the first anneal is performed at 400 to 500° C. This process is particularly applicable to fabrication of interconnects formed using a dual damascene process. The integrated circuit is described as any circuit, but can be a memory device such as a DRAM.

Abstract: The formation of microelectronic structures in trenches and vias of an integrated circuit wafer are described using nanocrystal solutions. A nanocrystal solution is applied to flood the wafer surface. The solvent penetrates the trench recesses within the wafer surface. In the process, nanocrystals dissolved or suspended in the solution are carried into these regions. The solvent volatilizes more quickly from the wafer plateaus as compared to the recesses causing the nanocrystals to become concentrated in the shrinking solvent pools within the recesses. The nanocrystals become stranded in the dry trenches. Heating the wafer to a temperature sufficient to sinter or melt the nanocrystals results in the formation of bulk polycrystalline domains. Heating is also carried out concurrently with nanocrystals solution deposition. Copper nanocrystals of less than about 5 nanometers are particularly well suited for formation of interconnects at temperatures of less than 350 degrees Celsius.

Abstract: A method for increasing the production yield of semiconductor devices having copper metallurgy planarized by a chemical-mechanical planarization process which includes a slurry that contains a conductor passivating agent, like benzotriazole, wherein a non-oxidizing anneal is used to remove any residue which might interfere with mechanical probing of conductive lands on the substrate prior to further metallization steps. The anneal may be performed by any of several techniques including a vacuum chamber, a standard furnace or by rapid thermal annealing.

Abstract: A method of manufacturing a silicon single crystal to be grown by the Czochralski method, wherein a crystal is pulled up in a CZ furnace by changing an average pulling rate for a crystal, having a predetermined length, a plurality of times, a relation between the average pulling rate and the OSF ring diameter for each pulling length is examined, an average pulling rate pattern for generation or disappearance of an OSF ring at a predetermined position is designed based on the examined results, and the single crystal is grown according to the average pulling rate pattern, and a silicon wafer not having grown-in defects is manufactured.

Abstract: An amorphous silicon film is deposited on a quartz substrate, and a metal of Ni is introduced into the amorphous silicon film so that the amorphous silicon film is crystallized. Phosphorus is ion-implanted with an oxide pattern used as a mask. A heating process is performed in a nitrogen atmosphere, by which Ni is gettered. A heating process is performed in an O2 atmosphere, by which Ni is gettered into the oxide. Like this, by performing the first gettering in a non-oxidative atmosphere, the Ni concentration can be reduced to such a level that oxidation does not cause any increase of irregularities or occurrence of pinholes. Thus, in a second gettering, enough oxidation can be effected without minding any increase of irregularities and occurrence of pinholes, so that the Ni concentration can be reduced to an extremely low level. Also, a high-quality crystalline silicon film free from surface irregularities and pinholes can be obtained.

Abstract: The present invention provides a method of carrying out a hydrogen anneal to a substrate having an interface between different materials provided that an annealing temperature is maintained higher than a hydrogen-eliminating initiation temperature, wherein a temperature of a furnace is controlled to be not higher than the hydrogen-eliminating initiation temperature until the substrate is taken out from the furnace after the hydrogen anneal is carried out.

Abstract: A method of minimizing the volume of the depressions 240 in aluminum cavity filling processes, by-depositing a conformal first layer of aluminum alloy 220 by chemical vapor deposition, long-throw sputtering, collimated sputtering, or ionized physical vapor deposition, to partially fill the cavity 202. This layer is preferably deposited at low temperature (eg. less than 300 degrees C.) and lower deposition pressure (if deposited by sputtering). Subsequently, a second layer of aluminum alloy 230 is deposited by sputtering at temperatures greater than 350 degrees C. and at high power (e.g. greater than 10 kW) to close the mouth of cavity 202. The second layer of aluminum 230 is then forced into the remaining volume of the cavity 202. As part of the cavity 202 is filled with aluminum, alloy 220 before the high pressure aluminum extrusion/reflow, less material is required to be transported into the cavity 202. Therefore, a smaller depression 240 above the cavity is produced.

Abstract: A method for forming a titanium nitride film of an excellent quality on a semiconductor substrate at a low temperature is achieved. With a heated semiconductor substrate on a susceptor held at a temperature of about 500° C., titanium tetrachloride and ammonia are introduced into a reactor to carry out the deposition of the titanium nitride film. After the deposition is completed, the semiconductor substrate within the reactor is continuously held at a temperature of 500° C. After a low pressure mercury lamp is turned on, while the inner part of the reactor is irradiated with ultraviolet rays with a wavelength of 170-280 nm emitted from the lamp, an ammonia gas is introduced, with the flow rate adjusted to about 1000 sccm, into the reactor held at a pressure of about 10 Torr to carry out annealing in an ammonia atmosphere for about 60 seconds.

Abstract: An active matrix type liquid crystal display, in which the reliability is enhanced by preventing the short-circuit and insulation breakdown of a gate insulating portion and the delay time of a gate bus line is shortened by reducing the resistivity of an interconnect film. The liquid crystal display of this type is manufactured by the steps of forming an interconnect/electrode film on a substrate by physical deposition; patterning the interconnect/electrode film; and anodic-oxidizing part or all of the interconnect/electrode film. In this method, the interconnect/electrode film is formed of an Al alloy containing at least one kind selected from a group consisting Fe, Co and rare earth elements in an amount of 0.1 to 10 at %; and the thickness of the anodic oxidation film is specified to be in the range of 200 Å or more.

Abstract: A contact between a polycrystalline silicon structure and a monocrystalline silicon region is produced by doping the silicon structure in amorphous or polycrystalline form and/or doping the monocrystalline silicon region with a dopant, in particular with oxygen, in such a concentration that a solubility limit is exceeded. In a subsequent heat treatment, dopant precipitations are formed which either control grain growth in the polycrystalline silicon layer or prevent a propagation of crystal faults into a substrate in the monocrystalline silicon region. Such a contact can be used, in particular, as a buried strap in a DRAM trench cell.

Abstract: A method of fabricating a self-align-contact is provided. A first gate and a second gate are formed on a semiconductor substrate. A spacer is formed on the sidewalls of the first gate and the second gate, and a source/drain region is formed between the first gate and the second gate. A dielectric layer is formed on the first gate, the second gate, the source/drain region, the spacer, and the semiconductor substrate. A self-align-contact opening is formed in the dielectric layer to expose the source/drain region. A metal silicide layer is formed on the source/drain region. A first conductive layer, such as doped polysilicon, is formed on the metal silicide layer and in the self-align-contact opening. A second conductive layer is formed on the first conductive layer, and the first conductive layer and the second conductive layer are patterned.

Abstract: There is provided a semiconductor device fabrication method. In the method, a gate layer is formed on a semiconductor substrate and patterned to form a first resultant structure, a metal layer is formed on the first resultant structure, a capping layer is formed on the metal layer, a metal silicide is formed on the gate layer by heating the substrate at a first temperature, unreacted metal layer and first capping layer are removed to form a second resultant structure, a second capping layer is formed on the second resultant structure, and the substrate is heated at a second temperature higher than the first temperature. The second capping layer suppresses a silicidation rate in the secondary heat treatment, thereby allowing a silicide of a good morphology to be achieved.

Abstract: In a method for producing an integrated circuit using a CMOS process, in particular a HV CMOS process, components are formed within troughs of different depths and of a first conductivity type, in particular N-type troughs, which are formed in a substrate layer of a second conductivity type opposite to the first conductivity type, in particular a P-type substrate. Further, a SOI wafer substrate is used that comprises a top substrate layer for forming the CMOS components, a lateral insulation layer provided beneath the substrate layer, and a support layer arranged beneath the insulation layer. The top substrate layer has a thickness less than or equal to the greatest trough depth of the CMOS process.

Abstract: First, a trench of a semiconductor substrate is filled with a polysilicon film deposited on the surface of the semiconductor substrate. A selective thin film having etching selectivity with respect to the polysilicon film is formed on the polysilicon film. Then, the selective thin film is etched (etched back) so that a part of the selective thin film remains in a depression of the polysilicon film, as a self-aligning mask. The polysilicon film is further etched with the self-aligning mask, thereby forming a polysilicon embedded layer in the trench with a flat surface.

Abstract: A method of forming an intact wiring film by applying a filling treatment with a metal material with no pores to holes/trenches, the method comprising forming a barrier layer 3 to an insulation film 2 having holes/trenches 2A, forming a seed layer by a PVD method on the surface of the barrier layer and laminating a wiring film 5A by a electrolytic plating method and heat treating the same under a high temperature/high pressure gas atmosphere.

Abstract: Sintering is effected a gate insulating film of a transistor in a hydrogen atmosphere at a temperature from 450° C. to 600° C. only before formation of an interconnection layer such as an aluminum interconnection layer which is less resistant to heat treatment at a temperature of 450° C. or more. Thereby, a method of manufacturing a semiconductor device can bring about sufficient recovery of a gate insulating film from process damages and others while preventing an adverse effect on the interconnection layer less resistant to the heat treatment at a high temperature.