Abstract: An aluminum sputtering process, particularly useful for filling vias and contacts of high aspect ratios formed through a dielectric layer and also usefull for forming interconnects that are highly resistant to electromigration. A liner or barrier layer is first deposited by a high-density plasma (HDP) physical vapor deposition (PVD, also called sputtering) process, such as is done with an inductively coupled plasma. If a contact is connected at its bottom to a silicon element, the first sublayer of the liner layer is a Ti layer, which is silicided to the silicon substrate. The second sublayer comprises TiN, which not only acts as a barrier against the migration of undesirable components into the underlying silicon but also when deposited with an HDP process and biased wafer forms a dense, smooth crystal structure. The third sublayer comprises Ti and preferably is graded from TiN to Ti. Over the liner layer, an aluminum layer is deposited in a standard, non-HDP process.

Abstract: An interconnect (60) is formed overlying a substrate (10). In one embodiment, an adhesion/barrier layer (81), a copper-alloy seed layer (42), and a copper film (43) are deposited overlying the substrate (10), and the substrate (10) is annealed. In an alternate embodiment, a copper film is deposited over the substrate, and the copper film is annealed. In yet another embodiment, an adhesion/barrier layer (81), a seed layer (82), a conductive film (83), and a copper-alloy capping film (84) are deposited over the substrate (10) to form an interconnect (92). The deposition and annealing steps can be performed on a common processing platform.

Abstract: Copper is the bulk interconnect metal in the manufacture of an integrated circuit in accordance with the damascene process. When copper is exposed through via apertures, carbon monoxide and hydrogen are used as reduction agents to convert black copper oxide to red copper oxide and the red copper oxide to copper. The integrated circuit is then transferred in a high vacuum to a sputter chamber so that re-oxidation does not occur before tantalum barrier metal can be deposited. As a result, a good tantalum-copper electrical contact can be made without risking embedding copper in oxide sidewalls (whence it could migrate to active circuit regions and impair device reliability).

Abstract: Cu interconnection patterns with improved electromigration resistance are formed by depositing a barrier metal layer, such as W or WN, to line an opening in a dielectric layer. The exposed surface of the deposited barrier metal layer is treated with silane or dichlorosaline to form a thin silicon layer thereon. Cu is then deposited to fill the opening and reacted with the thin silicon layer to form a thin layer of Cu silicide at the interface between Cu and the barrier metal layer, thereby reducing the interface defect density and improving electromigration resistance.

Abstract: A method of fabricating an integrated circuit includes forming a gate stack upon an active region of a substrate which includes a gate dielectric, a polysilicon gate conductor and a polysilicon consumption metal layer portion. The polysilicon consumption metal layer portion is then reacted with the polysilicon gate conductor to form a high conductivity gate conductor (silicide). In one embodiment, the polysilicon gate conductor is fully consumed. In another embodiment, the polysilicon gate conductor is substantially consumed but a portion of the polysilicon gate conductor adjacent the gate dielectric remains. In forming such a gate structure, a gate dielectric layer is first formed and a polysilicon gate layer is formed upon the gate dielectric layer. A polysilicon consumption metal layer is then formed upon the polysilicon gate layer. The surface is then patterned mask so that the location of the gate structures is protected. The substrate is then anisotropically etched to form the gate structures.

Abstract: A method for reducing salicide lateral growth. A substrate having a gate structure and an anti-reflection layer on the gate structure is provided. A spacer is formed on the side wall of the gate structure and the anti-reflection layer. Then, the anti-reflection layer is removed to expose the gate structure; wherein the gate structure and the spacers together form a recess structure. A salicide layer is formed on the gate structure in the recess structure and on the substrate.

Abstract: Methods of fabricating a silicide layer on a substrate or transistor structures thereon are provided. An exemplary method includes the steps of depositing a layer of metal on a substrate that has a pn junction. The metal layer and the substrate are heated to react the metal with the substrate and form the silicide layer. Any unreacted metal is removed. The substrate and the silicide layer are heated above the agglomeration threshold temperature of any filaments of the silicide layer penetrating the pn junction but below the agglomeration threshold temperature of the silicide layer. The method eliminates silicide filaments, particularly in cobalt silicide processing, that can otherwise penetrate the pn junction of a transistor source/drain region a lead to reverse-bias diode-leakage currents.

Abstract: A cost-effective method for fabricating MIM capacitors (120). After metal (106) deposition, the metal oxide (108) is formed using an oxidation chemistry that includes CO2 and H2. The CO2/H2 gas ratio is controlled for selective oxidation. Thus, the metal (106) is effectively protected from oxidation due to the existence of both H2 and CO2 as strong reduction reagent.

Abstract: A method of controlling stresses in thin films that are deposited over semiconductor device substrates. During anneal process steps, grain growth of the film creates stresses in that can damage or destroy it. The stresses lead to warping and bowing and ultimately to film cracking which undermines desired low resistivity. The present invention imparts thermal stability to thin films by grain boundary stuffing (GBS) of preselected elements that resist film grain changes that cause the stresses. GBS implants the elements into the thin film at desired depths, but above the film-substrate interface, sufficient to prevent or lessen destructive grain growth. GBS provides for structural film stability required during severe thermal cycles that occur during subsequent processing of semiconductor devices.

Abstract: A method of depositing a platinum based metal film by CVD deposition includes bubbling a non-reactive gas through an organic platinum based metal precursor to facilitate transport of precursor vapor to the chamber. The platinum based film is deposited onto a non-silicon bearing substrate in a CVD deposition chamber in the presence of ultraviolet light at a predetermined temperature and under a predetermined pressure. The film is then annealed in an oxygen atmosphere at a sufficiently low temperature to avoid oxidation of substrate. The resulting film is free of silicide and consistently smooth and has good step coverage.

Abstract: A process is disclosed for manufacturing a film that is a smooth and has large nitride grains of a diffusion barrier material selected from a group consisting of tungsten alloys of Group III and Group IV early transition metals and molybdenum alloys of Group III and Group IV early transition metals. The diffusion barrier material is preferably selected from a group consisting of ScyMz, ZryMz, ZrvScyMz, ZrvNbyMz, ZruScvNbyMz, NbyMz, NbvScyMz, TiyMz, TivScyMz, TivNbyMz, and TivZryMz, where M is one of tungsten and molybdenum. Under the process, a nitride of the diffusion barrier material is deposited by physical vapor deposition in an environment of nitrogen.

Abstract: A substrate which has been heated to a predetermined temperature by a heating unit during sputtering is transferred into an unload-lock chamber having a vacuum pump system and a vent gas introducing system. The unload-lock chamber is provided with a cooling stage which makes surface contact with the substrate so as to forcedly cool the substrate to a predetermined temperature. The substrate is placed on the cooling stage and forcedly cooled. After the substrate is cooled to the predetermined temperature or lower, the vent gas introducing system is operated so that the interior of the unload-lock chamber is returned to the atmospheric pressure ambient. Since the substrate under a high temperature condition does not make contact with the atmospheric pressure ambient, film properties are prevented from being varied.

Abstract: The present invention relates to high aspect-ratio electrical connections, wiring trenches, and methods of forming the same in semiconductor devices. In particular, the present invention relates to formation of contacts with refractory metal and/or refractory metal nitride liners that assist in filling of the contacts. Additionally disclosed is the combination of shallow junction fabrication and high aspect-ratio contact formation to form contacts between a shallow junction and microcircuitry wiring. More particularly, the present invention relates to aluminum filled contacts that fill contact corridors, trenches, or vias in semiconductor devices that are initially lined with a titanium layer and at least one other layer. Preferred other layers include CVD, PVD, or reacted TiN, Co, Ge, and Si.

Abstract: A liner material and method of use is disclosed. The method includes depositing a silicon layer into a deep void, such as a via or trench, and physical vapor depositing a cobalt seed layer onto the silicon. A supplemental cobalt layer is electroplated over the seed layer. The structure is then annealed, forming cobalt silicide (CoSix). The layer can be made very thin, facilitating further filling the via with highly conductive metals. Advantageously, the layer is devoid of oxygen and nitrogen, and thus allows low temperature metal reflows in filling the via. The liner material has particular utility in a variety of integrated circuit metallization processes, such as damascene and dual damascene processes.

Abstract: In a method for manufacturing a semiconductor device, a first insulating layer is formed on a semiconductor substrate, and a gate electrode is formed on the first insulating layer. Then, a second insulating layer is formed over the gate electrode. The second insulating layer has a high ability to stop the diffusion of hydrogen atoms therethrough. Then, hydrogen passivation is performed upon an interface between the semiconductor substrate and the first insulating layer at a first temperature. Then, a metal wiring layer is formed over the insulating layer, and the metal wiring layer is heated at a second temperature lower than the first temperature.

Abstract: Provided a process for producing a refractory metal by chemical vapor deposition of a bilayer-stacked tungsten metal by depositing a bilayer-stacked tungsten metal in a same chamber in the manner of not breaking the vacuum therein. Firstly, a layer of amorphous-like tungsten is deposited to increase thermal stability and to prevent diffusion of fluorine atom. Next, a nitridizing treatment is performed thereon to promote further the barrier property and thermal stability of the amorphous-like tungsten. Finally, conventional selective chemical vapor deposited tungsten having low is deposited on the amorphous-like tungsten. Through the deposition of bilayer tungsten according to the process of the invention, thermal stability of conventional selective chemical vapor deposited tungsten can be increased greatly.

Abstract: A method for forming a Cu-thin film includes the steps of coating a dispersion containing Cu-containing ultrafine particles individually dispersed therein on a semiconductor substrate having recessed portions, such as wiring grooves, via holes or contact holes, which have an aspect ratio ranging from 1 to 30; firing the coated semiconductor substrate in an atmosphere which can decompose organic substances present in the dispersion, but never oxidizes Cu to form a Cu-thin film on the substrate; then removing the Cu-thin film on the substrate except for that present in the recessed portions to thus level the surface of the substrate and to form the Cu-thin film in the recessed portions. The method permits the complete embedding or filling of the recessed portions of LSI substrates having a high aspect ratio with a Cu-thin film and thus permits the formation of a conductive, uniform and fine pattern, and further requires a low processing cost.

Abstract: A method of forming metallic layers on a substrate includes the steps of forming a first layer including a first metal on the substrate; cooling the first layer for a period of time sufficient to suppress formation of an intermetallic phase; and forming a second layer including a second metal distinct from the first metal on the first layer. The cooling step decreases the roughness of the resultant stacked structure by suppressing the formation of an intermetallic phase layer between the two metallic layers and by suppressing “bumps” or other surface irregularities that may form at relatively reactive grain boundaries in the first layer.

Abstract: Low resistivity titanium silicide, and semiconductor devices incorporating the same, may be formed by titanium alloy comprising titanium and 1-20 atomic percent refractory metal deposited in a layer overlying a silicon substrate, the substrate is then heated to a temperature sufficient to substantially form C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, and more preferably is Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900° C., and more preferably between about 600-700° C.

Abstract: Integrated circuitry and methods of forming integrated circuitry are described. In one aspect, a hole is formed in a semiconductor wafer. In a preferred implementation, the hole extends through the entire wafer. Subsequently, conductive material is formed within the hole and interconnects with integrated circuitry which is formed proximate at least one of a front and back wafer surface. According to one aspect of the invention, integrated circuitry is formed proximate both front and back surfaces. In a preferred implementation, a plurality of holes are formed through the wafer prior to formation of the integrated circuitry. In accordance with a preferred implementation, formation of the conductive material within the hole takes place through formation of a first material within the hole. A second material is formed over the first material, with at least the second material being electrically conductive.

Abstract: A solid thin film is formed from a layer of liquid material in such a manner as to fill a contact hole formed in a semiconductor structure; a semiconductor structure is firstly cooled rather than ambience, thereafter, liquid material is spread over the semiconductor structure, then the layer of liquid material is pressed so that the liquid material perfectly fills the contact hole, and, finally, the layer of liquid material is heated so as to form a solid layer from the layer of liquid material.

Abstract: A gate electrode is made up of a polycrystalline silicon film containing phosphorous as a dopant for determining its conductivity type, a titanium silicide film of the C54 structure, and a tungsten silicide film all of which films are laid one on another in said order. A method of manufacturing a semiconductor device of the present invention involves sequentially forming a non-single-crystal silicon film containing a dopant for determining a conductivity type of the non-single-crystal silicon film, a titanium film, and a metal silicide film on a substrate. A titanium silicide film of a C49 and/or C54 structure is formed by performing a heat treatment so as to cause the titanium film to react with the non-single-crystal silicon film while reducing a first native oxide film formed in a first interface between the titanium film and the non-single-silicon film and a second native oxide film formed in a second interface between the titanium film and the metal silicide film.

Abstract: A method for depositing materials on a surface, having the following steps: a) obtaining a surface having at least feature thereon, the surface and the feature having a layer of first material deposited thereon, the first material not filling substantially all of the feature; b) depositing a layer of a second material on the first material, wherein the melting point of the second material is less than that of the first material, and wherein the first material is soluble in the second material at a temperature less than the melting point of the first material; and c) heating the surface to a first temperature of at least equal to the melting point of the second material and at most equal to the melting point of the first material, wherein substantially all of the via is filled with the first material.

Abstract: A semiconductor device having a barrier film comprising an extremely thin film formed of one or more monolayers each comprised of a two-dimensional array of metal atoms. In one exemplary aspect, the barrier film is used for preventing the diffusion of atoms of another material, such as a copper conductor, into a substrate, such as a semiconducting material or an insulating material. In one mode of making the semiconductor device, the barrier film is formed by depositing a precursor, such as a metal halide (e.g., BaF2), onto the substrate material, and then annealing the resulting film on the substrate material to remove all of the constituents of the temporary heteroepitaxial film except for a monolayer of metal atoms left behind as attached to the surface of the substrate. A conductor, such as copper, deposited onto the barrier film is effectively prevented from diffusing into the substrate material even when the barrier film is only one or several monolayers in thickness.

Abstract: A process for preparing a diffusion barrier on a semiconductor substrate which comprises: conducting remote plasma-enhanced metal organic chemical vapor deposition of a thin film of TiNx on said substrate using an organotitanium compound under a flow of H2 plasma, wherein x ranges from 0.1 to 1.5, provides a TiNx thin film having a low carbon content and low specific resistivity.

Abstract: A process for increasing the sheet resistance and lowering the temperature coefficient of resistance of a thin film resistor deposited on a wafer, the process comprising ramping the temperature of the wafer to an annealing temperature above the decomposition temperature of the thin film resistor using a radiant heat source such that the wafer reaches the annealing temperature within a ramp up time of from about 5 to 10 seconds, and annealing the wafer at the annealing temperature for an annealing period of from about 50 to 85 seconds.

Abstract: To form a wiring electrode having excellent contact function, in covering a contact hole formed in an insulating film, a film of a wiring material comprising aluminum or including aluminum as a major component is firstly formed and on top of the film, a film having an element belonging to 12 through 15 groups as a major component is formed and by carrying out a heating treatment at 400° C. for 0.5 through 2 hr in an atmosphere including hydrogen, the wiring material is provided with fluidity and firm contact is realized.

Abstract: The present invention provides an apparatus and method for forming a film by loading an object to be processed into a process chamber, moving up supporting pins to receive the susceptor, heating the object to be processed with heat radiation for a predetermined time by means of a heater housed in the susceptor while the supporting pins is being moved up, mounting the object to be processed on the susceptor, introducing arbitrarily chosen gases to adjust an inner pressure and temperature in accordance with the film formation conditions, and introducing a raw material gas into the process chamber, thereby starting film formation. After completion of the film-formation, only the supply of the raw material gas is stopped, whereas supply of other gases is gradually stopped. When the object to be processed is unloaded from the process chamber after completion of the film formation process, first, supporting pins are moved up to move the object to be processed away from the heater housed in the susceptor.

Abstract: Several processes for forming semiconductor gate structures having treated titanium silicide layers are disclosed. There are at least three methods been provided for the present invention and a summarized general procedure of all the methods comprises the following steps: The first step is to provide a silicon substrate having a gate oxide layer formed on top the silicon substrate, and forming a polysilicon layer over the gate oxide layer, followed by the formation of a TiN layer over the polysilicon layer. A treated titanium silicide layer is then formed on top of the TiN layer. Sequentially, an anti-reflection (SiON) film is deposited on top of the treated titanium silicide layer with a capping layer formed over the anti-reflection film. Finally, patterning and etching the above layers to expose a portion of the gate oxide layer and to form a gate electrode, where the final gate structure is rounded up by a rapid thermal process (RTP).

Abstract: An object of the present invention is to provide a method of manufacturing a semiconductor device, which is capable of reducing metal-film stress produced upon formation of a high melting-point metal film by Chemical Vapor Deposition (CVD) and is very good in controllability. A typical invention of the present application is intended for the implantation of ions of an inert gas in the high melting-point metal film after deposition of the high melting-point metal film over a semiconductor wafer by CVD. According to the typical invention of the present application, since warpage of the semiconductor wafer due to the high melting-point metal film can be reduced, a failure in focus can be reduced in a patterning process for forming the subsequent interconnections, particularly an exposure process using a stepper. Accordingly, interconnections having desired dimensions can be formed.

Abstract: The method of metallization in semiconductor devices provides a substrate having a conducting region and having an insulating layer formed on the substrate. The insulating layer has a contact hole which exposes the conducting region. Next, a silicon-containing metallization layer and a silicon-free metallization layer are sequentially formed on the insulating layer such that the silicon-containing metallization layer contacts the conducting region through the contact hole. After heat-treating the substrate, the two metallization layers are patterned.

Abstract: A method of making a semiconductor device to reduce or prevent defects caused by the ejection of deposited material. The method includes a first layer of material deposited over a substrate in the presence of a gaseous ambient. A portion of the gaseous ambient is trapped by the first layer. This entrapped portion could cause defects during subsequent elevated temperature processing as the gas attempts to escape from the first layer. To prevent or reduce this problem, after depositing the first layer and before depositing a second layer over the first layer, the first layer is heated to remove at least a portion of the gaseous ambient trapped in the layer. For best results, the first layer is heated to a temperature at least as high as the highest temperature of later processing steps and at a pressure of no more than 1 torr. This method is particularly useful for layers formed by physical vapor deposition.

Abstract: A method is provided for forming barrier layers in channel or via openings of semiconductors by using in-situ nitriding of barrier metals (Ta, Ti, or W) after they have been deposited in channel and via openings which will allow better control of the barrier metal/barrier material (Ta/TaN, Ti/TiN, or W/WN) composition, eliminate particle problems, and avoiding target poisoning.

Abstract: A Cu interconnect member is passivated by diffusing Sn, Ta or Cr atoms into its upper surface to form an intermetallic layer. Embodiments include depositing Cu by electroplating or electroless plating to fill a damascene opening in a dielectric layer, CMP, depositing a sacrificial layer of Sn, Ta or Cr on the planarized surface, heating to diffuse Sn, Ta or Cr into the upper surface of the deposited Cu to form a passivating intermetallic alloy layer, and removing any remaining sacrificial layer by CMP or etching.

Abstract: A method of manufacturing a semiconductor device with a multilayer wiring (6, 11, 14) with aluminum conductor tracks (7, 12, 15) which are insulated from one another by insulating layers (9, 13). According to the method, an aluminum conductor track (20) provided on a surface (1) of a semiconductor body (2) is covered with a layer of insulating material (21), whereupon a contact window (22) with a wall (23) reaching down to the conductor track is formed in this insulating layer. A conductive intermediate layer (24, 28) and an aluminum layer (25, 29) are provided on this wall, whereupon a heat treatment is carried out such that aluminum (26) grows from the conductor track into the contact window. A conductive intermediate layer of titanium is provided on the wall of the contact window. A very thin, closed aluminum layer, which remains closed also during the heat treatment, can be formed on this titanium layer, which can be provided on the wall with a small thickness.

Abstract: A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with aluminum to form the aluminum wires. Trench digging is time consuming and costly. Moreover, aluminum has higher electrical resistance than other metals, such as silver. Accordingly, the invention provides a new "self-trenching" or "self-planarizing" method of making coplanar silver wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts silver with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with silver to form silver wires coplanar with the first layer.

Abstract: A method for forming a high-quality aluminum-copper alloy pattern over a semiconductor substrate. The method first forms an aluminum-copper alloy layer over a semiconductor substrate, and then performs a rapid thermal processing operation to remelt copper extracts into the alloy bulk. Subsequently, a photoresist layer is formed over the alloy layer. Finally, the alloy layer is etched to transfer the pattern from the photoresist layer to the metallic alloy layer. Unlike a conventional method that can lead to abnormal conduction due to the presence of extracts that are difficult to etch, this invention uses a thermal operation to remove the extracts before etching is conducted. Hence, the masking effect due to etching is mostly prevented.

Abstract: The present invention is a method of fabricating void-free and volcano-free tungsten plugs. A silicon film was formed over contact hole surfaces for restricting the reflow of a dielectric layer. A titanium film is formed over the silicon layer. By performing a thermal process to the silicon layer and the titanium layer in a nitride-containing environment, the etching damage to the substrate can be recovered and a silicon silicide and a titanium nitride can be formed. The contact resistance of plugs can be significantly reduced, when compared with known technology. The undesired formation of voids and volcano can be eliminated. The method can be employed to fabricate defect-free advanced ULSI devices.

Abstract: In manufacturing a semiconductor device, a refractory metal silicide layer having a first phase structure is formed. In this case, the refractory metal silicide layer having the first phase structure may be formed during performing a deposition operation of a refractory metal, in a state in which a semiconductor substrate is heated. Instead, a refractory metal film may be first deposited in a vacuum state, and then a semiconductor substrate may be heated in the vacuum state to change the refractory metal film into said refractory metal silicide layer having a first phase structure. After the refractory metal silicide layer having the first phase structure is formed, heat treatment is performed to change said refractory metal silicide layer having said first phase structure into a refractory metal silicide layer having a second phase structure.

Abstract: A method of forming metal lines is disclosed. The method comprises the steps of: forming a composite metal layer over a wafer, the composite metal layer having a top layer of titanium/titanium nitride; oxidizing the top layer of titanium/titanium nitride to form a layer of titanium oxide; and patterning and etching the composite metal layer to form the metal lines.

Abstract: The melting point of the solder forming a controlled collapse chip connection is tailored by forming a thin metal cap of a metal such as palladium or silver on a solder bump. When the solder bump is melted during reflow, the metal cap dissolves into the solder. Because the resulting alloy has a higher melting point than the solder, subsequent reflow processing does not melt the chip join structure.

Abstract: A method for use in the fabrication of semiconductor devices includes forming a layer of nitridated cobalt on a surface including silicon. A film cap including titanium is formed over the layer of cobalt and a thermal treatment is performed to form cobalt silicide from the layer of cobalt and the silicon. Further, a layer of cobalt or nickel may be formed over a titanium film on a surface including silicon. The titanium film is formed in an atmosphere including at least one of nitrogen and oxygen and a thermal treatment is performed for reversal and silicidation of the titanium film and the layer of cobalt or nickel to form cobalt silicide or cobalt nickel. The methods may be used for silicidation of a contact area, in forming a polycide line, or in use for other metal silicidation applications.

Abstract: A method of manufacturing a semiconductor device which includes an interface between a metal layer and a barrier layer of a nitride of a refractory metal, comprising the steps of depositing the barrier layer onto a wafer at high temperature; subjecting the barrier layer to a mixture of oxygen or an oxygen-containing gas and an inert gas in the presence of a plasma at low pressure and for a time sufficient to oxidize the surface of the barrier layer; removing the oxygen-containing gas; and depositing the metal layer onto the oxidized surface without subjecting said wafer to an air break. The method permits high throughput to be achieved at low cost.

Abstract: Void free Cu or Cu alloy interconnects are formed by annealing at superatmospheric pressure after metallization. Embodiments include filling a damascene opening in a dielectric layer with Cu or a Cu alloy and heat treating in a chamber at a pressure of about 2 atmospheres to about 750 atmospheres.

Abstract: A titanium based SALICIDE process that is free of bridging effects is described. A controlled quantity of nitrogen is delivered to the silicon oxide (or nitride) surface during titanium silicide formation. The amount of nitrogen is sufficient to inhibit outdiffusion of silicon at the dielectric areas, but insufficient to affect the sheet resistance of the silicon areas. This is accomplished by means of a titanium/titanium-rich titanium nitride/titanium sandwich that is formed in a single sputtering operation. An optional cap layer of stoichiometric titanium nitride may also be added.

Abstract: In a method of manufacturing a semiconductor device, a first wiring layer is formed on a semiconductor substrate. An interlevel insulating film is formed on the semiconductor substrate to cover the first wiring layer. A wiring groove is formed in the interlevel insulating film so as to pass a contact hole formed in the interlevel insulating film to such a depth as to expose the first wiring layer. A contact is formed in the contact hole by depositing a first conductive material on the first wiring layer exposed at the bottom of the contact hole. An island made of the first conductive material and formed on the surface of the interlevel insulating film upon forming the contact is etched and removed. A second wiring layer is formed in contact with the contact by burying a second conductive material in the wiring groove.

Abstract: A doped oxide and an undoped oxide are formed on a substrate. Then, the substrate is annealed to re-flow the doped oxide layer. The doped oxide is then etched back. Next, a contact hole is created by etching. An amorphous silicon layer is formed on the surface of the doped oxide layer and along the surface of the contact hole. Next, high temperature is used to recover the etching damage and simultaneously transform or convert the amorphous silicon into a polysilicon layer. A titanium layer and a titanium nitride are respectively formed onto the polysilicon layer. Next, rapid thermal process (RTP) is introduced to form a titanium silicide beneath the titanium nitride layer. A tungsten layer is formed on the titanium nitride layer and refilled into the contact hole. The tungsten layer is then etched back to form a tungsten plug with void-free in the contact hole. A conductive layer is formed on the titanium nitride layer.

Abstract: An interconnect structure and method for an integrated circuit chip for resisting electromigration is described incorporating patterned interconnect layers of Al or Al--Cu and interlayer contact regions or studs of Al.sub.2 Cu between patterned interconnect layers. The invention overcomes the problem of electromigration at high current density in the interconnect structure by providing a continuous path for Cu and/or Al atoms to move in the interconnect structure.

Abstract: A first metal film and a second metal film, both of which are made of Ni or the like, are deposited on the upper surface of a substrate made of SiC. In such a state, the interface between the first metal film and the substrate and the interface between the second metal film and the substrate both form a Schottky contact. Next, laser light is irradiated from above the upper surface of the substrate only onto the first metal film on the substrate after the diameter of the top end of the laser light has been reduced. Thus, since the metal-semiconductor interface between the first metal film and the substrate is turned into an alloy owing to the energy of the laser light without heating the entire substrate, an ohmic contact can be formed in the interface between the first metal film and the substrate. As a result, an ohmic electrode can be constituted by the first metal film.

Abstract: A method of forming a contact is provided. The method includes the steps of forming a contact hole, creating an enhanced doped region in the contact hole, annealing the enhanced doped region, depositing a barrier metal in the contact hole, annealing the barrier material, and depositing a conductive material in the contact hole. A contact made in this manner exhibits lower contact-to-substrate leakage currents than does a contact formed via conventional single-anneal techniques.