Abstract: Contact structures exhibiting resilience or compliance for a variety of electronic components are formed by bonding a free end of a wire to a substrate, configuring thw wire into a wire stem having a springable shape, serving thw wire stem, and overcoating the wire stem with at least one layer of a material chosen primarily for its structural (resiliency, compliance) characteristics. A variety of techniques for configuring, serving, and overcoating the wire stem are disclosed. In an exemplary embodiment, a free end of a wire stem is bonded to a contact area on a substrate, the wire stem is configured to ahve a springable shape, the wire stem is served to be free-standing by an electrical discharge, and the free-standing wire stem is overcoating by plating.

Abstract: A method of producing a smooth surface for a film of refractory metallic material is realized by placing a substrate in a CVD reactor; initiating deposition of a layer of two phase material via concurrent introduction into the CVD reactor of a precursor gas and molecular oxygen, the latter at a pressure between about 1.times.10.sup.-6 and 1.times.10.sup.-4 ; and annealing the treated layer at the deposition temperature.

Abstract: A method of forming a poly-silicide gate electrode (102). The polysilicon deposition is broken into two steps. After the first polysilicon layer (102a) is formed, a very thin oxide (102b) is formed thereover. Polysilicon deposition then continues to form a second polysilicon layer (102c). The oxide layer (102b) inhibits grain growth resulting in a smaller grain size for the second polysilicon layer (102c). Prior to silicide formation, a pre-amorphization implant is performed to amorphize the second polysilicon layer (102c) and possibly some of the first polysilicon layer (102a) as well. Titanium is deposited and reacted with the polysilicon layers to form a silicide. The silicide process consumes the interface between polysilicon layers (102a & 102c) and possibly a portion of the first polysilicon layer (102a). The resulting silicide layer has a more uniform sheet resistance.

Abstract: A method for nondestructive layer defect detection includes projecting radiation such as a laser beam on a surface of the layer. The surface of the layer is heated by the projected radiation so as to melt at least a portion of the layer. An impurity contained in a defect is heated by the projected radiation so as to increase the pressure of the material within the defect sufficiently to cause the impurity to emerge from the defect through the surface of the layer. The layer is then scanned for a visible defect created by the emergence of the impurity from the defect. A wafer scanning system for nondestructive layer defect detection includes a radiation source such as a laser and a wafer support system that supports a semiconductor wafer with a layer formed thereon in alignment with the radiation source.

Abstract: Method for fabricating a semiconductor device, is disclosed, in which a grain size is made coarse for forming a thin film with a low resistance, including the steps of (1) depositing an insulating film on a substrate, (2) depositing a silicon layer on the insulating film, (3) depositing an amorphous metal nitride film on the silicon layer, and (4) heat treating the amorphous metal nitride film to alter into a crystalline pure metal film.

Abstract: A method for forming metal interconnection of semiconductor device is disclosed. In the present invention, an aluminum layer in the 10 to 100 .ANG. range is deposited on the bottom of the contact before or after the deposition of a titanium layer for barrier metal, which forms TiAl.sub.3 by the reaction of titanium and aluminum. According to the invention, stable contact resistance and low leakage current can be obtained in the application of ultra shallow junction.

Abstract: A method for making copper interconnections in an integrated circuit is described. The structure is a damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing. Since photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.

Abstract: A method for forming a refractory metal silicide layer on a silicon surface in which a first layer of a refractory metal is formed on the silicon surface. A second layer extends over the first layer and is made of a nitrogen containing refractory metal. The silicon surface and the first and second layers are subjected to a heat treatment in an argon gas atmosphere to form a refractory metal silicide layer on an interface between the silicon surface and the first layer.

Abstract: A method of fabricating a capacitor of a semiconductor device is disclosed including the step of forming a lower electrode layer on a semiconductor substrate, and a dielectric on the lower electrode layer, a part of the lower electrode layer, a part of the upper electrode layer adjacent to the dielectric of the capacitor including the upper electrode on the dielectric, or all of them containing oxygen.

Abstract: A process for fabricating contact plugs for semiconductor IC devices. An insulating layer is formed over the surface of an IC substrate. The insulating layer is then patterned for forming contact vias revealing the surface of an electrically conductive region of the IC circuitry that requires electrical connections by the contact plugs. A glue (adhesive) layer is then formed over the sidewall surface inside the contact vias. The glue (adhesive) layer is densified by either a rapid thermal annealing or a plasma treatment in order to prevent the formation of voids when the plugs are formed. The internal space of the contact vias are then filled with an electrically conductive material to form the contact plugs.

Abstract: A method of making Copper alloys containing between 0.01 and 10 weight percent of at least one alloying element selected from carbon, indium and tin is disclosed for improved electromigration resistance, low resistivity and good corrosion resistance that can be used in chip and package interconnections and conductors by first forming the copper alloy and then annealing it to cause the diffusion of the alloying element toward the grain boundaries between the grains in the alloy are disclosed.

Abstract: A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.

Abstract: Process for making a semiconductor device having a barrier film comprising an extremely thin film formed of one or more monolayers each comprised of a two-dimensional array of metal atoms. In one exemplary aspect, the barrier film is used for preventing the diffusion of atoms of another material, such as a copper conductor, into a substrate, such as a semiconducting material or an insulating material. In one mode of making the semiconductor device, the barrier film is formed by depositing a metal halide as a precursor (e.g., BaF.sub.2 or SrF.sub.2), onto the substrate material, and then annealing the resulting film on the substrate material to remove all of the constituents of a temporary heteroepitaxial film except for a monolayer of metal atoms left behind as attached to the surface of the substrate. A conductor, such as copper, deposited onto the barrier film is effectively prevented from diffusing into the substrate material even when the barrier film is only one or several monolayers in thickness.

Abstract: An improved and new method for forming a metal conductor interconnection structure on a semiconductor substrate containing DRAM devices has been developed. The method utilizes a thermal anneal in a flowing gas mixture of nitrogen and hydrogen following patterning of the metal conductor interconnection structure and results in DRAM devices having improved mean refresh time (time between refresh cycles).

Abstract: The method for fabricating a semiconductor device includes steps of forming a layered structure by sequentially depositing a silicon film containing an impurity, a metal silicide film, and an amorphous silicon film containing an impurity, forming an electrode or an interconnect in a three-layer structure by selectively etching the amorphous silicon film, the metal silicide film and the silicon film in this order, and diffusing the impurity in the amorphous silicon film into the metal silicide film by a thermal process. Thus, the impurity is supplied from the amorphous silicon film to the metal silicide film so that the ion-implantation as required in the prior art is not necessary.

Abstract: A method of manufacturing semiconductor device which comprises the steps of forming an insulating film on an Si substrate provided with a wiring layer, forming a contact hole connected to the wiring layer and a wiring groove in the insulating film, filling the contact hole with an Si film, successively forming an Al film and a Ti film all over the substrate, performing a heat treatment thereby to substitute the Al film for the Ti film, and to allow the Si film to be absorbed by the Ti film, whereby filling the contact hole and wiring groove with the Al film, and removing a Ti/Ti silicide which is consisting of Ti silicide formed through the absorption of the Si film by the Ti film and a superfluous Ti, whereby filling the contact hole with an Al plug and filling the wiring groove with an Al wiring.

Abstract: Systems and methods that make it possible to rapidly cycle a workpiece through a temperature/time profile over a wide temperature range, e.g., 0.degree. C. to 350.degree. C., without having to lift and transfer the workpiece between separate baking and chilling mechanisms. The present invention is based in part upon the concept of using a low thermal mass, thermally conductive heating member to support a workpiece, such as a microelectronic device, during both baking and chilling operations. While supporting the workpiece on one surface, the other surface of the heating member can be brought into and out of thermal contact with a relatively thermally massive chill plate to easily switch between baking and chilling operations. A simple mechanism is all that is required to either physically separate the heating member and chill plate to accomplish the most rapid heating, or the simple mechanism adjoins the heating member and chill plate to accomplish the most rapid chilling.

Abstract: A method of manufacturing a semiconductor device having the steps of: preparing a semiconductor device structure having an interconnection structure including a pair of electrically separated interconnections disposed near each other in one layer and a conductive pattern disposed near the pair of interconnections in the same layer; and applying light having a high intensity sufficient for melting and scattering conductive material of the conductive pattern to the conductive pattern and shorting the pair of interconnections with material formed by melting, scattering, and depositing the conductive material. This method provides a semiconductor device capable of easily connecting separated interconnections formed in the same layer.

Abstract: The present invention provides methods of producing an anti-reflective layer on a semiconductor wafer/device and wafers/devices including that anti-reflective layer. The anti-reflective layer is produced by annealing layers of titanium and aluminum on a wafer/device to provide a roughened surface that significantly reduces reflectivity to improve the accuracy and definition provided by optical lithography processes.

Abstract: A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is deposited by chemical vapor deposition, or by physical vapor deposition in a layer less than about 800 angstroms.

Abstract: A three elemental compound for diffusion barrier layer having a superior diffusion barrier characteristics manufactured by forming the compound between the silicon diffused into the diffusion barrier layer and the two elemental compound for diffusion barrier layer before the metal wire layer penetrates into the diffusion barrier layer to reach the underlying silicon layer, using the different characteristics of the diffusion rate as above, is disclosed. A method of forming three elemental compound for diffusion barrier layer according to the present invention comprises a silicon substrate. A silicide layer is deposited on the silicon substrate. A refractory metal nitride layer is then deposited on the silicide layer. A metal wire layer is deposited on the refractory metal nitride layer.

Abstract: A heat treatment is performed in a hydrogen-gas containing atmosphere. A high-purity inert gas having a water content of not more than 2.57 ppm is used as a substitution gas for replacing a wafer-input air atmosphere and for replacing the hydrogen-gas containing atmosphere after the heat treatment.

Abstract: The multilevel interconnection forming method of the present invention comprises the following. A metal film containing aluminum is deposited on an insulating film of a substrate, and the metal film is patterned, to form a wiring layer of a first layer. An interlayer dielectric film forming part of the first layer is formed on an entire surface of the substrate, such that the interlayer dielectric film covers the wiring layer from upside. A hole is formed at a predetermined position of the interlayer dielectric film such that the hole reaches the wiring layer of the first layer. Aluminum is selectively deposited and filled into the hole by a CVD method, such that the aluminum is filled at a volume ratio smaller than 100% with respect to the hole. An active metal film is formed on an entire upper surface of an interlayer dielectric film including the hole filled with the aluminum. A metal layer containing aluminum is formed on the active metal film.

Abstract: A method for forming a gate dielectric (14b) begins by providing a substrate (12). A high K dielectric layer (14a) is deposited overlying the substrate (12). The dielectric layer (14a) contains bulk traps (16) and interface traps (18). A polysilicon gate electrode (20) is then patterned and etched overlying the gate dielectric (14a) whereby the plasma etching of the gate electrode (20) results in substrate plasma damage (22). A post gate wet oxidation process is performed between 750.degree. C. and 850.degree. C. to reduce plasma etch damage and trap sites (16, 18) in order to provide an improved gate dielectric (14b). Source and drain electrodes (30) are then formed within the substrate and laterally adjacent the gate electrode (20) to form a transistor device having more consistent threshold voltages, improved subthreshold slope operation, reduced gate to channel leakage, and improved speed of operation.

Abstract: An interlayer insulating film made of insulating material is deposited on a substrate having a conductive region at least partially on the surface area thereof. A connection hole is formed through the interlayer insulating film, to expose the conductive region. The connection hole is filled with a plug made of conductive material. An underlying layer made of Ti is deposited over the whole surface of the substrate including the surface of the plug. A wiring layer made of Al alloy is deposited on the underlying layer, without exposing the substrate to the external atmosphere after the deposition of the Ti layer. The wiring layer is reflowed by heating the substrate. A method is provided which is capable of connecting an upper wiring layer to a lower conductive region without lowering resistance to electromigration and lowering step coverage.

Abstract: The present invention is a method and apparatus for filling voids in a substrate with a desired material to form conductive components and/or other features on the substrate. In one embodiment in accordance with the principles of the present invention, a substrate with voids is covered with a first layer of material and then a second layer of material is formed on top of the first layer. The first layer is deformable at a deformation temperature, while the second layer has a higher yield strength than the first layer and is substantially non-deformable at the deformation temperature. The second layer, for example, may be a rigid and/or substantially incompressible layer that distributes a driving force to the first layer. The second layer is then pressed against the first layer at a temperature equal to or greater than the deformation temperature to drive portions of the first layer into the voids in the substrate.

Abstract: A recess having a height-to-width aspect ratio from about 6:1 to about 10:1 in a semiconductor structure is taught with a method of forming the same. In a first embodiment, a refractory metal layer is formed in the recess, which can be a trench, a contact hole, or a combination thereof. A refractory metal nitride layer is then formed on the refractory metal layer. A heat treatment, preferably RTP, is used to form a metal silicide contact at the bottom of the contact hole upon semiconductor material. In a first alternative method, an ammonia high-temperature treatment is conducted to remove undesirable impurities within the refractory metal nitride layer lining the contact hole and to replace the impurities with more nitrogen. In a second alternative method, a second refractory metal nitride layer is formed by PVD upon the first refractory metal nitride layer. In either alternative, a metallization layer is deposited with the recess.

Abstract: There are disclosed apparatus and method for well performing a reflow step that reduces malfunctions of TFTs due to defective contacts. The apparatus has at least first and second hermetic reaction chambers whose ambients can be controlled independently. These two chambers are connected together hermetically. In the first chamber, a film consisting only or chiefly of aluminum is formed by sputtering. In the second reaction chamber, a heat treatment is performed to impart fluidity to at least a part of the film consisting only or chiefly of aluminum.

Abstract: The present invention relates to a method of forming an interconnection for a semiconductor device using copper. The method of the invention, including the steps of forming an insulating layer having a groove on a semiconductor substrate containing active elements; forming and depositing a copper thin film on the insulating layer including the groove; and reflowing the copper thin film, may reflow the copper thin film deposited on the semiconductor substrate having a high-step surface for less than 30 min. below 450.degree. C., which show improved annealing conditions as compared with the conventional art. In addition, by reducing consumption of thermal energy in accordance with a low-temperature process, copper is restrained from being rapidly diffused through a silicon substrate, electrodes, etc. when forming the interconnection for the semiconductor device, thus improving productivity of the semiconductor devices.

Abstract: A nitriding agent is introduced into selected regions of a semiconductor device. A metal such as, for instance, titanium is immediately deposited over the semiconductor device. A subsequent thermal annealing step induces selective reactions between the titanium and the underlying silicon, thereby resulting in the formation of a layer of titanium silicide within the selected regions, as well as a layer of titanium nitride. The layer of titanium nitride and unreacted portions of the layer of titanium are removed in a subsequent etching step, thereby leaving intact a layer of titanium silicide within the selected regions. A second annealing step converts the silicide into a substantially stoichiometric composition. The introduction of the nitriding agent into the selected regions significantly reduces the agglomeration of titanium during silicide formation, thereby resulting in a more uniform, and thus more conductive, silicide layer.

Abstract: A substrate heating apparatus having a chamber, a device for adding gas into the chamber and a substrate heater is provided. The substrate heater is located within the chamber and includes a first plate having a bottom surface. The bottom surface of the first plate has at least one groove. The at least one groove forms at least two thermal zones on the first plate. The substrate heater further includes a heater element and a second plate. The heater element is located between the bottom surface of the first plate and the second plate and thus enables heating of the substrate by radiation and gas conduction.

Abstract: A method of forming wirings which includes forming a film of a silicon-containing metal layer at a high temperature on an underlying metal, thereby forming a silicon alloy layer which includes the underlying metal and the silicon-containing metal during film formation. In a case of forming wirings by a silicon-containing metal layer, occurrence of Si nodules can be eliminated to obtain wirings of high reliability.

Abstract: A method of forming a metal plug. A contact window is formed to penetrate through a dielectric layer on a substrate having a MOS formed thereon. A titanium glue layer is formed on the dielectric layer and the circumference of the contact window. A titanium barrier layer is formed on the titanium nitride layer. Using nitrogen plasma bombardment on the titanium nitride layer, the structure of the titanium nitride layer is transformed. The number of the nucleation seeds is increased, and the size of grains is reduced. A metal layer is formed on the titanium nitride layer and fills the contact window. A part of the metal layer is removed and a metal plug within the contact window is formed.

Abstract: A first TiSix layer is deposited on a polysilicon layer, then a silicon substrate is annealed in a vacuum atmosphere to crystallize the TiSix layer, and a second TiSix layer is provided on the first crystallized TiSix layer.

Abstract: In a method and an appratus for a thin film growth on a semiconductor crystal substrate, impurities and contaminants absorbed on the inside wall of the reaction vessel are very harmful because these impurities and contaminants will deteriorate the quality of the thin film. A method and an apparatus by which the quantity of these impurities and contaminants absorbed on the inside wall of the reaction vessel can be restrained and removed easily are disclosed in this invention, wherein a semiconductor crystal substrate is mounted in the reaction vessel, and the wall of the reation vessel is cooled forcibly by a coolant while the substrate is under heating procedure to grow a thin film on the substrate by supplying the raw material gas into the reaction vessel. And the temperature of the wall of the reaction vessel during the procedure except the thin film growth is kept higher temperature than the temprature of the wall of the reaction vessel during the thin film growth procedure.

Abstract: Via void formation is substantially reduced or eliminated between the steps of depositing a barrier layer on a HSQ gap fill layer, and filling a through-hole with a conductive material deposited on the barrier layer, by performing a low-temperature baking following the deposition of the barrier layer. In particular, a high-temperature, low-pressure degas operation is performed immediately preceding, and in-situ with, the tungsten plug deposition that fills the through-hole to form a via. The low-pressure baking is performed at a high temperature and sufficiently low pressure that is less than the vapor pressure of imparities contained in the HSQ. Hence, any exposed portions of the HSQ gap fill layer that are not covered by the barrier layer (e.g., the titanium nitride (TiN) liner) will be outgassed during the low-pressure baking to minimize the possibility of HSQ outgas during tungsten deposition.

Abstract: Borderless submicron vias are formed between patterned metal layers gap filled with a high density plasma oxide. Heat treatment is conducted after chemical vapor deposition of the high density plasma oxide to substantially increase the grain size of the patterned metal layers, thereby improving electromigration resistance.

Abstract: A method of fabricating a metal plug. On a semiconductor substrate comprising a MOS device, a dielectric layer, and a via hole penetrating though the dielectric layer, a conformal titanium layer is formed on the dielectric layer and the via hole. A low temperature annealing is formed in a nitrogen environment, so that a surface of the titanium layer is transformed into a first thin titanium nitride layer. A conformal second titanium nitride layer is formed on the first thin titanium nitride layer by using collimator sputtering. A metal layer is formed and etched back on the second titanium nitride layer to form a metal plug.

Abstract: Disclosed herein is a method for forming a copper interconnect in which a substrate having the copper interconnect is exposed to atmosphere after the substrate is cooled to a temperature below 160.degree. C. under a non-oxidizable atmosphere. The exposure of the substrate to a relatively high temperature conventionally makes an electric resistance between interconnects on the substrate higher to prevent high integration. In accordance with the present invention, the above electric resistance can be reduced to smoothly realize the high integration because of the exposure of the substrate to a relatively low temperature.

Abstract: Copper and a small amount of an alloying metal such as magnesium or aluminum are cosputtered onto a substrate having oxide on at least a portion of its surface. Either the wafer is held at an elevated temperature during deposition or the sputtered film is annealed without the wafer being exposed to ambient. Due to the high temperature, the alloying metal diffuses to the surface. If a surface is exposed to a low partial pressure of oxygen or contacts silicon dioxide, the magnesium or aluminum forms a thin stable oxide. The alloying metal oxide encapsulates the copper layer to provide a barrier against copper migration, to form an adhesion layer over silicon dioxide, and to act as a seed layer for the later growth of copper, for example, by electroplating.

Abstract: Method of fabricating a narrow linewidth transistor having a low sheet resistance. The transistor may be fabricated in a surface of a semiconductor layer (12). A gate body (14) may be formed separated from an outer surface (16) of the semiconductor layer (12) by a gate insulator (18). The gate body (14) may have an inner surface (20) proximate to the semiconductor layer (12) and an opposite outer surface (22). An insulator layer (30) may be deposited outwardly of the semiconductor layer (12) and the gate body (14). The insulator layer (30) may be anisotropically etched to form side walls (32) adjacent to the gate body (14). The anisotropic etch may cause a residual layer of contaminants (34) to form on the outer surface (16) of the semiconductor layer (12) and on the outer surface (22) of the gate body (14). A protective layer (50) may be deposited outwardly of the residual layer of contaminants (34). Dopants may be implanted into the semiconductor layer (12) proximate to the side walls (32).

Abstract: A II-VI group compound semiconductor device includes a semiconductor substrate, a Zn.sub.X Mg.sub.1-X S.sub.Y Se.sub.1-Y (0.ltoreq.X.ltoreq.1, 0.ltoreq.Y.ltoreq.1) semiconductor layer formed on the semiconductor substrate, and an electrode layer formed on the semiconductor layer, the electrode layer containing an additive element of Cd or Te and a metal which can form a eutectic alloy with the additive element, thus achieving an electrode layer having a small contact resistance, especially an electrode layer with an ohmic contact.

Abstract: On a main surface of a silicon substrate of one conductivity type, a diffusion layer of the opposite conductivity type is formed, and the main surface of the silicon substrate is covered by an insulator film. The insulator film is formed with a contact hole which extends to reach the diffusion layer of the opposite conductivity type. A contact plug is provided in the contact hole. The contact plug fills the contact hole and comprises a first silicon layer of the opposite conductivity type directly connected to the diffusion layer of the opposite conductivity type, a silicon-germanium alloy layer of the opposite conductivity type directly contact to the first silicon layer, and a second silicon layer of the opposite conductivity type directly contact to the silicon-germanium alloy layer. Wiring is provided on the surface of the insulator film in direct contact to the contact plug.

Abstract: A process for preparing a semiconductor device using a dielectric thin film includes the steps of forming a first electrode on a base plate; forming a dielectric film on the first electrode, the dielectric film including a Perovskite structure oxide; forming a second electrode on the dielectric film; and annealing the first and second electrodes so that metal components of the first and second electrodes are oxidized and diffused into a crystal system of the dielectric film.

Abstract: A method for fabricating a semiconductor device, such as a MOS (metal-oxide semiconductor) transistor, with self-aligned silicide is provided. This method can prevent junction leakage between the silicide and the substrate so as to allow the resultant semiconductor device to have reliable performance. The method includes the steps of preparing a semiconductor substrate; forming at least one transistor element over the substrate, the transistor element including a pair of source/drain regions, a gate, a dielectric layer over the gate, and a spacer on the sidewall of the gate; and performing an ion-bombardment process so as to transport one part of the dielectric layer that is adjacent to the top of the spacer to beside the bottom of the spacer.

Abstract: Platinum film orientation-controlled to (111), (200) and/or (220) are provided by depositing the platinum film under an atmosphere containing nitrogen as well as an inert gas (Ar, Ne, Kr, Xe) on a substrate heated to temperature ranged from room temperature to 500.degree. C., and then annealing to substantially remove nitrogen introduced into the platinum film during the deposition thereof. The platinum film formed in this process has an excellent electrical conductivity (resistivity is lower than 15 .mu..OMEGA.-cm), good enough adhesion strength to be used for electronic devices, and does not show hillocks, pores or pinholes.

Abstract: A method for forming a conductive contact having an atomically flat interface is disclosed. A layer containing cobalt and titanium is deposited on a silicon substrate and the resulting structure annealed in a nitrogen containing atmosphere at about 500.degree. C. to about 700.degree. C. A conductive material is deposited on top of the structure formed on anneal. A flat interface, which prevents diffusion of conductive materials into the underlying silicon substrate is formed. The method can be used to form contacts for very small devices and shallow junctions, such as are required for ULSI shallow junctions.

Abstract: A method of producing an improved thin film transistor structure is provided having no source/gate or drain/gate overlap. A laser-assisted doping technique is applied to fabricate such transistors. A radiation filter is employed, which is transparent to light at the photolithography wavelength, but reflective or opaque at the laser wavelength. Eliminating source/gate and drain/gate overlap significantly reduces or eliminates parasitic capacitance and feed-through voltage between source and gate. Short-channel a-Si:H thin film transistors may be obtained having high field effect mobilities. Improved pixel performance and pixel-to-pixel uniformity is provided.

Abstract: A polysilicon/amorphous silicon composite layer for improved linewidth control in the patterning of gate electrodes, in the manufacture of metal oxide semiconductor (MOS) devices. The formation of a composite polysilicon/amorphous silicon gate in an integrated circuit gives the device the electrical performance and doping qualities of a polysilicon gate and also gives the device the smoothness of an amorphous silicon gate which improves line definition during gate patterning.

Abstract: A CVD process for Ti--Si--N or Ti--B--N films wherein a single feed gas (preferably TDMAT) serves as the source for titanium and nitrogen, and another feed gas is used as the source for silicon or boron. This avoids gas-phase particulate nucleation while providing good conformality. When the required thickness has been deposited, the silicon or boron feed gas continues to flow for some time after the titanium/nitrogen or titanium/boron source gas has been turned off. This results in a Ti--N film with a Si-rich or B-rich surface, which is conformal and has a low defect density. In a second embodiment, a single feed gas, such as TDMAT, is thermally decomposed to form a Ti--N layer. A post-deposition anneal is performed in a gas which supplies silicon or boron, incorporating these materials into the layer. The incorporation of silicon or boron into the layer minimizes the absorption of oxygen into the films, and therefore stabilizes the resulting films.