Abstract: There are provided a manufacturing process for a mirror finished silicon wafer capable of manufacturing a mirror finished silicon wafer, having an excellent quality in which grown-in crystal defects are annihilated by heat-treating the silicon mirror finished wafer in a heat treatment in a gas atmosphere of high safety at a lower cost without selection of a heat treatment furnace for use in the heat treatment, a mirror finished silicon wafer having an excellent quality, and a heat treatment furnace preferably used in the manufacturing process.

Abstract: A method of depositing a non-conductive barrier layer onto a metal surface wherein the resistance of the metal remains substantially unchanged before and after the non-conductive barrier layer deposition. The deposition process provides a low temperature processing environment so as to inhibit the formation of impurities such as silicide in the metal, wherein the silicide can adversely increase the resistance of the underlying metal.

Abstract: This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduce the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.

Abstract: A semiconductor device includes a semiconductor substrate having a device element, an interlayer dielectric layer (silicon oxide layer, BPSG layer) formed on the semiconductor substrate, a through hole defined in the interlayer dielectric layer, a barrier layer formed on surfaces of the interlayer dielectric layer and the through hole, and a wiring layer formed on the barrier layer. The barrier layer includes a first metal oxide layer formed from an oxide of a metal that forms the barrier layer (e.g., a first titanium oxide layer), a metal nitride layer formed from a nitride of the metal that forms the barrier layer (e.g., a titanium nitride layer), and a second metal oxide layer formed from an oxide of the metal that forms the barrier layer (e.g., a second titanium oxide layer). The semiconductor device thus manufactured has a barrier layer of an excellent barrier capability.

Abstract: The present invention teaches how greater solder ball height can be achieved without the need to sacrifice areal density. The mold in which the solder is formed, is created in two steps. In a first exposure, a negative photoresist (preferably DFR) is patterned to form a conventional cylindrical mold. However, exposure and development time are adjusted in such a way that a layer of unexposed and undeveloped resist of reduced thickness remains covering the floor of the mold. This residual resist layer is given a second exposure and, after development, forms an annular insert in the bottom of the first mold. After the mold has been filled with solder (either through electroplating or by using solder paste) it is removed, the result being a solder bump made up of two contiguous coaxial cylinders the upper one having the larger diameter. After remelt, bumps having this shape form oblate spheroids rather than spheres.

Abstract: A nickel silicide layer is formed on a semiconductor device having a crystalline silicon source/drain region doped with arsenic. Arsenic is doped into the crystalline silicon, by implantation, for example, so that the concentration of arsenic is slightly below the surface of the silicon. Annealing restores the crystalline structure of the silicon after implantation of the arsenic. Amorphous silicon is selectively deposited over the source/drain regions and over the top of the gate electrode. Nickel is deposited over the entire semiconductor device and a second anneal reacts the nickel with the amorphous silicon. The second anneal is timed so that the nickel reacts with the amorphous silicon, and does not substantially react with the silicon source/drain regions containing arsenic. Preventing the nickel from substantially reacting with the silicon source/drain regions containing arsenic provides a smooth interface between the resulting nickel silicide and the silicon source/drain regions doped with arsenic.

Abstract: The present invention relates to a diffusion barrier layer for a semiconductor device and fabrication method thereof. The diffusion barrier layer according to the present invention is fabricated by forming a diffusion barrier layer containing a refractory metal material and an insulating material on an insulating layer and in a contact hole, wherein the insulating layer being partially etched to form the contact hole, is formed on a semiconductor substrate; and annealing the diffusion barrier layer. Therefore, an object of the present invention is to provide a diffusion barrier layer for a semiconductor device, which is of an amorphous or microcrystalline state and thermodynamically stable even at a high temperature since an insulating material is bonded to a refractory metal material in the diffusion barrier layer.

Abstract: In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from being adsorbed onto the surface of the first conductive layer. In one embodiment, a second conductive layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates an oxide formed between the two layers as a result of subsequent thermal treatments. In another embodiment, a dielectric layer is deposited onto the first conductive layer, and the plasma treatment lessens if not eliminates the ability of the first conductive layer to incorporate oxygen from the dielectric.

Abstract: A dual-sided semiconductor chip is formed on a wafer to have a low-resistance, electrically-conductive path through the wafer. By forming the conductive path through the wafer, elements on one side of the wafer can exchange signals (voltages and/or currents) with elements on the other side of the wafer.

Abstract: This invention describes two new methods to form copper alloy films. In the first embodiment of this invention physical vapor deposition (PVD) or sputtering of a copper alloy film, is then followed by a chemical vapor deposition (CVD) or electro-chemical deposition (ECD) of a layer of pure copper. In the second embodiment of this invention chemical vapor deposition (CVD) or electro-chemical deposition (ECD) deposits a layer of pure copper, which is then followed by physical vapor deposition (PVD) or sputtering of a copper alloy film. In yet another embodiment to these methods, special, separate low temperature annealing steps follow said methods to enhance copper alloy formation. By the two deposition techniques briefly described above, high aspect ratio vias and trenches can be filled with copper corrosion and electromigration resistant alloys.

Abstract: A method for manufacturing a capacitor of a semiconductor memory device by a two-step thermal treatment is provided. A lower electrode is formed on a semiconductor substrate. A dielectric layer is formed over the lower electrode. An upper electrode formed of a noble metal is formed over the dielectric layer. The resultant having the upper electrode undergoes a first thermal treatment under a first atmosphere including oxygen at a first temperature which is selected to be within a range of 200-600° C., which is lower than the oxidation temperature of the upper electrode. The first thermally treated resultant undergoes a second thermal treatment under a second atmosphere without oxygen at a second temperature which is selected to be within a range of 300-900° C., which is higher than the first temperature.

Abstract: In order to provide a manufacturing method of a semiconductor device which can improve the interconnection lifetime, while controlling the increase in resistance thereof, and, in addition, can raise the manufacturing stability; by applying a plasma treatment to the surface of a copper interconnection 17 with a source gas comprising a nitrogen element being used, a copper nitride layer 24 is formed, and thereafter a silicon nitride film 18 is formed. Hereat, under the copper nitride layer 24, a thin copper silicide layer 25 is formed.

Abstract: In a method for fabricating a thin film transistor array substrate, a glass substrate undergoes an oxygen plasma treatment. A silver or silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a gate line assembly proceeding in the horizontal direction. The gate line assembly includes gate lines, gate electrodes, and gate pads. Thereafter, a silicon nitride-based gate insulating layer is deposited onto the substrate, and a semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. The semiconductor layer and the ohmic contact layer are HF-treated. A silver alloy-based conductive layer is deposited onto the substrate, and patterned to thereby form a data line assembly. The data line assembly includes data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads.

Abstract: A semiconductor device and a manufacturing method therefor, a circuit substrate, and electronic apparatus are provided, in which electrical connection can be performed with high reliability and with ease.

Abstract: A manufacturing method of a semiconductor device which includes wiring dense part and wiring isolated part enables occurrence of ‘Erosion’ to be prevented, as well as it is capable of being prevented occurrence of ‘micro-scratch’ on surface of oxide layer. The manufacturing method sets a plurality of trench-parts on insulation layer, before forming metal plating layer consisting of copper so as to embed trench-parts. Manufacturing process implements annealing in such a way that grain-size of the metal plating layer in the wiring dense part becomes smaller than the grain-size in the wiring isolated part. The annealing, for instance, is implemented with substrate temperature of 70 to 200° C. Subsequently, the manufacturing step perfects the semiconductor device while polishing the metal plating layer to cause the surface of the substrate to be flat.

Abstract: A method for stabilizing a degas temperature of wafers in a degas chamber comprises (a) setting an electrical heater at an initial output power, (b) heating each wafer for a first period of time to keep the temperature of the wafer at a predetermined range by setting the electrical heater at a first output power equal to or higher than the initial output power, (c) heating the wafer for a second period of time to increase the temperature of the wafer to a predetermined value by raising the output power of the electrical heater to a second output power; and (d) heating the wafer for a third period of time by reducing the output power of the electrical heater to a third output power. The method lessens the “first wafer effect” and the “temperature-accumulated effect”. Therefore, the temperature of the wafers can be well controlled before a subsequent sputtering process.

Abstract: A method for forming a thin aluminum-nitride film (112). Solid hydrazine cyanurate is heated to produce in-situ hydrazine (N2H4). The in-situ hydrazine reacts with a previously deposited ailminum layer (108) to form aluminum-nitride (112).

Abstract: Methods and apparatuses are disclosed in which a refractory layer is formed during rapid thermal processing wherein ambient hydrogen is used in the thermal processing chamber. Rapid thermal processing may occur at a temperature approximately in the range of 350° C. to approximately 550° C.

Abstract: In one aspect, the invention includes a semiconductor processing method comprising a) forming a metal silicide layer over a substrate; b) depositing a layer comprising silicon, nitrogen and oxygen over the metal silicide layer; and c) while the layer comprising silicon, nitrogen and oxygen is over the metal silicide layer, annealing the metal silicide layer.

Abstract: A semiconductor device which can reduce contact resistance, is disclosed. A semiconductor device according to the present invention includes a lower conductor pattern and an upper conductor pattern. The lower conductor pattern is in contact with the upper conductor pattern. The lower conductor pattern includes a first doped polysilicon layer, a first tungsten silicide layer and a cap layer formed sequentially. Here, the cap layer is formed to a doped polysilicon layer containing a small amount of tungsten and has stoichiometrical equivalent ratio x of Si higher than the first tungsten silicide layer. The upper conductor pattern includes a second doped polysilicon layer and a second tungsten layer formed sequentially. The contact of lower conductor pattern and the upper conductor pattern is substantially formed between the cap layer and the second doped polysilicon layer. Preferably, stoichiometrical equivalent ratio x of Si for the first tungsten silicide layer is 2.3 to 2.

Abstract: In order to fabricate a dynamic memory cell configuration with a long retention time, a hydrogen heat treatment of the wafer is carried out after the production of the interconnect system. The hydrogen heat treatment is performed in a PECVD reactor into which hydrogen is introduced and excited in the plasma. The heat treatment becomes more effective as a result and can be combined with deposition processes, in particular of passivation layers, carried out in PECVD installations.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer of titanium, tantalum, tungsten, or a nitride of the aforegoing is deposited to line the opening, and a copper or copper alloy conductor core is deposited to fill the channel opening over the barrier layer. After planarization of the conductor core and the barrier layer, an ammonia, nitrogen hydride, or hydrogen plasma treatment is performed below 300° C. to reduce the residual oxide on the conductor core material. The plasma treatment is followed by the deposition of a silicon nitride capping layer performed below 300° C. After the reducing and deposition process, a densification process is performed between 380° C. and 420° C.

Abstract: A metallization structure and method for fabricating such a metallization structure are presented. The present method preferably includes forming a void within a metal layer. The void may have a void pressure level, which is preferably approximately equal to the pressure in a deposition chamber in which the metal layer is arranged when the void is formed. Subsequently, the void may be collapsed by increasing a pressure level outside of the void to a collapsing pressure level significantly above the void pressure level. Increasing a pressure level outside of the void preferably includes increasing a pressure level within the deposition chamber to a collapsing pressure sufficient to collapse the void. A metallization structure formed by such a process may be substantially void-free, even in narrow, high aspect ratio metallization cavities.

Abstract: A method for making a semiconductor device is described. That method comprises forming a copper containing layer on a substrate, then forming a tantalum containing layer on the copper containing layer. After the tantalum containing layer is oxidized, an etch stop layer may be formed on the oxidized tantalum layer.

Abstract: A method of manufacturing a metal pattern of a semiconductor device. A Ti layer and a metal layer are successively formed on a semiconductor substrate or on an insulating layer. Then, a wiring pattern including a Ti layer pattern and a metal layer pattern is formed by patterning said Ti layer and the metal layer. Heat treating is employed under an atmosphere of a compound including nitrogen in order to react an exposed portion of the Ti layer pattern to form TiN as a main product, thereby increasing the stability and adhesiveness of the metal layer for subsequent processes.

Abstract: Disclosed is a technique capable of suppressing the damage of a semiconductor manufacturing apparatus due to the breakage or the crack to the minimum by surely detecting the breakage or the crack on a part of a wafer in a semiconductor manufacturing apparatus of a multi-chamber system. An entire image of a wafer is photographed by a camera in each time when the wafer is processed, and the photographed image is processed by a discrimination unit, thereby determining the presence of the breakage or the crack on the wafer. When the breakage or the crack is detected, an error signal is transmitted from the discrimination unit to a computer that controls the semiconductor manufacturing apparatus, and the operations of the process chamber and the transport chamber used immediately before the detection of the breakage or the crack on the wafer are stopped.

Abstract: A heat treatment method for heat treating a thin film is a method for heat treating the thin film having a metallic silicide layer, comprising a heating step, a temperature keeping step and a cooling step. Among these steps, the thin film is heated in an atmosphere of gas which is oxidizing gas or includes oxidizing gas at least in the heating step. An oxide film is formed on the thin film in the heating step to prevent the phosphorous atoms from escaping.

Abstract: In forming an interconnection having a structure in which an Al interconnection is covered with an interlayer insulating film, for the purpose of preventing voids to be created in the Al interconnection layer, together with suppressing the current leakage owing to the generation of etching residues, a multi-layered structure including a barrier layer (4), an Al interconnection metal layer (5), a Ti layer (2b) and an anti-reflection layer (6) is formed on a semiconductor substrate having an insulating surface, and thereafter layers of said multi-layered structure are patterned, at least, down to the Ti layer (2b) into the shape of structure is heated so as to turn the Ti layer (2b) into an AlTi alloy layer and, then, the steps of growing an interlayer insulating film to bury said patterned interconnection planarizing the interlayer insulating film and carrying out another heat treatment to degas the interlayer insulating film are performed.

Abstract: The reliability and elecrtromigration resistance of planarized metallization patterns, e.g., of copper, in-laid in the surface of a layer of dielectric material, are enhanced by a process comprising blanket-depositing on the planarized, upper surfaces of the metallization features and the dielectric layer at least one thin layer comprising at least one alloying element for the metal of the features, and then uniformly diffusing at least a minimum amount of the at least one thin layer for a minimum depth below the upper surfaces of the metallization features to effect alloying therewith. The alloyed portions of the metallization features advantageously reduce electromigration therefrom. Planarization, as by CMP, may be performed subsequent to diffusion/alloying to remove any remaining elevated, alloyed or unalloyed portions of the at least one thin layer.

Abstract: In a method of manufacturing a thin film, a buffer layer is formed a substrate. Thereafter, a ferroelectric thin film material is applied thereto before thermally decomposing the buffer layer. Subsequently, the buffer layer and the ferroelectric thin film are decomposed together. Finally, a crystallized thermal process is performed.

Abstract: A method of forming a dual damascene structure. A first dielectric layer and a second dielectric layer are sequentially formed over a substrate. A first photoresist layer is formed over the second dielectric layer. Photolithographic and etching operations are conducted to remove a portion of the second dielectric layer and the first dielectric layer so that a via opening is formed. A conformal third dielectric layer is coated over the surface of the second dielectric layer and the interior surface of the via opening. The conformal third dielectric layer forms a liner dielectric layer. A second photoresist layer is formed over the second dielectric layer and then the second photoresist layer is patterned. Using the patterned second photoresist layer as a mask, a portion of the second dielectric layer is removed to form a trench. The patterned second photoresist layer is removed. Conductive material is deposited over the substrate to fill the via opening and the trench.

Abstract: The present invention provides a method of preventing fluorine ions from residing in a gate to result in boron ion penetration into a gate oxide on a semiconductor wafer. A substrate, an oxide layer, a conductive layer, an anti-reflection coating (ARC), and a photoresist layer positioned on the ARC defining patterns of a gate, are formed, respectively, on the semiconductor wafer. The method first involves an etching process to remove portions of both the ARC and the conductive layer uncovered by the photoresist layer to form the gate and a gate oxide layer. After the photoresist layer is stripped, an ion implantation process is performed using the gate covered by the ARC as hard mask and boron fluoride (BF2+) as the dopant to form lightly doped drains (LDD) in the substrate adjacent to the gate. Then, a spacer is formed around the gate after the ARC is removed. Finally, the method is completed with the formation of a source and a drain in the substrate adjacent to the spacer after the ARC is stripped.

Abstract: A method and structure is described which substantially eliminates the grain growth of copper due to self annealing. Basically, by alloying the copper interconnect e.g. with Cr, Co, Zn or Ag in an amount which does not cause a second phase or precipitation at the annealing temperature, one can control and maintain the grain size of the copper and hence achieve a uniform microstructure while improving the strength, hardness and CMP removal rate of the interconnect while substantially maintaining the conductivity of the copper.

Abstract: A method and structure providing N-profile engineering at the poly/gate oxide and gate oxide/Si interfaces of a layered polysilicon/amorphous silicon structure of a semiconductor device. NH3 annealing provides for the introduction of nitrogen to the interface, where the nitrogen suppresses Boron diffusion, improves gate oxide integrity, and reduces the sites available for trapping hot carriers which degrade device performance.

Abstract: A method for processing a substrate comprising the formation of a metal nitride/metal stack suitable for use as a barrier/liner for sub-0.18 &mgr;m device fabrication. After a metal nitride layer is deposited upon a metal layer, the metal nitride layer is exposed to a treatment step in a nitrogen-containing environment, e.g., a plasma. The plasma treatment modifies the entire metal nitride layer and a top portion of the underlying metal layer. The plasma adds nitrogen to the top portion of the metal layer, resulting in the formation of a nitrated-metal layer. Aside from reducing the microstructure mismatch across the nitride-metal interface, the plasma treatment also densifies and reduces impurities from the deposited nitride layer. The resulting nitride/metal stack exhibits improved film properties, including enhanced adhesion and barrier characteristics. A composite nitride layer of a desired thickness can also be formed by repeating the deposition and treatment cycles of thinner component nitride layers.

Abstract: A data carrier for noncontacting control of persons with nontransferable entitlement to utilize a service is integrated into a bracelet (1) so as to be useless after the bracelet (1) is opened.

Abstract: Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have begun using copper instead of aluminum to form integrated-circuit wiring, because copper offers lower electrical resistance and better reliability at smaller dimensions. However, use of copper typically requires forming a diffusion barrier to prevent contamination of other parts of an integrated circuit and forming a seed layer to facilitate copper plating steps. Unfortunately, typical diffusion barrier materials add appreciable resistance to the copper wiring, and thus negate some of the advantages of using copper. Moreover, conventional methods of forming the diffusion barriers and seed layers require use of separate wafer-processing chambers, giving rise to transport delays and the introduction of defect-causing particles.

Abstract: A plurality of test interconnect structures are formed with each test interconnect structure having a respective alloy seed layer and with a fill conductive material formed to fill the respective interconnect opening. The respective alloy seed layer of each of the test interconnect structures has a respective thickness and a respective concentration of an alloy dopant within a bulk conductive material. A respective thermal anneal process is performed at a respective thermal anneal temperature for each of the plurality of test interconnect structures. A respective resistance and a respective rate of electromigration failure is measured for each of the plurality of test interconnect structures. For forming an IC interconnect structure within an IC interconnect opening, an alloy seed layer is deposited onto sidewalls and a bottom wall of the IC interconnect opening, and the IC interconnect opening is filled by growing a fill conductive material from the alloy seed layer within the IC interconnect opening.

Abstract: A method of manufacturing a semiconductor device comprises steps of: forming a first metal film having a reducing property on a semiconductor substrate; thermal treating the resulting semiconductor substrate for reducing a native oxide film naturally formed on the semiconductor substrate and for forming a first silicide film on the semiconductor substrate; removing an unreacted first metal film selectively; forming a second metal film on the semiconductor substrate; and thermal treating the resulting semiconductor substrate for forming a second silicide film on a surface of the semiconductor substrate which includes a region where the first silicide film is formed.

Abstract: In a substrate processing apparatus, processing units are stacked in a multistage manner around a transport robot arranged at the center of a processing area for forming a processing part. In a second hierarchy, rotary coating units are arranged through an indexer and a transport robot. In a fourth hierarchy located above the second hierarchy, rotary developing units are stacked above the rotary coating units respectively. Multistage thermal processing units and an edge exposure unit are horizontally arranged above an interface mechanism part. Thus, a substrate processing apparatus capable of reducing the area for setting the same is provided.

Abstract: A method for forming conductive lines such as interconnects and DRAM gate stacks. A blanket stack is formed on a substrate including a conductive diffusion barrier, a near noble metal such as cobalt, followed by a silicon layer and a top insulator layer. The blanket stack is patterned with resist to define the conductive lines. The stack is dry etched down to the near noble metal layer. The resist is then removed and the stack is annealed to react the near noble metal and silicon to form a conductive compound having fine grain size. The unreacted noble metal is then wet etched, using the conductive diffusion barrier as a wet etch stop. A further dry etch is then performed down to the substrate, using the top insulator layer as a mask. In this manner, only one mask is required to form the conductive line.

Abstract: A method for manufacturing a semiconductor device for use in a memory cell including the steps of preparing an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conductive plugs; patterning the insulating layer into a first predetermined configuration to form contact holes; forming a diffusion barrier layer on an entire surface including the contact holes; forming a seed layer on top of the diffusion barrier layer; forming a first conductive layer and a conductive plug on top of the seed layer; carrying out a thermal treatment for changing grains of the conductive plug into a granular type; removing the first conductive layer, the diffusion barrier layer, and the seed layer until a top surface of the insulating layer is exposed; forming a second conductive layer on the conductive plug and the diffusion barrier layer; patterning the second conductive layer into a second predetermined configura

Abstract: A method for forming a void-free epitaxial cobalt silicide (CoSi2) layer on an ultra-shallow source/drain junction. A patterned silicon structure is cleaned using HF. A first titanium layer, a cobalt layer, and a second titanium layer are successively formed on the patterned silicon substrate. The patterned silicon substrate is annealed at a temperature of between about 550° C. and 580° C. in a nitrogen ambient at atmospheric pressure; whereby the cobalt migrates downward and reacts with the silicon structure to form a CoSi2/CoSi layer, and the first titanium layer migrates upward and the first titanium layer and the second titanium layer react with the nitrigen ambient to form TiN. The TiN and unreacted cobalt are removed. The silicon structure is annealed at a temperature of between about 825° C. and 875° C. to convert the CoSi2/CoSi layer to a CoSi2 layer. The CoSi2 layer can optionally be implanted with impurity ions which are subsequently diffused to form ultra-shallow junctions.

Abstract: A method is provided for manufacturing an integrated circuit on a semiconductor wafer having a semiconductor substrate with a semiconductor device thereon. A dielectric layer is formed on the semiconductor substrate and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening. A seed layer is deposited on the barrier layer and securely bonds to the barrier layer. A conductor layer is deposited to fill the channel opening over the barrier layer. A planarization technique is used to planarize the barrier, seed layer, and conductor layers to be coplanar with the dielectric layer to form a conductor channel. The semiconductor wafer is then subjected to a two step timed anneal.

Abstract: A single-substrate-heat-processing method performs a reformation process for a tantalum oxide film on a wafer and a crystallization process for this film in this order. In the reformation process and crystallization process, a heater is set at preset temperatures substantially equal to each other, and a pressure in a process chamber is set at first and second process pressures different from each other. A density of a gas present between a support surface and the wafer is changed by using the pressure in the process chamber as a parameter, and thus a heat transfer rate between the support surface and wafer is changed, thereby setting a wafer temperature at first and second process temperatures different from each other.

Abstract: Disclosed is a method using the implantation of ionized titanium for the formation of an electrical contact having a metal silicide diffusion barrier. The electrical contact is created by the steps of etching a contact opening over an active region on an in-process integrated circuit wafer, implanting metal ions into the contact opening, and annealing the contact opening to form a titanium silicide layer at the bottom of the contact opening adjacent to the underlying active region. In a further step, a titanium nitride layer is formed on the surface of the contact opening above the metal silicide layer, and the remainder of the contact opening is then filled by depositing tungsten into the contact opening. The method is especially useful for forming contacts having a high aspect ratio and for forming self-aligned contacts as it is capable of forming a uniform silicide layer at the bottom of a narrow contact opening.

Abstract: A process for producing metal-containing layers, in particular metal-containing diffusion barriers, contact layers and/or antireflection layers. The process according to the invention has a first step in which a metal layer having a predetermined thickness at an elevated temperature is applied to a semiconductor structure. Next, the metal layer is cooled in a nitrogen-containing atmosphere, resulting in a metal nitride layer being formed.

Abstract: A method is provided for manufacturing an integrated circuit on a semiconductor wafer having a semiconductor substrate with a semiconductor device thereon. A dielectric layer is formed on the semiconductor substrate and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening. A seed layer is deposited on the barrier layer and securely bonds to the barrier layer. A conductor layer is deposited to fill the channel opening over the barrier layer. A planarization technique is used to planarize the barrier, seed layer, and conductor layers to be coplanar with the dielectric layer to form a conductor channel. The semiconductor wafer is then subjected to a two step timed anneal.

Abstract: A dual damascene manufacturing process, which is applicable on a dual damascene structure, is described. The etching stop layer at a bottom of the trench line is removed followed by a thermal treatment to smooth out the surface at the bottom of the trench line and in the via to form a larger and smoother opening at the top part of the via. The via and the trench line are then filled with a barrier layer and a metal layer.

Abstract: A substrate processing method of processing a surface of a substrate in manufacture of a semiconductor device, characterized by comprising a surface processing step for making a substance having an adsorption heat higher than that of an organic matter whose adsorption on the surface of the substrate, which has been cleaned, is undesirable, adsorbed on the surface of the substrate, and a film formation step for forming a thin film on the surface of the substrate which was processed in the above step.