Abstract: Disclosed is a heat treatment apparatus for performing a heat treatment on an object to-be-processed by a heater, which can inhibit variation in thermal histories among the objects to-be-processed. The heat treatment apparatus includes, among others, a correction part to correct a power control signal output from an adjusting unit so that a conduction rate of an AC voltage applied to a heater is decreased. Specifically, the correction is performed based on a value obtained by multiplying a first correction value with a second correction value, where the first correction value is generated according to a ratio of the voltage detection value of AC power source to a predetermined reference voltage, and the second correction value is generated according to a ratio of the resistance value of the heater to a predetermined reference resistance value.

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract: The present invention is related to the field of semiconductor processing and, more particularly, to the formation of low resistance layers on germanium substrates. One aspect of the present invention is a method comprising: providing a substrate on which at least one area of a germanium layer is exposed; depositing over the substrate and said germanium area a metal, e.g., Co or Ni; forming over said metal, a capping layer consisting of a silicon oxide containing layer, of a silicon nitride layer, or of a tungsten layer, preferably of a SiO2 layer; then annealing for metal-germanide formation; then removing selectively said capping layer and any unreacted metal, wherein the temperature used for forming said capping layer formation is lower than the annealing temperature.

Abstract: A method for heating a wafer that has at least one layer to be heated and a sub-layer. The method includes applying at least one light flux pulse to the wafer for heating the at least one layer in a manner such that the absorption coefficient of the flux by the layer is low as long as the temperature of the layer to be heated is in the low temperature range (PBT) but the absorption coefficient increases significantly when the temperature of the layer enters a high temperature range (PHT). Also, a sub-layer is selected such that the absorption coefficient of the applied light flux at the selected wavelength is high in the low temperature range (PBT) and the temperature enters the high temperature range (PHT) when the sub-layer is subjected to the light flux. The application of the light flux achieves improved heating of the wafer.

Abstract: In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.

Abstract: A thin film type varistor and a method of manufacturing the same are provided. The method includes: a depositing a first zinc oxide thin film at a low temperature through a sputtering method; and a forming a zinc oxide thin film for a varistor by treating the first zinc oxide thin film with heat at a low temperature in an environment in which an inert gas and oxygen are injected. Accordingly, it is possible to lower a processing temperature and simplify a manufacturing process while maintaining a varistor characteristic so as to be applied to a highly integrated circuit.

Abstract: A semiconductor substrate has a plurality of active device patterns. At least some of the active device patterns comprise doped regions. The substrate has a plurality of surface regions, including the active device patterns and un-patterned regions, with respectively different reflectances for light in a near infrared wavelength. A first difference is determined, between a largest reflectance at the near infrared wavelength and a smallest reflectance at the near infrared wavelength. A second infrared wavelength is determined, for which a second difference between a largest reflectances a smallest reflectance is substantially less than the first difference at the near infrared wavelength. A rapid thermal processing (RTP) spike annealing dopant activation step is performed on the substrate using a second light source providing light at the second wavelength.

Abstract: A method for making a semiconductor MOS device is provided. A gate structure is formed on a substrate. A source and a drain are formed in the substrate on both sides of the gate structure. The substrate is then subjected to a pre-amorphization implant (PAI) process. A transitional stress layer is then formed on the substrate. Thereafter, a laser anneal with a first temperature is performed. After the laser anneal, a rapid thermal process is performed with a second temperature that is lower than the first temperature. Subsequently, the transitional stress layer is removed.

Abstract: In the case of a lens array type homogenizer optical system, the incident angle and intensity of a laser beam 1 entering a large-sized lens (long-axis condenser lens 22) of a long-axis condensing optical system, which is provided on the rear side, are changed for every shot by performing laser irradiation while long-axis lens arrays 20a and 20b are reciprocated in a direction corresponding to a long axial direction of a linear beam (X-direction). Therefore, vertical stripes are significantly reduced. Further, the incident angle and intensity of a laser beam 1 entering a large-sized lens (projection lens 30) of a short-axis condensing optical system, which is provided on the rear side, are changed for every shot by performing laser irradiation while short-axis lens arrays 26a and 26b are reciprocated in a direction corresponding to a short axial direction of a linear beam (Y-direction). Therefore, horizontal stripes are significantly reduced.

Abstract: The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput.

Abstract: A method of forming a multi-doped junction is disclosed. The method includes providing a first substrate and a second substrate. The method also includes depositing a first ink on a first surface of each of the first substrate and the second substrate, the first ink containing a first set of nanoparticles and a first set of solvents, the first set of nanoparticles containing a first concentration of a first dopant. The method further includes depositing a second ink on a second surface of each of the first substrate and the second substrate, the second ink containing a second set of nanoparticles and a second set of solvents, the second set of nanoparticles containing a second concentration of a second dopant. The method also includes placing the first substrate and the second substrate in a back to back configuration; and heating the first substrate and the second substrate in a first drive-in ambient to a first temperature and for a first time period.

Abstract: A method of manufacturing a flash memory device and devices thereof, which may be capable of preventing damage to a gate. A method of manufacturing a flash memory device may include preparing a semiconductor substrate having an active region defined by a device separator. A method of manufacturing a flash memory device may include forming a floating gate, a oxide-nitride-oxide (ONO) layer and/or a control gate layer on and/or over a substrate. A method of manufacturing a flash memory device may include forming a low temperature oxide (LTO) film on and/or over a control gate, etching a LTO film to expose a desired part of a control gate, using a LTO film as a mask to etch a desired part of each of a floating gate layer, a ONO layer and/or a control gate to form a gate pattern, and/or substantially removing a LTO film by wet etching.

Abstract: A method of depositing a metal film on a substrate with patterned features includes placing a substrate with patterned features into a photo-induced chemical vapor deposition (PI-CVD) process chamber. The method also includes depositing a metal film by PI-CVD to fill the patterned features from bottom up.

Abstract: The invention provides a method for manufacturing a semiconductor device that comprises placing a metallic gate layer over a gate dielectric layer where the metallic gate layer has a crystallographic orientation, and re-orienting the crystallographic orientation of the metallic gate layer by subjecting the metallic gate layer to a hydrogen anneal.

Abstract: Disclosed herein is a rapid annealing method in a mixed structure composed of a heat treatment-requiring material, dielectric layer and conductive layer, comprising that during rapid annealing on a predetermined part of the heat treatment-requiring material, by instantaneously generated intense heat due to Joule heating by application of an electric field to the conductive layer, the potential difference between the heat treatment-requiring material and the conductive layer is set lower than the dielectric break-down voltage of the dielectric layer, thereby preventing generation of arc by dielectric breakdown of the dielectric layer during the annealing.

Abstract: The present invention provides a method for forming a self-aligned Ni alloy silicide contact. The method of the present invention begins by first depositing a conductive Ni alloy with Pt and optionally at least one of the following metals Pd, Rh, Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W or Re over an entire semiconductor structure which includes at least one gate stack region. An oxygen diffusion barrier comprising, for example, Ti, TiN or W is deposited over the structure to prevent oxidation of the metals. An annealing step is then employed to cause formation of a NiSi, PtSi contact in regions in which the metals are in contact with silicon. The metal that is in direct contact with insulating material such as SiO2 and Si3N4 is not converted into a metal alloy silicide contact during the annealing step A. selective etching step is then performed to remove unreacted metal from the sidewalls of the spacers and trench isolation regions.

Abstract: A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation.

Abstract: In one aspect, the present invention provides a silicon photodetector having a surface layer that is doped with sulfur inclusions with an average concentration in a range of about 0.5 atom percent to about 1.5 atom percent. The surface layer forms a diode junction with an underlying portion of the substrate. A plurality of electrical contacts allow application of a reverse bias voltage to the junction in order to facilitate generation of an electrical signal, e.g., a photocurrent, in response to irradiation of the surface layer. The photodetector exhibits a responsivity greater than about 1 A/W for incident wavelengths in a range of about 250 nm to about 1050 nm, and a responsivity greater than about 0.1 A/W for longer wavelengths, e.g., up to about 3.5 microns.

Abstract: An object is to provide a single crystal semiconductor layer with extremely favorable characteristics without performing CMP treatment or heat treatment at high temperature. Further, an object is to provide a semiconductor substrate (or an SOI substrate) having the above single crystal semiconductor layer. A first single crystal semiconductor layer is formed by a vapor-phase epitaxial growth method on a surface of a second single crystal semiconductor layer over a substrate; the first single crystal semiconductor layer and a base substrate are bonded to each other with an insulating layer interposed therebetween; and the first single crystal semiconductor layer and the second single crystal semiconductor layer are separated from each other at an interface therebetween so as to provide the first single crystal semiconductor layer over the base substrate with the insulating layer interposed therebetween. Thus, an SOI substrate can be manufactured.

Abstract: The present disclosure is related to a method for determining time to failure characteristics of a microelectronics device. A test structure, being a parallel connection of a plurality of such on-chip interconnects, is provided. Measurements are performed on the test structure under test conditions for current density and temperature. The test structure is arranged such that failure of one of the on-chip interconnects within the parallel connection changes the test conditions for at least one of the other individual on-chip interconnects of the parallel connection. From these measurements, time to failure characteristics are determined, whereby the change in the test conditions is compensated for.

Abstract: A process for the preparation of low resistivity arsenic or phosphorous doped (N+/N++) silicon wafers which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, reliably form oxygen precipitates.

Abstract: A method for annealing a semiconductor device having at least one polysilicon region formed on a substrate, comprises growing dielectric material on the substrate adjacent to the polysilicon region. The method continues by polishing a surface of the dielectric material and by depositing a layer of a semi-transparent material on both the surface of the dielectric material and the surface of the polysilicon region. The method concludes by annealing the semiconductor device.

Abstract: Disclosed is a method of providing a poly-Si layer used in fabricating poly-Si TFT's or devices containing poly-Si layers. Particularly, a method utilizing at least one metal plate covering the amorphous silicon layer or the substrate, and applying RTA (Rapid Thermal Annealing) for light illuminating process, then the light converted into heat by the metal plate will further be conducted to the amorphous silicon layer to realize rapid thermal crystallization. Thus the poly-Si layer of the present invention is obtained.

Abstract: A method for manufacturing a semiconductor device including a semiconductor substrate composed of silicon carbide, an upper surface electrode which contacts an upper surface of the substrate, and a lower surface electrode which contacts a lower surface of the substrate, the method including steps of: (a) forming an upper surface structure on the upper surface side of the substrate, and (b) forming a lower surface structure on the lower surface side of the substrate. The step (a) comprises steps of: (a1) depositing an upper surface electrode material layer on the upper surface of the substrate, the upper surface electrode material layer being a raw material layer of the upper surface electrode, and (a2) annealing the upper surface electrode material layer.

Abstract: A method for manufacturing a flash memory device is capable of controlling a phenomenon in which a length of the channel between a source and a drain is decreased due to undercut. The method includes forming a gate electrode comprising a floating gate, an ONO film and a control gate using a hard mask pattern over a semiconductor substrate, forming a spacer over the sidewall of the gate electrode, forming an low temperature oxide (LTO) film over the entire surface of the semiconductor substrate including the gate electrode and the spacer, etching the LTO film such that a top portion of the source/drain region and a top portion of the gate electrode are exposed, and removing the LTO film present over the sidewall of the gate electrode by wet-etching.

Abstract: In a method for producing a bonded wafer by bonding a wafer for active layer and a wafer for support layer and thinning the wafer for active layer according to the invention, oxygen ions are implanted into the wafer for active layer at a state of holding a temperature of the wafer for active layer below 200° C. under a dose of 5×1015 to 5×1016 atoms/cm2, whereby there can be obtained a bonded wafer being excellent in the thickness uniformity after thinning and having a dramatically improved surface roughness.

Abstract: The described embodiments of methods of bottom-up metal deposition to fill interconnect and replacement gate structures enable gap-filling of fine features with high aspect ratios without voids and provide metal films with good film quality. In-situ pretreatment of metal film(s) deposited by gas cluster ion beam (GCIB) allows removal of surface impurities and surface oxide to improve adhesion between an underlying layer with the deposited metal film(s). Metal films deposited by photo-induced chemical vapor deposition (PI-CVD) using high energy of low-frequency light source(s) at relatively low temperature exhibit liquid-like nature, which allows the metal films to fill fine feature from bottom up. The post deposition annealing of metal film(s) deposited by PI-CVD densifies the metal film(s) and removes residual gaseous species from the metal film(s). For advanced manufacturing, such bottom-up metal deposition methods address the challenges of gap-filling of fine features with high aspect ratios.

Abstract: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract: A system for and method of processing, i.e., annealing semiconductor materials. By controlling the time, frequency, variance of frequency, microwave power density, wafer boundary conditions, ambient conditions, and temperatures (including ramp rates), it is possible to repair localized damage lattices of the crystalline structure of a semiconductor material that may occur during the ion implantation of impurities into the material, electrically activate the implanted dopant, and substantially minimize further diffusion of the dopant into the silicon. The wafer boundary conditions may be controlled by utilizing susceptor plates (4) or a water chill plate (12). Ambient conditions may be controlled by gas injection (10) within the microwave chamber (3).

Abstract: A method of manufacturing a semiconductor device has forming a ferroelectric film over a substrate, placing the substrate having the ferroelectric film in a chamber substantially held in vacuum, introducing oxygen and an inert gas into the chamber, annealing the ferroelectric film in the chamber, and containing oxygen and the inert gas while the chamber is maintained sealed.

Abstract: An annealing method and apparatus for semiconductor manufacturing is described. The method and apparatus allows an anneal that can span a thermal budget and be tailored to a specific process and its corresponding activation energy. In some cases, the annealing method spans a timeframe from about 1 millisecond to about 1 second. An example for this annealing method includes a sub-second anneal method where a reduction in the formation of nickel pipes is achieved during salicide processing. In some cases, the method and apparatus combine the rapid heating rate of a sub-second anneal with a thermally conductive substrate to provide quick cooling for a silicon wafer. Thus, the thermal budget of the sub-second anneal methods may span the range from conventional RTP anneals to flash annealing processes (including duration of the anneal, as well as peak temperature). Other embodiments are described.

Abstract: Provided is a method for forming a buried word line in a semiconductor device. The method includes forming a trench by etching a pad layer and a substrate, forming a conductive layer to fill the trench, planarizing the conductive layer until the pad layer is exposed, performing an etch-back process on the planarized conductive layer, and performing an annealing process in an atmosphere of a nitride-based gas after at least one of the forming of the conductive layer, the planarizing of the conductive layer, and the performing of the etch-back process on the planarized conductive layer.

Abstract: The present process for rapidly heating and cooling a target material without damaging the substrate upon which it has been deposited. More specifically, target material is coated onto a first substrate. A self-propagating nanoenergetic material is selected that combusts at temperatures sufficient to change the target material and creates a flame front that propagates sufficiently quickly that the first substrate is not substantially heated. The nanoenergetic material is deposited on the target material, such that the target material and the nanoenergetic material is sandwiched between the substrate and the target material. The nanoenergetic material is ignited and the flame front of the nanoenergetic material is allowed to propagate over the second substrate and change the target material.

Abstract: A microelectromechanical device package with integral a heater and a method for packaging the microelectromechanical device are disclosed in this invention. The microelectromechanical device package comprises a first package substrate and second substrate, between which a microelectromechanical device, such as a micromirror array device is located. In order to bonding the first and second package substrates so as to package the microelectromechanical device inside, a sealing medium layer is deposited, and heated by the heater so as to bond the first and second package substrates together.

Abstract: (a1) A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. (a2) A first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. (a3) Conductive material essentially consisting of Cu is deposited on the first film to embed the conductive material in the concave portion. (a4) The semiconductor substrate is annealed. During the period until a barrier layer is formed having also a function of improving tight adhesion, it is possible to ensure sufficient tight adhesion of wiring members and prevent peel-off of the wiring members.

Abstract: A semiconductor substrate is irradiated with accelerated hydrogen ions, thereby forming a damaged region including a large amount of hydrogen. After a single crystal semiconductor substrate and a supporting substrate are bonded to each other, the semiconductor substrate is heated, so that the single crystal semiconductor substrate is separated in the damaged region. A single crystal semiconductor layer which is separated from the single crystal semiconductor substrate is irradiated with a laser beam. The single crystal semiconductor layer is melted by laser beam irradiation, whereby the single crystal semiconductor layer is recrystallized to recover its crystallinity and to planarized a surface of the single crystal semiconductor layer. After the laser beam irradiation, the single crystal semiconductor layer is heated at a temperature at which the single crystal semiconductor layer is not melted, so that the lifetime of the single crystal semiconductor layer is improved.

Abstract: A method of fabricating a copper interconnect on a substrate is disclosed in which the interconnect and substrate are subjected to a low temperature anneal subsequent to polarization of the interconnect and prior to deposition of an overlying dielectric layer. The low temperature anneal inhibits the formation of hillocks in the copper material during subsequent high temperature deposition of the dielectric layer. Hillocks can protrude through passivation layer, thus causing shorts within the connections of the semiconductor devices formed on the substrate. In one example, the interconnect and substrate are annealed at a temperature of about 200° C. for a period of about 180 seconds in a forming gas environment comprising hydrogen (5 parts per hundred) and nitrogen (95 parts per hundred).

Abstract: Ion implantation is carried out to form a p-well region and a source region in parts of a high resistance SiC layer on a SiC substrate, and a carbon film is deposited over the substrate. With the carbon film deposited over the substrate, annealing for activating the implanted dopant ions is performed, and then the carbon film is removed. Thus, a smooth surface having hardly any surface roughness caused by the annealing is obtained. Furthermore, if a channel layer is epitaxially grown, the surface roughness of the channel layer is smaller than that of the underlying layer. Since the channel layer having a smooth surface is provided, it is possible to obtain a MISFET with a high current drive capability.

Abstract: Source and drain electrodes are each formed by an alternation of first and second layers made from a germanium and silicon compound. The first layers have a germanium concentration comprised between 0% and 10% and the second layers have a germanium concentration comprised between 10% and 50%. At least one channel connects two second layers respectively of the source electrode and drain electrode. The method comprises etching of source and drain zones, connected by a narrow zone, in a stack of layers. Then superficial thermal oxidation of said stack is performed so a to oxidize the silicon of the germanium and silicon compound having a germanium concentration comprised between 10% and 50% and to condense the germanium Ge. The oxidized silicon of the narrow zone is removed and a gate dielectric and a gate are deposited on the condensed germanium of the narrow zone.

Abstract: A method of fabricating a dielectric layer is described. A substrate is provided, and a dielectric layer is formed over the substrate. The dielectric layer is performed with a nitridation process. The dielectric layer is performed with a first annealing process. A first gas used in the first annealing process includes inert gas and oxygen. The first gas has a first partial pressure ratio of inert gas to oxygen. The dielectric layer is performed with the second annealing process. A second gas used in the second annealing includes inert gas and oxygen. The second gas has a second partial pressure ratio of inert gas to oxygen, and the second partial pressure ratio is smaller than the first partial pressure ratio. At least one annealing temperature of the two annealing processes is equal to or greater than 950° C. The invention improves uniformity of nitrogen dopants distributed in dielectric layer.

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a high-k dielectric over a substrate, forming a first metal layer over the high-k dielectric, forming a second metal layer over the first metal layer, forming a first silicon layer over the second metal layer, implanting a plurality of ions into the first silicon layer and the second metal layer overlying a first region of the substrate, forming a second silicon layer over the first silicon layer, patterning a first gate structure over the first region and a second gate structure over a second region, performing an annealing process that causes the second metal layer to react with the first silicon layer to form a silicide layer in the first and second gate structures, respectively, and driving the ions toward an interface of the first metal layer and the high-k dielectric in the first gate structure.

Abstract: A semiconductor device of the present invention is manufactured by the following steps: forming a single-crystal semiconductor layer over a substrate having an insulating surface; irradiating a region of the single-crystal semiconductor layer with laser light; forming a circuit of a pixel portion using a region of the single-crystal semiconductor layer which is not irradiated with the laser light; and forming a driver circuit for driving the circuit of the pixel portion using the region of the single-crystal semiconductor layer which is irradiated with the laser light. Thus, a semiconductor device using a single-crystal semiconductor layer which is suitable for a peripheral driver circuit region and a single-crystal semiconductor layer which is suitable for a pixel region can be provided.

Abstract: A method of fabricating a semiconductor device includes depositing tungsten on an insulating layer in which a contact hole is formed by chemical vapor deposition (CVD), performing chemical mechanical planarization (CMP) on the tungsten to expose the insulating layer and form a tungsten contact plug, and performing rapid thermal oxidation (RTO) on the tungsten contact plug in an oxygen atmosphere such that the tungsten expands volumetrically into tungsten oxide (W?O?).

Abstract: A method for forming a device isolation structure of a semiconductor device using at least three annealing steps to anneal a flowable insulation layer is presented. The method includes the steps of forming a hard mask pattern on a semiconductor substrate having active regions exposing a device isolation region of the semiconductor substrate; etching the device isolation region of the semiconductor substrate exposed through the hard mask pattern, and therein forming a trench; forming a flowable insulation layer to fill a trench; first annealing the flowable insulation layer at least three times; second annealing the first annealed flowable insulation layer; removing the second annealed flowable insulation layer until the hard mask pattern is exposed; and removing the exposed hard mask pattern.

Abstract: Methods are provided for depositing a silicon carbide layer having significantly reduced current leakage. The silicon carbide layer may be a barrier layer or part of a barrier bilayer that also includes a barrier layer. Methods for depositing oxygen-doped silicon carbide barrier layers are also provided. The silicon carbide layer may be deposited by reacting a gas mixture comprising an organosilicon compound, an aliphatic hydrocarbon comprising a carbon-carbon double bond or a carbon-carbon triple bond, and optionally, helium in a plasma. Alternatively, the silicon carbide layer may be deposited by reacting a gas mixture comprising hydrogen or argon and an organosilicon compound in a plasma.

Abstract: A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.

Abstract: In a method for producing bases with external contacts for surface mounting on circuit mounts, bases with external contacts are electrodeposited on semiconductor wafers or semiconductor chips. Subsequently, electrodeposited bases with external contacts are heat treated on the semiconductor wafers or the semiconductor chips at temperatures below the melting temperature of the deposited contact base material. Thereafter, a so-called RTP process is carried out in the form of a high-temperature interval in which the melting temperature is reached. Subsequently, the surfaces of the bases with external contacts are wet etched, the overall method being terminated by a cooling and drying operation. The bases with external contacts thus produced can be reliably surface mounted on circuit mounts.

Abstract: In a method for producing a bonded wafer by bonding a wafer for active layer to wafer for support layer and then thinning the wafer for active layer, a terrace grinding for forming a terrace portion is carried out prior to a step of exposing the oxygen ion implanted layer to thereby leave an oxide film on a terrace portion of the wafer for support layer.

Abstract: An integrated circuit including an intrusion attack detection device. The device includes a single-piece formed of a conductive material and surrounded with an insulating material and includes at least one stretched or compressed elongated conductive track, connected to a mobile element, at least one conductive portion distant from said piece and a circuit for detecting an electric connection between the piece and the conductive portion. A variation in the length of said track in an attack by removal of the insulating material, causes a displacement of the mobile element until it contacts the conductive portion.

Abstract: A method for making an integrated circuit device includes forming at least one interconnect structure adjacent a substrate by forming at least one barrier layer, forming a doped copper seed layer on the at least one barrier layer, and forming a copper layer on the doped copper seed layer. The method may further include annealing the integrated circuit device after forming the copper layer to diffuse the dopant from the doped copper seed layer into grain boundaries of the copper layer. The doped copper seed layer may include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant to provide the enhanced electromigration resistance. Forming the copper layer may comprise plating the copper layer. In addition, forming the copper layer may comprise forming the copper layer to include at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium as a dopant.