Abstract: A multi-layer piezoelectric component includes a plurality of piezoelectric layers, a first inner electrode sheet, a second inner electrode sheet, a first outer electrode, and a second outer electrode. The piezoelectric layers are wound around an axis to form a laminar roll having first and second end faces transverse to the axis. The piezoelectric layers include at least one first layer and at least one second layer. Each of the first and second layers has opposite first and second edges respectively at the first and second end faces, and opposite inner and outer circumferential surfaces. The first and second inner electrode sheets respectively overlie the inner circumferential surfaces of the first and second layers. The first and second outer electrodes are respectively and electrically connected to the first and second inner electrode sheets.

Abstract: To form a wiring electrode having excellent contact function, in covering a contact hole formed in an insulting film, a film of a wiring material comprising aluminum or including aluminum as a major component is firstly formed and on top of the film, a film having an element belonging to 12 through 15 groups as a major component is formed and by carrying out a heating treatment at 400° C. for 0.5 through 2 hr in an atmosphere including hydrogen, the wiring material is provided with fluidity and firm contact is realized.

Abstract: A method of fabricating a MOS transistor by millisecond annealing. A semiconductor substrate with a gate stack comprising a gate electrode overlying a gate dielectric layer on a top surface of a semiconductor substrate is provided. At least one implanting process is performed to form two doped regions on opposite sides of the gate electrode. Millisecond annealing activates dopants in the doped regions. The millisecond anneal includes rapid heating and rapid cooling within 1 to 50 milliseconds.

Abstract: An Al3Ti film having a large amount of dissolved Si is deposited on a semiconductor substrate to form a laminate with an Al wiring film, and heat treatment is performed at a temperature of at least 400° C., to thereby absorb excessive Si into the Al3Ti film and so prevent the occurrence of Si nodules. By depositing Al film at a temperature of at least 400° C. at the time of depositing the Al wiring film on the Al3Ti film, excessive Si is caused to be absorbed in the Al3Ti film. Further, at the time of depositing a Ti film on the semiconductor substrate and depositing the Al wiring film, the Al film is deposited at a temperature of a least 400° C., there is reaction between the Ti film within the laminate, causing an Al3Ti film to be produced, and excessive Si is absorbed in the Al3 Ti film produced.

Abstract: This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.

Abstract: A method of forming a conductor structure on a surface of a wafer is provided. The surface of the wafer includes cavities separated by field regions. Initially, a barrier layer is deposited on the surface that includes cavities separated by field regions. A thin seed layer with a substantially uniform thickness is deposited on the barrier layer. The barrier layer and the seed layer portions in the cavities occupy less than 30% of the volume of each cavity. The remaining volume of each cavity is filled with a conductive material which is formed on the seed layer. The conductive layer has a substantially small thickness. After forming the conductive layer, the wafer is annealed to increase grain size in the conductive layer and the seed layer.

Abstract: A novel method for preventing the formation of voids in metal interconnects fabricated on a wafer, particularly during a thermal anneal process, is disclosed. The method includes fabricating metal interconnects between metal lines on a wafer. During a thermal anneal process carried out to reduce electrical resistance of the interconnects, the wafer is positioned in spaced-apart relationship to a wafer heater. This spacing configuration facilitates enhanced stabilility and uniformity in heating of the wafer by reducing the presence of particles on and providing a uniform flow of heated air or gas against and the wafer backside. This eliminates or at least substantially reduces the formation of voids in the interconnects during the anneal process.

Abstract: A method for forming a stabilized metal silicide film, e.g., contact (source/drain or gate), that does not substantially agglomerate during subsequent thermal treatments, is provided. In the present invention, ions that are capable of attaching to defects within the Si-containing layer are implanted into the Si-containing layer prior to formation of metal silicide. The implanted ions stabilize the film, because the implants were found to substantially prevent agglomeration or at least delay agglomeration to much higher temperatures than in cases in which no implants were used.

Abstract: Numerous embodiments of a method and apparatus for a sacrificial annealing layer are disclosed. In one embodiment, a method of forming a sacrificial annealing layer for a semiconductor device comprises forming one or more sacrificial layers on at least a portion of the top surface of a semiconductor device, annealing at least a portion of the device, and removing a substantial portion of the one or more sacrificial layers, where the removing results in no substantial physical alterations to the device.

Abstract: Disclosed herein is a method of improving residue and thermal characteristics of a semiconductor device. The method comprises the steps of a) depositing nickel and cobalt layers sequentially on a silicone substrate having a transistor formed thereon, b) depositing a capping layer on the cobalt layer, c) forming a silicide layer from the cobalt and nickel layers deposited on the silicone substrate by heat treatment, and d) wet etching to remove a residue. As the silicide layer is formed by additionally deposing the capping layer of titanium nitride on triple layers of silicone, cobalt and nickel, thermal stability for a thermal process performed when forming the silicide is ensured, and as resistance caused by an etchant is eliminated by the subsequent etching process, the residue is completely removed.

Abstract: A method of annealing a metal layer on a substrate in a chamber is provided. The method comprises positioning a substrate with a metal layer thereon in a chamber, removing atmospheric gases from the chamber, providing process gas to the chamber, and annealing the metal layer at a temperature greater than about 80 degrees Celsius. Also provided is a method of forming a feature on a substrate. The method comprises depositing a dielectric layer on the substrate, forming at least one opening within the dielectric layer, depositing a metal layer in the opening, positioning the substrate in an annealing chamber, removing atmospheric gases from the annealing chamber, providing process gas to the annealing chamber, and annealing the metal layer at temperature greater than about 80 degrees Celsius.

Abstract: A process for forming a metal suicide gate in an FET device, where the suicide is self-forming (that is, formed without the need for a separate metal/silicon reaction step), and no CMP or etchback of the silicon material is required. A first layer of silicon material (polysilicon or amorphous silicon) is formed overlying the gate dielectric; a layer of metal is then formed on the first layer, and a second layer of silicon on the metal layer. A high-temperature (>700° C.) processing step, such as source/drain activation anneal, is subsequently performed; this step is effective to form a silicide layer above the gate dielectric by reaction of the metal with silicon in the first layer. A second high-temperature processing step (such as source/drain silicidation) may be performed which is effective to form a second silicide layer from silicon in the second layer.

Abstract: A method for conductive line of semiconductor device is disclosed. A cobalt silicide layer is formed on an impurity junction region exposed through a contact hole. The cobalt silicide layer stabilizes a contact resistance so that the contact resistance of the impurity junction region does not vary in subsequent thermal processes.

Abstract: A capping layer (118) is used during an anneal to form fully silicided NiSi gate electrodes (120). The capping layer (118) comprises a material with an affinity for boron, such as TiN. The capping layer (118) serves as a boron trap that reduces the interface boron concentration for PMOS transistors without reducing the interface arsenic concentration for NMOS transistors.

Abstract: A method of manufacturing a semiconductor device having an interconnection part formed of multiple carbon nanotubes is disclosed. The method includes the steps of (a) forming a growth mode control layer controlling the growth mode of the carbon nanotubes, (b) forming a catalyst layer on the growth mode control layer, and (c) causing the carbon nanotubes to grow by heating the catalyst layer by thermal CVD so that the carbon nanotubes serve as the interconnection part. The growth mode control layer is formed by sputtering or vacuum deposition in an atmospheric gas, using a metal selected from a group of Ti, Mo, V, Nb, and W. The growth mode is controlled in accordance with a predetermined concentration of oxygen gas of the atmospheric gas.

Abstract: Apparatus and method for treating a surface of a substrate for electrolytic or electroless plating of metals in integrated circuit manufacturing. In one embodiment the method includes forming a barrier layer on a substrate. A metal-seed layer is then formed on the barrier layer. The method continues by performing in situ surface treatment of the metal-seed layer to form a passivation layer on the metal-seed layer. In another embodiment of a method of this invention, a substrate is provided into an electroplating tool chamber. The substrate has a barrier layer formed thereon, a metal seed layer formed on the barrier layer and a passivation layer formed over the metal seed layer. The method continues by annealing the substrate in forming gas to reduce the passivation layer. A conductive material is deposited on the substrate using an electrolytic plating or electroless plating process.

Abstract: The present invention provides a technique for forming a metal silicide, such as a cobalt disilicide, even at extremely scaled device dimensions without unduly degrading the film integrity of the metal silicide. To this end, an ion implantation may be performed, advantageously with silicon, prior to a final anneal cycle, thereby correspondingly modifying the grain structure of the precursor of the metal silicide.

Abstract: Conductive contacts in a semiconductor structure, and methods for forming the conductive components are provided. The method comprises depositing a conductive material over a substrate to fill a contact opening, removing excess material from the substrate leaving the contact within the opening, and then heating treating the contact at a high temperature, preferably with a rapid thermal anneal process, in a reactive gas to remove an undesirable component from the contact, for example, thermal annealing a TiCl4-based titanium nitride in ammonia to remove chlorine from the contact, which can be corrosive to an overlying aluminum interconnect at a high concentration. The contacts are useful for providing electrical connection to active components in integrated circuits such as memory devices. In an embodiment of the invention, the contacts comprise boron-doped and/or undoped TiCl4-based titanium nitride having a low concentration of chlorine.

Abstract: The method for fabricating a semiconductor device comprises the steps of: forming a dummy electrode 22n and a dummy electrode 22p; forming a metal film 32 on the dummy electrode 22p; conducting a thermal treatment at a first temperature to substitute the dummy electrode 22n with an electrode 34a of a material containing the constituent material of the metal film 32; forming a metal film 36 on the dummy electrode 22n; and conducting a thermal treatment at a second temperature, which is lower than the first temperature and at which an interdiffusion of constituent materials between the electrode 34a and the metal film 36 does not take place, to substitute the second dummy electrode with an electrode 34b of a material containing the constituent material of the metal film 36.

Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed around the gate. Source/drain junctions are formed in the semiconductor substrate. An intermediate phase silicide is formed on the source/drain regions and on the gate. The sidewall spacer is removed. A final phase silicide is formed from the intermediate phase silicide. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed in the interlayer dielectric to the final phase silicide.

Abstract: A method of fabricating a resistor in which the resistance value of the resistor is measured and adjusted after silicidation is provided. The method of the present invention begins with first providing at least one resistor, e.g., polysilicon, having a resistance value on a surface of a semiconductor substrate. The at least one resistor has been subjected to a silicidation process. Next, the resistance value of the at least one resistor is measured to determine the actual resistance of the resistor after silicidation. After the measuring step, the resistance of the resistor is adjusted to achieve a desired resistance value. The adjusting may include a post silicidation rapid thermal anneal and/or a post silicidation ion implantation and a low temperature rapid thermal anneal step.

Abstract: An alloying method includes the steps of forming a metal layer on a semiconductor having been transferred to a material having a low thermal conductivity, and alloying an interface between the semiconductor and the metal layer by irradiating the interface with a laser beam having a wavelength absorbable in at least one of the semiconductor and the metal layer. The irradiation energy of the laser beam is set in a range of 20 to 100 mJ/cm2. The material having a low thermal conductivity is a resin or amorphous silicon. According to the alloying method using laser irradiation, since the entire semiconductor is not heated and only a necessary portion is locally heated, the necessary portion can be readily alloyed to be converted into an ohmic contact without exerting adverse effect on characteristics of the semiconductor device.

Abstract: A semiconductor comprises a substrate including a single crystal semiconductor region, and a pattern including a line pattern provided on the substrate, the line pattern having a longitudinal direction differing from a crystal orientation of the single crystal semiconductor region.

Abstract: Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat.

Abstract: A method of production of a multilayer ceramic capacitor or other multilayer ceramic electronic device with few structural defects and improved highly accelerated life, that is, a method of production of a multilayer ceramic electronic device having a firing step of firing a stack comprised of a dielectric layer paste and an internal electrode layer paste including a base metal alternately arranged in a plurality of layers, a first annealing step of annealing, at a temperature T1 of 600 to 900° C., the stack after firing and a second annealing step of annealing, at a temperature T2 of 900 to 1200° C. (however, excluding 900° C.), the stack after said first annealing.

Abstract: A breakdown voltage of a capacitive element is improved by re-crystallizing a tungsten silicide film under a dielectric film. In forming the capacitive element which uses a polycrystalline silicon film and the tungsten silicide film as a lower electrode, the tungsten silicide film is re-crystallized by heating using an RTA (Rapid Thermal Annealing) system before forming a silicon oxide film used as the dielectric film. By doing so, an interface between the silicon oxide film and the tungsten silicide film is prevented from becoming uneven and a breakdown voltage of the dielectric film is improved drastically. Thus an amount of electric charge stored in the capacitive element is increased as well as it is made possible that the capacitive element is applied to a semiconductor device operating at higher voltage.

Abstract: The present invention can protect from degradation of product reliability of a semiconductor caused during formation of a salicide suppression layer. In order to achieve this, unlike the conventional method in which the sidewall spacer of the gate electrode and the salicide suppression layer in the non-salicide region are formed through two etching processes, the salicide suppression layer and the sidewall spacer are formed at the same time with one etching process after the salicide suppression substance and the sidewall spacer substance are sequentially formed in the present invention, such that it is possible to efficiently prevent an undercut effect from occurring at the spacer side during the etching process for forming the salicide suppression layer, and to effectively prevent the surface of the semiconductor substrate from being damaged.

Abstract: A method for forming a titanium nitride layer. A pre-heating step is performed, wherein a substrate is placed in a chamber comprising inert gas with a pre-heating pressure between 0.1˜3 torr. A TiN deposition step is then performed, wherein the substrate is placed in a reactive gas at least comprising NH3 and TiCl4, and the first TiN deposition step has a reactive pressure of more than 5 torr and a reactive temperature of more than 500° C.

Abstract: An alloying method includes the steps of forming a metal layer on a semiconductor having been transferred to a material having a low thermal conductivity, and alloying an interface between the semiconductor and the metal layer by irradiating the interface with a laser beam having a wavelength absorbable in at least one of the semiconductor and the metal layer. The irradiation energy of the laser beam is set in a range of 20 to 100 mJ/cm2. The material having a low thermal conductivity is a resin or amorphous silicon. According to the alloying method using laser irradiation, since the entire semiconductor is not heated and only a necessary portion is locally heated, the necessary portion can be readily alloyed to be converted into an ohmic contact without exerting adverse effect on characteristics of the semiconductor device.

Abstract: An alloying method includes the steps of forming a metal layer on a semiconductor having been transferred to a material having a low thermal conductivity, and alloying an interface between the semiconductor and the metal layer by irradiating the interface with a laser beam having a wavelength absorbable in at least one of the semiconductor and the metal layer. The irradiation energy of the laser beam is set in a range of 20 to 100 mJ/cm2. The material having a low thermal conductivity is a resin or amorphous silicon. According to the alloying method using laser irradiation, since the entire semiconductor is not heated and only a necessary portion is locally heated, the necessary portion can be readily alloyed to be converted into an ohmic contact without exerting adverse effect on characteristics of the semiconductor device.

Abstract: A tunnel dielectric layer is formed on a semiconductor device. A floating gate layer is formed on the tunnel dielectric layer. An intergate dielectric layer (ONO layer) is formed on the floating gate layer. An in-situ doped silicon is deposited on the intergate dielectric layer to form a control gate layer and then, an annealing is carried out. The control gate layer, the intergate dielectric layer, and the floating gate layer are patterned through a photolithographic process. The phase transformation of the control gate silicon layer does not occur during a subsequent gate oxidation process to reduce the thickness variation of the ONO layer, thereby improving endurance and bake retention characteristics of the semiconductor device.

Abstract: This invention relates to a process for treatment of a multi-layer wafer with materials having differential thermal characteristics, the process comprising a high temperature heat treatment step that can generate secondary defects, characterised in that this process includes a wafer surface preparation step before the high temperature heat treatment step.

Abstract: A method (and resulting structure) for fabricating a silicide for a semiconductor device, includes depositing a metal or an alloy thereof on a silicon substrate, reacting the metal or the alloy to form a first silicide phase, etching any unreacted metal, depositing a silicon cap layer over the first silicide phase, reacting the silicon cap layer to form a second silicide phase, for the semiconductor device, and etching any unreacted silicon. The substrate can be either a silicon-on-insulator (SOI) substrate or a bulk silicon substrate.

Abstract: The present invention relates to the reduction of critical dimensions and the reduction of feature sizes in manufacturing integrated circuits. Specifically, the method controls photoresist flow rates to develop critical dimensions beyond the resolution limits of the photoresist material used, and the limits of lithographic tool sets. The post exposure and developed resist pattern is exposed to a solvent prior to a bake or reflow process. Exposure to the solvent lowers the molecular weight of the resist material, modifying the resist material's reflow rate. The post-exposure resist is then easier to control during a subsequent reflow process to reduce the hole or line size of the patterned resist.

Abstract: The present invention provides a method for forming a gate oxide film of a semiconductor device including the steps of; forming a gate oxide film and a polysilicon film sequentially on a semiconductor substrate; performing a nitrogen ion implantation process after the formation of the gate oxide film and the polysilicon film; performing a thermal treatment process to form barrier layers by combination of oxides and nitrogen at an interface between the semiconductor substrate and the gate oxide film, and at an interface between the gate oxide film and the polysilicon film; and forming a nitride on the polysilicon film.

Abstract: A method for reducing peeling of a cross-linked polymer passivation layer in a solder bump formation process including providing a multi-level semiconductor device formed on a semiconductor process wafer having an uppermost surface comprising a metal bonding pad in electrical communication with underlying device levels; forming a layer of resinous pre-cursor polymeric material over the process surface said resinous polymeric material having a glass transition temperature (Tg) upon curing; subjecting the semiconductor process wafer to a pre-curing thermal treatment temperature below Tg for a period of time; and, subjecting the semiconductor process wafer to at least one subsequent thermal treatment temperature above Tg for a period of time to form an uppermost passivation layer.

Abstract: After carrying an LCD substrate in a reaction container of a heat treatment unit, blowing a previously heated helium gas from a gas supply part, which opposes to the surface of the LCD substrate, over the entire surface of the LCD substrate. The temperature of the LCD substrate is raised by radiation heat of a heater and heat exchange with the helium gas. After performing CVD or annealing in the reaction container, cooling the LCD substrate by blowing a gas for heat exchange having a temperature about a room temperature from the gas supply part over the entire surface of the LCD substrate. Return the cooled LCD substrate to a carrier in the carrier chamber via a conveyance chamber.

Abstract: A semiconductor device having stable device characteristics, in which variation in contact resistance between silicon and poly-silicon or between poly-silicon and poly-silicon is reduced. In a cleaning process before forming an upper layer poly-silicon film, a treatment is conducted to form a thin uniform oxide film on the surface of silicon. After forming the upper layer poly-silicon film 11, a removed portion is uniformly formed on the thin uniform oxide film by applying a short time, high temperature annealing treatment.

Abstract: The inventor devised methods of forming interconnects that result in conductive structures with fewer voids and thus reduced electrical resistance. One embodiment of the method starts with an insulative layer having holes and trenches, fills the holes using a selective electroless deposition, and fills the trenches using a blanket deposition. Another embodiment of this method adds an anti-bonding material, such as a surfactant, to the metal before the electroless deposition, and removes at least some the surfactant after the deposition to form a gap between the deposited metal and interior sidewalls of the holes and trenches. The gap serves as a diffusion barrier. Another embodiments leaves the surfactant in place to serve as a diffusion barrier. These and other embodiments ultimately facilitate the speed, efficiency, or fabrication of integrated circuits.

Abstract: A method of manufacturing an integrated circuit having a gate structure above a substrate that includes germanium utilizes at least one layer as a seal. The layer advantageously can prevent back sputtering and outdiffusion. A transistor can be formed in the substrate by doping through the layer. Another layer can be provided below the first layer. Layers of silicon dioxide, silicon carbide, silicon nitride, titanium, titanium nitride, titanium/titanium nitride, tantalum nitride, and silicon carbide can be used.

Abstract: The present invention is directed to an apparatus and process for heating and cooling semiconductor wafers in thermal processing chambers. In particular, the apparatus of the present invention includes a cooling device for actively cooling the wafers after the wafers have been heated. During use, the cooling device can be movable towards and away from a wafer placed in the chamber for selectively cooling the wafer at desired times. In an alternative embodiment, a gas can be directed towards the wafer for rapidly reducing the temperature of the wafer at the completion of the process. Alternatively, the wafer can be lowered to close proximity of a cooling member to achieve active and selective cooling.

Abstract: Disclosed is a method of manufacturing the semiconductor devices. The method comprising the steps of forming a gate electrode on a semiconductor substrate, depositing an oxide film for a spacer on the gate electrode, implementing an anisotropic dry etch process for the oxide film for the spacer to form spacers at the sidewalls of the gate electrode, and implementing a rapid thermal annealing process for the spacers under an oxygen atmosphere in order to segregate hydrogen contained within the spacers toward the surface. Therefore, hydrogen contained within the spacer oxide film is not diffused into the tunnel oxide film and the film quality of the tunnel oxide film is thus improved. As a result, program or erase operation characteristics of the flash memory device and a retention characteristic of the flash memory device could be improved.

Abstract: A method for forming a titanium nitride layer. The method includes the steps of exposing a semiconductor substrate to a reactive gas containing TiCl4 and NH3 for a first deposition to form a layer of titanium nitride on the substrate, at reaction pressure less than 1 torr and temperature less than 500° C.; placing the semiconductor substrate in NH3 gas for a first annealing step, at pressure between 1 and 3 torr; exposing the semiconductor substrate to a reactive gas comprising TiCl4 and NH3 for a second deposition, at pressure exceeding 5 torr and temperature exceeding 500° C.; and subjecting the semiconductor substrate to a second annealing step in NH3 gas, at pressure exceeding 5 torr.

Abstract: Provided is a manufacturing method of a semiconductor device which comprises (a) depositing a first insulating film over a wafer, (b) forming an interconnect opening in the first insulating film, (c) forming, in the interconnect opening, an interconnect having a conductor film comprised mainly of copper, (d) forming a taper at a corner of said conductor film on the opening side of the interconnect opening, and (e) depositing a second insulating film over the first insulating film and interconnect. The present invention makes it possible to improve dielectric breakdown strength between interconnects each having a main conductor film comprised mainly of copper.

Abstract: In a method for forming a gate electrode having an excellent sidewall profile, after a gate structure is formed on a substrate, a first oxide film is formed on a sidewall of the gate structure and on the substrate by re-oxidizing the gate structure and the substrate under an atmosphere including an oxygen gas and an inert gas. The gate structure has a gate oxide film pattern, a polysilicon film pattern and a metal silicide film pattern. A portion of the first oxide film formed on a sidewall of the polysilicon film pattern has a thickness substantially identical to that of a portion of the first oxide film formed on a sidewall of the metal silicide film pattern. A failure of a semiconductor device having the gate electrode can be minimized because the gate electrode has an improved sidewall profile.

Abstract: A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.

Abstract: A method is provided for eliminating uneven heating of substrate active areas during laser thermal annealing (LTA) due to variations in gate electrode density. Embodiments include adding dummy structures, formed simultaneously with the gate electrodes, to “fill in” the spaces between isolated gate electrodes, such that the spacing between the gate electrodes and the dummy structures is the same as the spacing between the densest array of device structures on the substrate surface. Since the surface features (i.e., the gate electrodes and the dummy structures) appear substantially uniform to the LTA laser, the laser radiation is uniformly absorbed by the substrate, and the substrate surface is evenly heated.

Abstract: There is provided a method of fabricating a gate electrode, including the steps of (a) forming a gate oxide film at a surface of a semiconductor substrate, (b) forming a multi-layered structure on the gate oxide film, the multi-layered structure including a polysilicon layer formed on the gate oxide film, a refractive metal silicide layer formed on the polysilicon layer, and a silicon nitride layer formed on the refractive metal silicide layer, (c) thermally annealing the multi-layered structure in a nitrogen atmosphere to thereby form a silicon nitride film on sidewalls of the polysilicon layer and the refractive metal silicide layer, and (d) oxidizing the semiconductor substrate and the multi-layered structure.

Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.

Abstract: Disclosed herein is a method for manufacturing a zinc oxide semiconductor. The method comprises the steps of forming a zinc oxide thin film including a group V element as a dopant on a substrate by using a zinc oxide compound containing a group V element or an oxide thereof, charging the substrate having the zinc oxide thin film formed thereon into a chamber for thermal annealing, and thermal annealing the substrate in the chamber to activate the dopant, thereby changing the zinc oxide thin film exhibiting n-type electrical properties or insulator properties to a zinc oxide thin film exhibiting p-type electrical properties.